def create(self, dep_file): import re from vlog_parser import VerilogParser from vhdl_parser import VHDLParser if isinstance(dep_file, VHDLFile): return VHDLParser(dep_file) elif isinstance(dep_file, VerilogFile) or isinstance(dep_file, SVFile): vp = VerilogParser(dep_file) for d in dep_file.include_paths: vp.add_search_path(d) return vp else: raise ValueError("Unecognized file format : %s" % dep_file.file_path)
def create(self, dep_file): import re from vlog_parser import VerilogParser from vhdl_parser import VHDLParser if isinstance(dep_file, VHDLFile) : return VHDLParser(dep_file) elif isinstance(dep_file, VerilogFile) or isinstance(dep_file, SVFile) : vp = VerilogParser(dep_file) for d in dep_file.include_paths: vp.add_search_path(d) return vp else : raise ValueError("Unecognized file format : %s" % dep_file.file_path)
def create(self, dep_file): import re from vlog_parser import VerilogParser from vhdl_parser import VHDLParser extension = re.match(re.compile(".+\.(\w+)$"), dep_file.file_path) if not extension: raise ValueError("Unecognized file format : %s" % dep_file.file_path) extension = extension.group(1).lower() if extension in ["vhd", "vhdl"]: return VHDLParser(dep_file) elif extension in ["v", "sv"]: vp = VerilogParser(dep_file) for d in dep_file.include_paths: vp.add_search_path(d) return vp
def create(self, filename, search_path): import re from vlog_parser import VerilogParser from vhdl_parser import VHDLParser extension=re.match(re.compile(".+\.(\w+)$"), filename) if(not extension): throw ("Unecognized file format : %s" % filename); extension = extension.group(1).lower() if(extension in ["vhd", "vhdl"]): return VHDLParser(); elif(extension in ["v", "sv"]): vp = VerilogParser(); for d in search_path: vp.add_search_path(d) return vp
def create(self, filename, search_path): import re from vlog_parser import VerilogParser from vhdl_parser import VHDLParser extension = re.match(re.compile(".+\.(\w+)$"), filename) if (not extension): throw("Unecognized file format : %s" % filename) extension = extension.group(1).lower() if (extension in ["vhd", "vhdl"]): return VHDLParser() elif (extension in ["v", "sv"]): vp = VerilogParser() for d in search_path: vp.add_search_path(d) return vp