Пример #1
0
    def run(self):
        pool = self.modules_pool
        self._check_all_fetched_or_quit()

        logging.info("Merging all cores into one source file per language.")
        flist = pool.build_global_file_set()
#        if not os.path.exists(self.options.merge_cores):
 #           os.makedirs(self.options.merge_cores)
        base = self.options.dest

        f_out = open(base+".vhd", "w")
        f_out.write("\n\n\n\n")
        f_out.write("------------------------------ WARNING -------------------------------\n")
        f_out.write("-- This code has been generated by hdlmake --merge-cores option     --\n")
        f_out.write("-- It is provided for your convenience, to spare you from adding    --\n")
        f_out.write("-- lots of individual source files to ISE/Modelsim/Quartus projects --\n")
        f_out.write("-- mainly for Windows users. Please DO NOT MODIFY this file. If you --\n")
        f_out.write("-- need to change something inside, edit the original source file   --\n")
        f_out.write("-- and re-genrate the merged version!                               --\n")
        f_out.write("----------------------------------------------------------------------\n")
        f_out.write("\n\n\n\n")

        for vhdl in flist.filter(VHDLFile):
            f_out.write("\n\n---  File: %s ----\n" % vhdl.rel_path())
            f_out.write("---  Source: %s\n" % vhdl.module.url)
            if vhdl.module.revision:
                f_out.write("---  Revision: %s\n" % vhdl.module.revision)
            f_out.write("---  Last modified: %s\n" % time.ctime(os.path.getmtime(vhdl.path)))
            f_out.write(open(vhdl.rel_path(), "r").read()+"\n\n")
                #print("VHDL: %s" % vhdl.rel_path())
        f_out.close()

        f_out = open(base+".v", "w")

        f_out.write("\n\n\n\n")
        f_out.write("////////////////////////////// WARNING ///////////////////////////////\n")
        f_out.write("// This code has been generated by hdlmake --merge-cores option     //\n")
        f_out.write("// It is provided for your convenience, to spare you from adding    //\n")
        f_out.write("// lots of individual source files to ISE/Modelsim/Quartus projects //\n")
        f_out.write("// mainly for Windows users. Please DO NOT MODIFY this file. If you //\n")
        f_out.write("// need to change something inside, edit the original source file   //\n")
        f_out.write("// and re-genrate the merged version!                               //\n")
        f_out.write("//////////////////////////////////////////////////////////////////////\n")
        f_out.write("\n\n\n\n")

        for vlog in flist.filter(VerilogFile):
            f_out.write("\n\n//  File: %s\n" % vlog.rel_path())
            f_out.write("//  Source: %s\n" % vlog.module.url)
            if vlog.module.revision:
                f_out.write("//  Revision: %s\n" % vlog.module.revision)
            f_out.write("//  Last modified: %s\n" % time.ctime(os.path.getmtime(vlog.path)))
            vpp = VerilogPreprocessor()
            for include_path in vlog.include_dirs:
                vpp.add_path(include_path)
            vpp.add_path(vlog.dirname)
            f_out.write(vpp.preprocess(vlog.rel_path()))
        f_out.close()

        for ngc in flist.filter(NGCFile):
            import shutil
            logging.info("copying NGC file: %s" % ngc.rel_path())
            shutil.copy(ngc.rel_path(), os.getcwd())

        logging.info("Cores merged.")
Пример #2
0
    def merge_cores(self):
        from srcfile import VerilogFile, VHDLFile, SVFile, NGCFile
        from vlog_parser import VerilogPreprocessor

        solver = DependencySolver()

        pool = self.modules_pool
        if not pool.is_everything_fetched():
            p.echo(
                "A module remains unfetched. Fetching must be done prior to makefile generation"
            )
            p.echo(
                str([
                    str(m) for m in self.modules_pool.modules
                    if not m.isfetched
                ]))
            quit()

        flist = pool.build_global_file_list()
        flist_sorted = solver.solve(flist)

        #        if not os.path.exists(self.options.merge_cores):
        #           os.makedirs(self.options.merge_cores)
        base = self.options.merge_cores

        f_out = open(base + ".vhd", "w")
        f_out.write("\n\n\n\n")
        f_out.write(
            "------------------------------ WARNING -------------------------------\n"
        )
        f_out.write(
            "-- This code has been generated by hdlmake --merge-cores option     --\n"
        )
        f_out.write(
            "-- It is provided for your convenience, to spare you from adding    --\n"
        )
        f_out.write(
            "-- lots of individual source files to ISE/Modelsim/Quartus projects --\n"
        )
        f_out.write(
            "-- mainly for Windows users. Please DO NOT MODIFY this file. If you --\n"
        )
        f_out.write(
            "-- need to change something inside, edit the original source file   --\n"
        )
        f_out.write(
            "-- and re-genrate the merged version!                               --\n"
        )
        f_out.write(
            "----------------------------------------------------------------------\n"
        )
        f_out.write("\n\n\n\n")

        for vhdl in flist_sorted.filter(VHDLFile):
            f_out.write("\n\n--- File: %s ----\n\n" % vhdl.rel_path())
            f_out.write(open(vhdl.rel_path(), "r").read() + "\n\n")
            #print("VHDL: %s" % vhdl.rel_path())
        f_out.close()

        f_out = open(base + ".v", "w")

        f_out.write("\n\n\n\n")
        f_out.write(
            "////////////////////////////// WARNING ///////////////////////////////\n"
        )
        f_out.write(
            "// This code has been generated by hdlmake --merge-cores option     //\n"
        )
        f_out.write(
            "// It is provided for your convenience, to spare you from adding    //\n"
        )
        f_out.write(
            "// lots of individual source files to ISE/Modelsim/Quartus projects //\n"
        )
        f_out.write(
            "// mainly for Windows users. Please DO NOT MODIFY this file. If you //\n"
        )
        f_out.write(
            "// need to change something inside, edit the original source file   //\n"
        )
        f_out.write(
            "// and re-genrate the merged version!                               //\n"
        )
        f_out.write(
            "//////////////////////////////////////////////////////////////////////\n"
        )
        f_out.write("\n\n\n\n")

        for vlog in flist_sorted.filter(VerilogFile):
            f_out.write("\n\n//    File: %s     \n\n" % vlog.rel_path())
            vpp = VerilogPreprocessor()
            vpp.add_path(vlog.dirname)
            f_out.write(vpp.preprocess(vlog.rel_path()))
        f_out.close()

        for ngc in flist_sorted.filter(NGCFile):
            import shutil
            print("NGC:%s " % ngc.rel_path())
            shutil.copy(ngc.rel_path(), self.options.merge_cores + "/")
Пример #3
0
    def merge_cores(self):
        from srcfile import VerilogFile, VHDLFile, SVFile, NGCFile
        from vlog_parser import VerilogPreprocessor

        solver = DependencySolver()

        pool = self.modules_pool
        if not pool.is_everything_fetched():
            p.echo("A module remains unfetched. Fetching must be done prior to makefile generation")
            p.echo(str([str(m) for m in self.modules_pool.modules if not m.isfetched]))
            quit()

        flist = pool.build_global_file_list();
        flist_sorted = solver.solve(flist);

#        if not os.path.exists(self.options.merge_cores):
 #           os.makedirs(self.options.merge_cores)
        base = self.options.merge_cores

        f_out = open(base+".vhd", "w")
        f_out.write("\n\n\n\n");
        f_out.write("------------------------------ WARNING -------------------------------\n");
        f_out.write("-- This code has been generated by hdlmake --merge-cores option     --\n");
        f_out.write("-- It is provided for your convenience, to spare you from adding    --\n");
        f_out.write("-- lots of individual source files to ISE/Modelsim/Quartus projects --\n");
        f_out.write("-- mainly for Windows users. Please DO NOT MODIFY this file. If you --\n");
        f_out.write("-- need to change something inside, edit the original source file   --\n");
        f_out.write("-- and re-genrate the merged version!                               --\n");
        f_out.write("----------------------------------------------------------------------\n");
        f_out.write("\n\n\n\n");



        for vhdl in flist_sorted.filter(VHDLFile):
            f_out.write("\n\n--- File: %s ----\n\n" % vhdl.rel_path())
            f_out.write(open(vhdl.rel_path(),"r").read()+"\n\n")
                #print("VHDL: %s" % vhdl.rel_path())
        f_out.close()

        f_out = open(base+".v", "w")

        f_out.write("\n\n\n\n");
        f_out.write("////////////////////////////// WARNING ///////////////////////////////\n");
        f_out.write("// This code has been generated by hdlmake --merge-cores option     //\n");
        f_out.write("// It is provided for your convenience, to spare you from adding    //\n");
        f_out.write("// lots of individual source files to ISE/Modelsim/Quartus projects //\n");
        f_out.write("// mainly for Windows users. Please DO NOT MODIFY this file. If you //\n");
        f_out.write("// need to change something inside, edit the original source file   //\n");
        f_out.write("// and re-genrate the merged version!                               //\n");
        f_out.write("//////////////////////////////////////////////////////////////////////\n");
        f_out.write("\n\n\n\n");

        for vlog in flist_sorted.filter(VerilogFile):
            f_out.write("\n\n//    File: %s     \n\n" % vlog.rel_path())
            vpp = VerilogPreprocessor()
            vpp.add_path(vlog.dirname)
            f_out.write(vpp.preprocess(vlog.rel_path()))
        f_out.close()

        for ngc in flist_sorted.filter(NGCFile):
            import shutil
            print("NGC:%s " % ngc.rel_path())
            shutil.copy(ngc.rel_path(), self.options.merge_cores+"/")