def test_compile_project_vhdl_93(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("93"))
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
join(self.prefix_path, "vcom"),
"-quiet",
"-modelsimini",
join(self.output_path, "modelsim.ini"),
"-93",
"-work",
"lib",
"file.vhd",
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_verilog_extra_flags(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
source_file = project.add_source_file("file.v",
"lib",
file_type="verilog")
source_file.set_compile_option("modelsim.vlog_flags",
["custom", "flags"])
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
join(self.prefix_path, "vlog"),
"-quiet",
"-modelsimini",
join(self.output_path, "modelsim.ini"),
"custom",
"flags",
"-work",
"lib",
"file.v",
"-L",
"lib",
]
check_output.assert_called_once_with(check_args, env=simif.get_env())
def test_compile_project_verilog_define(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
defines={"defname": "defval"})
simif.compile_project(project)
process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"]
process.assert_called_once_with(process_args, env=simif.get_env())
process_args = [
join(self.prefix_path, "vlog"),
"-quiet",
"-modelsimini",
join(self.output_path, "modelsim.ini"),
"-work",
"lib",
"file.v",
"-L",
"lib",
"+define+defname=defval",
]
check_output.assert_called_once_with(process_args, env=simif.get_env())
def test_compile_project_verilog_include(self, process, check_output):
simif = ModelSimInterface(prefix=self.prefix_path,
output_path=self.output_path,
persistent=False)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v",
"lib",
file_type="verilog",
include_dirs=["include"])
simif.compile_project(project)
process_args = [
str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"
]
process.assert_called_once_with(process_args, env=simif.get_env())
check_args = [
str(Path(self.prefix_path) / "vlog"),
"-quiet",
"-modelsimini",
str(Path(self.output_path) / "modelsim.ini"),
"-work",
"lib",
"file.v",
"-L",
"lib",
"+incdir+include",
]
check_output.assert_called_once_with(check_args, env=simif.get_env())