def test_loopback_register(register=0, verbose=True):
print
print 'Loopback Register {:}'.format(register)
print
address = {
0 : 0x0003,
1 : 0x000B
}[register]
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0000) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0001) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0002) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0004) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0008) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0010) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0020) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0040) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0080) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0100) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0200) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0400) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0800) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x1000) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x2000) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x4000) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x8000) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0000) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x5555) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0xAAAA) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0xFFFF) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
write_address(address, 0x0000) # Write Loopback Register
read_address(address, verbose=verbose) # Loopback Register
def test_gpio(verbose=True):
"""
Wishbone Register Offset = 0xE000
@param verbose
@returns None
@brief Test GPIO
"""
# 0xE000
# 0x0001 direction
# 0x0000 data
# //gpio(15 downto 6) => open,
# //gpio(5) => FPGA_DCM_RST,
# //gpio(4) => BUFFER_OE_N,
# //gpio(3) => LD_TAP4_N,
# //gpio(2) => LD_TAP3_N,
# //gpio(1) => LD_TAP2_N,
# //gpio(0) => LD_TAP1_N
# gpio(15 downto 12) => open,
# gpio(11) => open,
# gpio(10) => FPGA_DCM_RST,
# gpio(9) => LD_DATA_N,
# gpio(8) => BUFFER_OE_N,
# gpio(7) => LD_TAP4_N,
# gpio(6) => LD_TAP3_N,
# gpio(5) => LD_TAP2_N,
# gpio(4) => LD_TAP1_N,
# gpio(3) => CS_TAP4_N,
# gpio(2) => CS_TAP3_N,
# gpio(1) => CS_TAP2_N,
# gpio(0) => CS_TAP1_N
#verbose = True
print
print '@' * 50
print
print 'Test GPIO'
print
read_address(0xE000, verbose=verbose)
write_address(0xE001, 0xF000) # Direction
#logiWrite(0xE000, (0x00, 0x55)) # Data
write_address(0xE000, 0x5000) # Data
read_address(0xE000, verbose=verbose)
#logiWrite(0xE000, (0x00, 0xAA)) # Data
write_address(0xE000, 0xA000) # Data
read_address(0xE000, verbose=verbose)
# Drive BUFFER_OE_N Low
#logiWrite(0xE001, (0x01, 0x00)) # Direction = Output # LSB, MSB
write_address(0xE001, 0x0100) # Direction
#logiWrite(0xE000, (0x00, 0x00)) # Data
write_address(0xE000, 0x0000) # Data
read_address(0xE000, verbose=verbose)
