def bench():
# Parameters
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
qsfp_tx_clk_1 = Signal(bool(0))
qsfp_tx_rst_1 = Signal(bool(0))
qsfp_rx_clk_1 = Signal(bool(0))
qsfp_rx_rst_1 = Signal(bool(0))
qsfp_rxd_1 = Signal(intbv(0)[64:])
qsfp_rxc_1 = Signal(intbv(0)[8:])
qsfp_tx_clk_2 = Signal(bool(0))
qsfp_tx_rst_2 = Signal(bool(0))
qsfp_rx_clk_2 = Signal(bool(0))
qsfp_rx_rst_2 = Signal(bool(0))
qsfp_rxd_2 = Signal(intbv(0)[64:])
qsfp_rxc_2 = Signal(intbv(0)[8:])
qsfp_tx_clk_3 = Signal(bool(0))
qsfp_tx_rst_3 = Signal(bool(0))
qsfp_rx_clk_3 = Signal(bool(0))
qsfp_rx_rst_3 = Signal(bool(0))
qsfp_rxd_3 = Signal(intbv(0)[64:])
qsfp_rxc_3 = Signal(intbv(0)[8:])
qsfp_tx_clk_4 = Signal(bool(0))
qsfp_tx_rst_4 = Signal(bool(0))
qsfp_rx_clk_4 = Signal(bool(0))
qsfp_rx_rst_4 = Signal(bool(0))
qsfp_rxd_4 = Signal(intbv(0)[64:])
qsfp_rxc_4 = Signal(intbv(0)[8:])
# Outputs
qsfp_txd_1 = Signal(intbv(0)[64:])
qsfp_txc_1 = Signal(intbv(0)[8:])
qsfp_txd_2 = Signal(intbv(0)[64:])
qsfp_txc_2 = Signal(intbv(0)[8:])
qsfp_txd_3 = Signal(intbv(0)[64:])
qsfp_txc_3 = Signal(intbv(0)[8:])
qsfp_txd_4 = Signal(intbv(0)[64:])
qsfp_txc_4 = Signal(intbv(0)[8:])
# sources and sinks
qsfp_1_source = xgmii_ep.XGMIISource()
qsfp_1_source_logic = qsfp_1_source.create_logic(qsfp_rx_clk_1,
qsfp_rx_rst_1,
txd=qsfp_rxd_1,
txc=qsfp_rxc_1,
name='qsfp_1_source')
qsfp_1_sink = xgmii_ep.XGMIISink()
qsfp_1_sink_logic = qsfp_1_sink.create_logic(qsfp_tx_clk_1,
qsfp_tx_rst_1,
rxd=qsfp_txd_1,
rxc=qsfp_txc_1,
name='qsfp_1_sink')
qsfp_2_source = xgmii_ep.XGMIISource()
qsfp_2_source_logic = qsfp_2_source.create_logic(qsfp_rx_clk_2,
qsfp_rx_rst_2,
txd=qsfp_rxd_2,
txc=qsfp_rxc_2,
name='qsfp_2_source')
qsfp_2_sink = xgmii_ep.XGMIISink()
qsfp_2_sink_logic = qsfp_2_sink.create_logic(qsfp_tx_clk_2,
qsfp_tx_rst_2,
rxd=qsfp_txd_2,
rxc=qsfp_txc_2,
name='qsfp_2_sink')
qsfp_3_source = xgmii_ep.XGMIISource()
qsfp_3_source_logic = qsfp_3_source.create_logic(qsfp_rx_clk_3,
qsfp_rx_rst_3,
txd=qsfp_rxd_3,
txc=qsfp_rxc_3,
name='qsfp_3_source')
qsfp_3_sink = xgmii_ep.XGMIISink()
qsfp_3_sink_logic = qsfp_3_sink.create_logic(qsfp_tx_clk_3,
qsfp_tx_rst_3,
rxd=qsfp_txd_3,
rxc=qsfp_txc_3,
name='qsfp_3_sink')
qsfp_4_source = xgmii_ep.XGMIISource()
qsfp_4_source_logic = qsfp_4_source.create_logic(qsfp_rx_clk_4,
qsfp_rx_rst_4,
txd=qsfp_rxd_4,
txc=qsfp_rxc_4,
name='qsfp_4_source')
qsfp_4_sink = xgmii_ep.XGMIISink()
qsfp_4_sink_logic = qsfp_4_sink.create_logic(qsfp_tx_clk_4,
qsfp_tx_rst_4,
rxd=qsfp_txd_4,
rxc=qsfp_txc_4,
name='qsfp_4_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
qsfp_tx_clk_1=qsfp_tx_clk_1,
qsfp_tx_rst_1=qsfp_tx_rst_1,
qsfp_txd_1=qsfp_txd_1,
qsfp_txc_1=qsfp_txc_1,
qsfp_rx_clk_1=qsfp_rx_clk_1,
qsfp_rx_rst_1=qsfp_rx_rst_1,
qsfp_rxd_1=qsfp_rxd_1,
qsfp_rxc_1=qsfp_rxc_1,
qsfp_tx_clk_2=qsfp_tx_clk_2,
qsfp_tx_rst_2=qsfp_tx_rst_2,
qsfp_txd_2=qsfp_txd_2,
qsfp_txc_2=qsfp_txc_2,
qsfp_rx_clk_2=qsfp_rx_clk_2,
qsfp_rx_rst_2=qsfp_rx_rst_2,
qsfp_rxd_2=qsfp_rxd_2,
qsfp_rxc_2=qsfp_rxc_2,
qsfp_tx_clk_3=qsfp_tx_clk_3,
qsfp_tx_rst_3=qsfp_tx_rst_3,
qsfp_txd_3=qsfp_txd_3,
qsfp_txc_3=qsfp_txc_3,
qsfp_rx_clk_3=qsfp_rx_clk_3,
qsfp_rx_rst_3=qsfp_rx_rst_3,
qsfp_rxd_3=qsfp_rxd_3,
qsfp_rxc_3=qsfp_rxc_3,
qsfp_tx_clk_4=qsfp_tx_clk_4,
qsfp_tx_rst_4=qsfp_tx_rst_4,
qsfp_txd_4=qsfp_txd_4,
qsfp_txc_4=qsfp_txc_4,
qsfp_rx_clk_4=qsfp_rx_clk_4,
qsfp_rx_rst_4=qsfp_rx_rst_4,
qsfp_rxd_4=qsfp_rxd_4,
qsfp_rxc_4=qsfp_rxc_4)
@always(delay(4))
def clkgen():
clk.next = not clk
qsfp_tx_clk_1.next = not qsfp_tx_clk_1
qsfp_rx_clk_1.next = not qsfp_rx_clk_1
qsfp_tx_clk_2.next = not qsfp_tx_clk_2
qsfp_rx_clk_2.next = not qsfp_rx_clk_2
qsfp_tx_clk_3.next = not qsfp_tx_clk_3
qsfp_rx_clk_3.next = not qsfp_rx_clk_3
qsfp_tx_clk_4.next = not qsfp_tx_clk_4
qsfp_rx_clk_4.next = not qsfp_rx_clk_4
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
qsfp_tx_rst_1.next = 1
qsfp_rx_rst_1.next = 1
qsfp_tx_rst_2.next = 1
qsfp_rx_rst_2.next = 1
qsfp_tx_rst_3.next = 1
qsfp_rx_rst_3.next = 1
qsfp_tx_rst_4.next = 1
qsfp_rx_rst_4.next = 1
yield clk.posedge
rst.next = 0
qsfp_tx_rst_1.next = 0
qsfp_rx_rst_1.next = 0
qsfp_tx_rst_2.next = 0
qsfp_rx_rst_2.next = 0
qsfp_tx_rst_3.next = 0
qsfp_rx_rst_3.next = 0
qsfp_tx_rst_4.next = 0
qsfp_rx_rst_4.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test UDP RX packet")
current_test.next = 1
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 5678
test_frame.udp_dest_port = 1234
test_frame.payload = bytearray(range(32))
test_frame.build()
qsfp_1_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame.build_eth().build_axis_fcs().data)
# wait for ARP request packet
while qsfp_1_sink.empty():
yield clk.posedge
rx_frame = qsfp_1_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 1
assert check_frame.arp_sha == 0x020000000000
assert check_frame.arp_spa == 0xc0a80180
assert check_frame.arp_tha == 0x000000000000
assert check_frame.arp_tpa == 0xc0a80181
# generate response
arp_frame = arp_ep.ARPFrame()
arp_frame.eth_dest_mac = 0x020000000000
arp_frame.eth_src_mac = 0xDAD1D2D3D4D5
arp_frame.eth_type = 0x0806
arp_frame.arp_htype = 0x0001
arp_frame.arp_ptype = 0x0800
arp_frame.arp_hlen = 6
arp_frame.arp_plen = 4
arp_frame.arp_oper = 2
arp_frame.arp_sha = 0xDAD1D2D3D4D5
arp_frame.arp_spa = 0xc0a80181
arp_frame.arp_tha = 0x020000000000
arp_frame.arp_tpa = 0xc0a80180
qsfp_1_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
arp_frame.build_eth().build_axis_fcs().data)
while qsfp_1_sink.empty():
yield clk.posedge
rx_frame = qsfp_1_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 1234
assert check_frame.udp_dest_port == 5678
assert check_frame.payload.data == bytearray(range(32))
assert qsfp_1_source.empty()
assert qsfp_1_sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
sw = Signal(intbv(0)[2:])
jp = Signal(intbv(0)[4:])
uart_suspend = Signal(bool(0))
uart_dtr = Signal(bool(0))
uart_txd = Signal(bool(0))
uart_rts = Signal(bool(0))
amh_right_mdio_i = Signal(bool(0))
amh_left_mdio_i = Signal(bool(0))
eth_r0_rxd = Signal(intbv(0)[64:])
eth_r0_rxc = Signal(intbv(0)[8:])
eth_r1_rxd = Signal(intbv(0)[64:])
eth_r1_rxc = Signal(intbv(0)[8:])
eth_r2_rxd = Signal(intbv(0)[64:])
eth_r2_rxc = Signal(intbv(0)[8:])
eth_r3_rxd = Signal(intbv(0)[64:])
eth_r3_rxc = Signal(intbv(0)[8:])
eth_r4_rxd = Signal(intbv(0)[64:])
eth_r4_rxc = Signal(intbv(0)[8:])
eth_r5_rxd = Signal(intbv(0)[64:])
eth_r5_rxc = Signal(intbv(0)[8:])
eth_r6_rxd = Signal(intbv(0)[64:])
eth_r6_rxc = Signal(intbv(0)[8:])
eth_r7_rxd = Signal(intbv(0)[64:])
eth_r7_rxc = Signal(intbv(0)[8:])
eth_r8_rxd = Signal(intbv(0)[64:])
eth_r8_rxc = Signal(intbv(0)[8:])
eth_r9_rxd = Signal(intbv(0)[64:])
eth_r9_rxc = Signal(intbv(0)[8:])
eth_r10_rxd = Signal(intbv(0)[64:])
eth_r10_rxc = Signal(intbv(0)[8:])
eth_r11_rxd = Signal(intbv(0)[64:])
eth_r11_rxc = Signal(intbv(0)[8:])
eth_l0_rxd = Signal(intbv(0)[64:])
eth_l0_rxc = Signal(intbv(0)[8:])
eth_l1_rxd = Signal(intbv(0)[64:])
eth_l1_rxc = Signal(intbv(0)[8:])
eth_l2_rxd = Signal(intbv(0)[64:])
eth_l2_rxc = Signal(intbv(0)[8:])
eth_l3_rxd = Signal(intbv(0)[64:])
eth_l3_rxc = Signal(intbv(0)[8:])
eth_l4_rxd = Signal(intbv(0)[64:])
eth_l4_rxc = Signal(intbv(0)[8:])
eth_l5_rxd = Signal(intbv(0)[64:])
eth_l5_rxc = Signal(intbv(0)[8:])
eth_l6_rxd = Signal(intbv(0)[64:])
eth_l6_rxc = Signal(intbv(0)[8:])
eth_l7_rxd = Signal(intbv(0)[64:])
eth_l7_rxc = Signal(intbv(0)[8:])
eth_l8_rxd = Signal(intbv(0)[64:])
eth_l8_rxc = Signal(intbv(0)[8:])
eth_l9_rxd = Signal(intbv(0)[64:])
eth_l9_rxc = Signal(intbv(0)[8:])
eth_l10_rxd = Signal(intbv(0)[64:])
eth_l10_rxc = Signal(intbv(0)[8:])
eth_l11_rxd = Signal(intbv(0)[64:])
eth_l11_rxc = Signal(intbv(0)[8:])
# Outputs
led = Signal(intbv(0)[4:])
uart_rst = Signal(bool(0))
uart_ri = Signal(bool(0))
uart_dcd = Signal(bool(0))
uart_dsr = Signal(bool(0))
uart_rxd = Signal(bool(1))
uart_cts = Signal(bool(0))
amh_right_mdc = Signal(bool(1))
amh_right_mdio_o = Signal(bool(1))
amh_right_mdio_t = Signal(bool(1))
amh_left_mdc = Signal(bool(1))
amh_left_mdio_o = Signal(bool(1))
amh_left_mdio_t = Signal(bool(1))
eth_r0_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r0_txc = Signal(intbv(0xff)[8:])
eth_r1_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r1_txc = Signal(intbv(0xff)[8:])
eth_r2_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r2_txc = Signal(intbv(0xff)[8:])
eth_r3_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r3_txc = Signal(intbv(0xff)[8:])
eth_r4_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r4_txc = Signal(intbv(0xff)[8:])
eth_r5_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r5_txc = Signal(intbv(0xff)[8:])
eth_r6_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r6_txc = Signal(intbv(0xff)[8:])
eth_r7_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r7_txc = Signal(intbv(0xff)[8:])
eth_r8_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r8_txc = Signal(intbv(0xff)[8:])
eth_r9_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r9_txc = Signal(intbv(0xff)[8:])
eth_r10_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r10_txc = Signal(intbv(0xff)[8:])
eth_r11_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r11_txc = Signal(intbv(0xff)[8:])
eth_l0_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l0_txc = Signal(intbv(0xff)[8:])
eth_l1_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l1_txc = Signal(intbv(0xff)[8:])
eth_l2_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l2_txc = Signal(intbv(0xff)[8:])
eth_l3_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l3_txc = Signal(intbv(0xff)[8:])
eth_l4_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l4_txc = Signal(intbv(0xff)[8:])
eth_l5_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l5_txc = Signal(intbv(0xff)[8:])
eth_l6_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l6_txc = Signal(intbv(0xff)[8:])
eth_l7_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l7_txc = Signal(intbv(0xff)[8:])
eth_l8_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l8_txc = Signal(intbv(0xff)[8:])
eth_l9_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l9_txc = Signal(intbv(0xff)[8:])
eth_l10_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l10_txc = Signal(intbv(0xff)[8:])
eth_l11_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l11_txc = Signal(intbv(0xff)[8:])
# sources and sinks
eth_r0_source = xgmii_ep.XGMIISource()
eth_r0_source_logic = eth_r0_source.create_logic(clk,
rst,
txd=eth_r0_rxd,
txc=eth_r0_rxc,
name='eth_r0_source')
eth_r0_sink = xgmii_ep.XGMIISink()
eth_r0_sink_logic = eth_r0_sink.create_logic(clk,
rst,
rxd=eth_r0_txd,
rxc=eth_r0_txc,
name='eth_r0_sink')
eth_r1_source = xgmii_ep.XGMIISource()
eth_r1_source_logic = eth_r1_source.create_logic(clk,
rst,
txd=eth_r1_rxd,
txc=eth_r1_rxc,
name='eth_r1_source')
eth_r1_sink = xgmii_ep.XGMIISink()
eth_r1_sink_logic = eth_r1_sink.create_logic(clk,
rst,
rxd=eth_r1_txd,
rxc=eth_r1_txc,
name='eth_r1_sink')
eth_r2_source = xgmii_ep.XGMIISource()
eth_r2_source_logic = eth_r2_source.create_logic(clk,
rst,
txd=eth_r2_rxd,
txc=eth_r2_rxc,
name='eth_r2_source')
eth_r2_sink = xgmii_ep.XGMIISink()
eth_r2_sink_logic = eth_r2_sink.create_logic(clk,
rst,
rxd=eth_r2_txd,
rxc=eth_r2_txc,
name='eth_r2_sink')
eth_r3_source = xgmii_ep.XGMIISource()
eth_r3_source_logic = eth_r3_source.create_logic(clk,
rst,
txd=eth_r3_rxd,
txc=eth_r3_rxc,
name='eth_r3_source')
eth_r3_sink = xgmii_ep.XGMIISink()
eth_r3_sink_logic = eth_r3_sink.create_logic(clk,
rst,
rxd=eth_r3_txd,
rxc=eth_r3_txc,
name='eth_r3_sink')
eth_r4_source = xgmii_ep.XGMIISource()
eth_r4_source_logic = eth_r4_source.create_logic(clk,
rst,
txd=eth_r4_rxd,
txc=eth_r4_rxc,
name='eth_r4_source')
eth_r4_sink = xgmii_ep.XGMIISink()
eth_r4_sink_logic = eth_r4_sink.create_logic(clk,
rst,
rxd=eth_r4_txd,
rxc=eth_r4_txc,
name='eth_r4_sink')
eth_r5_source = xgmii_ep.XGMIISource()
eth_r5_source_logic = eth_r5_source.create_logic(clk,
rst,
txd=eth_r5_rxd,
txc=eth_r5_rxc,
name='eth_r5_source')
eth_r5_sink = xgmii_ep.XGMIISink()
eth_r5_sink_logic = eth_r5_sink.create_logic(clk,
rst,
rxd=eth_r5_txd,
rxc=eth_r5_txc,
name='eth_r5_sink')
eth_r6_source = xgmii_ep.XGMIISource()
eth_r6_source_logic = eth_r6_source.create_logic(clk,
rst,
txd=eth_r6_rxd,
txc=eth_r6_rxc,
name='eth_r6_source')
eth_r6_sink = xgmii_ep.XGMIISink()
eth_r6_sink_logic = eth_r6_sink.create_logic(clk,
rst,
rxd=eth_r6_txd,
rxc=eth_r6_txc,
name='eth_r6_sink')
eth_r7_source = xgmii_ep.XGMIISource()
eth_r7_source_logic = eth_r7_source.create_logic(clk,
rst,
txd=eth_r7_rxd,
txc=eth_r7_rxc,
name='eth_r7_source')
eth_r7_sink = xgmii_ep.XGMIISink()
eth_r7_sink_logic = eth_r7_sink.create_logic(clk,
rst,
rxd=eth_r7_txd,
rxc=eth_r7_txc,
name='eth_r7_sink')
eth_r8_source = xgmii_ep.XGMIISource()
eth_r8_source_logic = eth_r8_source.create_logic(clk,
rst,
txd=eth_r8_rxd,
txc=eth_r8_rxc,
name='eth_r8_source')
eth_r8_sink = xgmii_ep.XGMIISink()
eth_r8_sink_logic = eth_r8_sink.create_logic(clk,
rst,
rxd=eth_r8_txd,
rxc=eth_r8_txc,
name='eth_r8_sink')
eth_r9_source = xgmii_ep.XGMIISource()
eth_r9_source_logic = eth_r9_source.create_logic(clk,
rst,
txd=eth_r9_rxd,
txc=eth_r9_rxc,
name='eth_r9_source')
eth_r9_sink = xgmii_ep.XGMIISink()
eth_r9_sink_logic = eth_r9_sink.create_logic(clk,
rst,
rxd=eth_r9_txd,
rxc=eth_r9_txc,
name='eth_r9_sink')
eth_r10_source = xgmii_ep.XGMIISource()
eth_r10_source_logic = eth_r10_source.create_logic(clk,
rst,
txd=eth_r10_rxd,
txc=eth_r10_rxc,
name='eth_r10_source')
eth_r10_sink = xgmii_ep.XGMIISink()
eth_r10_sink_logic = eth_r10_sink.create_logic(clk,
rst,
rxd=eth_r10_txd,
rxc=eth_r10_txc,
name='eth_r10_sink')
eth_r11_source = xgmii_ep.XGMIISource()
eth_r11_source_logic = eth_r11_source.create_logic(clk,
rst,
txd=eth_r11_rxd,
txc=eth_r11_rxc,
name='eth_r11_source')
eth_r11_sink = xgmii_ep.XGMIISink()
eth_r11_sink_logic = eth_r11_sink.create_logic(clk,
rst,
rxd=eth_r11_txd,
rxc=eth_r11_txc,
name='eth_r11_sink')
eth_l0_source = xgmii_ep.XGMIISource()
eth_l0_source_logic = eth_l0_source.create_logic(clk,
rst,
txd=eth_l0_rxd,
txc=eth_l0_rxc,
name='eth_l0_source')
eth_l0_sink = xgmii_ep.XGMIISink()
eth_l0_sink_logic = eth_l0_sink.create_logic(clk,
rst,
rxd=eth_l0_txd,
rxc=eth_l0_txc,
name='eth_l0_sink')
eth_l1_source = xgmii_ep.XGMIISource()
eth_l1_source_logic = eth_l1_source.create_logic(clk,
rst,
txd=eth_l1_rxd,
txc=eth_l1_rxc,
name='eth_l1_source')
eth_l1_sink = xgmii_ep.XGMIISink()
eth_l1_sink_logic = eth_l1_sink.create_logic(clk,
rst,
rxd=eth_l1_txd,
rxc=eth_l1_txc,
name='eth_l1_sink')
eth_l2_source = xgmii_ep.XGMIISource()
eth_l2_source_logic = eth_l2_source.create_logic(clk,
rst,
txd=eth_l2_rxd,
txc=eth_l2_rxc,
name='eth_l2_source')
eth_l2_sink = xgmii_ep.XGMIISink()
eth_l2_sink_logic = eth_l2_sink.create_logic(clk,
rst,
rxd=eth_l2_txd,
rxc=eth_l2_txc,
name='eth_l2_sink')
eth_l3_source = xgmii_ep.XGMIISource()
eth_l3_source_logic = eth_l3_source.create_logic(clk,
rst,
txd=eth_l3_rxd,
txc=eth_l3_rxc,
name='eth_l3_source')
eth_l3_sink = xgmii_ep.XGMIISink()
eth_l3_sink_logic = eth_l3_sink.create_logic(clk,
rst,
rxd=eth_l3_txd,
rxc=eth_l3_txc,
name='eth_l3_sink')
eth_l4_source = xgmii_ep.XGMIISource()
eth_l4_source_logic = eth_l4_source.create_logic(clk,
rst,
txd=eth_l4_rxd,
txc=eth_l4_rxc,
name='eth_l4_source')
eth_l4_sink = xgmii_ep.XGMIISink()
eth_l4_sink_logic = eth_l4_sink.create_logic(clk,
rst,
rxd=eth_l4_txd,
rxc=eth_l4_txc,
name='eth_l4_sink')
eth_l5_source = xgmii_ep.XGMIISource()
eth_l5_source_logic = eth_l5_source.create_logic(clk,
rst,
txd=eth_l5_rxd,
txc=eth_l5_rxc,
name='eth_l5_source')
eth_l5_sink = xgmii_ep.XGMIISink()
eth_l5_sink_logic = eth_l5_sink.create_logic(clk,
rst,
rxd=eth_l5_txd,
rxc=eth_l5_txc,
name='eth_l5_sink')
eth_l6_source = xgmii_ep.XGMIISource()
eth_l6_source_logic = eth_l6_source.create_logic(clk,
rst,
txd=eth_l6_rxd,
txc=eth_l6_rxc,
name='eth_l6_source')
eth_l6_sink = xgmii_ep.XGMIISink()
eth_l6_sink_logic = eth_l6_sink.create_logic(clk,
rst,
rxd=eth_l6_txd,
rxc=eth_l6_txc,
name='eth_l6_sink')
eth_l7_source = xgmii_ep.XGMIISource()
eth_l7_source_logic = eth_l7_source.create_logic(clk,
rst,
txd=eth_l7_rxd,
txc=eth_l7_rxc,
name='eth_l7_source')
eth_l7_sink = xgmii_ep.XGMIISink()
eth_l7_sink_logic = eth_l7_sink.create_logic(clk,
rst,
rxd=eth_l7_txd,
rxc=eth_l7_txc,
name='eth_l7_sink')
eth_l8_source = xgmii_ep.XGMIISource()
eth_l8_source_logic = eth_l8_source.create_logic(clk,
rst,
txd=eth_l8_rxd,
txc=eth_l8_rxc,
name='eth_l8_source')
eth_l8_sink = xgmii_ep.XGMIISink()
eth_l8_sink_logic = eth_l8_sink.create_logic(clk,
rst,
rxd=eth_l8_txd,
rxc=eth_l8_txc,
name='eth_l8_sink')
eth_l9_source = xgmii_ep.XGMIISource()
eth_l9_source_logic = eth_l9_source.create_logic(clk,
rst,
txd=eth_l9_rxd,
txc=eth_l9_rxc,
name='eth_l9_source')
eth_l9_sink = xgmii_ep.XGMIISink()
eth_l9_sink_logic = eth_l9_sink.create_logic(clk,
rst,
rxd=eth_l9_txd,
rxc=eth_l9_txc,
name='eth_l9_sink')
eth_l10_source = xgmii_ep.XGMIISource()
eth_l10_source_logic = eth_l10_source.create_logic(clk,
rst,
txd=eth_l10_rxd,
txc=eth_l10_rxc,
name='eth_l10_source')
eth_l10_sink = xgmii_ep.XGMIISink()
eth_l10_sink_logic = eth_l10_sink.create_logic(clk,
rst,
rxd=eth_l10_txd,
rxc=eth_l10_txc,
name='eth_l10_sink')
eth_l11_source = xgmii_ep.XGMIISource()
eth_l11_source_logic = eth_l11_source.create_logic(clk,
rst,
txd=eth_l11_rxd,
txc=eth_l11_rxc,
name='eth_l11_source')
eth_l11_sink = xgmii_ep.XGMIISink()
eth_l11_sink_logic = eth_l11_sink.create_logic(clk,
rst,
rxd=eth_l11_txd,
rxc=eth_l11_txc,
name='eth_l11_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
sw=sw,
jp=jp,
led=led,
uart_rst=uart_rst,
uart_suspend=uart_suspend,
uart_ri=uart_ri,
uart_dcd=uart_dcd,
uart_dtr=uart_dtr,
uart_dsr=uart_dsr,
uart_txd=uart_txd,
uart_rxd=uart_rxd,
uart_rts=uart_rts,
uart_cts=uart_cts,
amh_right_mdc=amh_right_mdc,
amh_right_mdio_i=amh_right_mdio_i,
amh_right_mdio_o=amh_right_mdio_o,
amh_right_mdio_t=amh_right_mdio_t,
amh_left_mdc=amh_left_mdc,
amh_left_mdio_i=amh_left_mdio_i,
amh_left_mdio_o=amh_left_mdio_o,
amh_left_mdio_t=amh_left_mdio_t,
eth_r0_txd=eth_r0_txd,
eth_r0_txc=eth_r0_txc,
eth_r0_rxd=eth_r0_rxd,
eth_r0_rxc=eth_r0_rxc,
eth_r1_txd=eth_r1_txd,
eth_r1_txc=eth_r1_txc,
eth_r1_rxd=eth_r1_rxd,
eth_r1_rxc=eth_r1_rxc,
eth_r2_txd=eth_r2_txd,
eth_r2_txc=eth_r2_txc,
eth_r2_rxd=eth_r2_rxd,
eth_r2_rxc=eth_r2_rxc,
eth_r3_txd=eth_r3_txd,
eth_r3_txc=eth_r3_txc,
eth_r3_rxd=eth_r3_rxd,
eth_r3_rxc=eth_r3_rxc,
eth_r4_txd=eth_r4_txd,
eth_r4_txc=eth_r4_txc,
eth_r4_rxd=eth_r4_rxd,
eth_r4_rxc=eth_r4_rxc,
eth_r5_txd=eth_r5_txd,
eth_r5_txc=eth_r5_txc,
eth_r5_rxd=eth_r5_rxd,
eth_r5_rxc=eth_r5_rxc,
eth_r6_txd=eth_r6_txd,
eth_r6_txc=eth_r6_txc,
eth_r6_rxd=eth_r6_rxd,
eth_r6_rxc=eth_r6_rxc,
eth_r7_txd=eth_r7_txd,
eth_r7_txc=eth_r7_txc,
eth_r7_rxd=eth_r7_rxd,
eth_r7_rxc=eth_r7_rxc,
eth_r8_txd=eth_r8_txd,
eth_r8_txc=eth_r8_txc,
eth_r8_rxd=eth_r8_rxd,
eth_r8_rxc=eth_r8_rxc,
eth_r9_txd=eth_r9_txd,
eth_r9_txc=eth_r9_txc,
eth_r9_rxd=eth_r9_rxd,
eth_r9_rxc=eth_r9_rxc,
eth_r10_txd=eth_r10_txd,
eth_r10_txc=eth_r10_txc,
eth_r10_rxd=eth_r10_rxd,
eth_r10_rxc=eth_r10_rxc,
eth_r11_txd=eth_r11_txd,
eth_r11_txc=eth_r11_txc,
eth_r11_rxd=eth_r11_rxd,
eth_r11_rxc=eth_r11_rxc,
eth_l0_txd=eth_l0_txd,
eth_l0_txc=eth_l0_txc,
eth_l0_rxd=eth_l0_rxd,
eth_l0_rxc=eth_l0_rxc,
eth_l1_txd=eth_l1_txd,
eth_l1_txc=eth_l1_txc,
eth_l1_rxd=eth_l1_rxd,
eth_l1_rxc=eth_l1_rxc,
eth_l2_txd=eth_l2_txd,
eth_l2_txc=eth_l2_txc,
eth_l2_rxd=eth_l2_rxd,
eth_l2_rxc=eth_l2_rxc,
eth_l3_txd=eth_l3_txd,
eth_l3_txc=eth_l3_txc,
eth_l3_rxd=eth_l3_rxd,
eth_l3_rxc=eth_l3_rxc,
eth_l4_txd=eth_l4_txd,
eth_l4_txc=eth_l4_txc,
eth_l4_rxd=eth_l4_rxd,
eth_l4_rxc=eth_l4_rxc,
eth_l5_txd=eth_l5_txd,
eth_l5_txc=eth_l5_txc,
eth_l5_rxd=eth_l5_rxd,
eth_l5_rxc=eth_l5_rxc,
eth_l6_txd=eth_l6_txd,
eth_l6_txc=eth_l6_txc,
eth_l6_rxd=eth_l6_rxd,
eth_l6_rxc=eth_l6_rxc,
eth_l7_txd=eth_l7_txd,
eth_l7_txc=eth_l7_txc,
eth_l7_rxd=eth_l7_rxd,
eth_l7_rxc=eth_l7_rxc,
eth_l8_txd=eth_l8_txd,
eth_l8_txc=eth_l8_txc,
eth_l8_rxd=eth_l8_rxd,
eth_l8_rxc=eth_l8_rxc,
eth_l9_txd=eth_l9_txd,
eth_l9_txc=eth_l9_txc,
eth_l9_rxd=eth_l9_rxd,
eth_l9_rxc=eth_l9_rxc,
eth_l10_txd=eth_l10_txd,
eth_l10_txc=eth_l10_txc,
eth_l10_rxd=eth_l10_rxd,
eth_l10_rxc=eth_l10_rxc,
eth_l11_txd=eth_l11_txd,
eth_l11_txc=eth_l11_txc,
eth_l11_rxd=eth_l11_rxd,
eth_l11_rxc=eth_l11_rxc)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(46))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
bytearray(axis_frame))
eth_l0_source.send(xgmii_frame)
while eth_l0_sink.empty():
yield clk.posedge
check_frame = eth_l0_sink.recv()
assert check_frame == xgmii_frame
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8099
test_frame.payload = bytearray(range(15, -1, -1)) + bytearray(
[0] * (46 - 16))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
bytearray(axis_frame))
eth_l11_source.send(xgmii_frame)
yield delay(400)
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(46))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
bytearray(axis_frame))
eth_l0_source.send(xgmii_frame)
while eth_r7_sink.empty():
yield clk.posedge
check_frame = eth_r7_sink.recv()
assert check_frame == xgmii_frame
yield delay(100)
raise StopSimulation
return (dut, clkgen, check, eth_r0_source_logic, eth_r0_sink_logic,
eth_r1_source_logic, eth_r1_sink_logic, eth_r2_source_logic,
eth_r2_sink_logic, eth_r3_source_logic, eth_r3_sink_logic,
eth_r4_source_logic, eth_r4_sink_logic, eth_r5_source_logic,
eth_r5_sink_logic, eth_r6_source_logic, eth_r6_sink_logic,
eth_r7_source_logic, eth_r7_sink_logic, eth_r8_source_logic,
eth_r8_sink_logic, eth_r9_source_logic, eth_r9_sink_logic,
eth_r10_source_logic, eth_r10_sink_logic, eth_r11_source_logic,
eth_r11_sink_logic, eth_l0_source_logic, eth_l0_sink_logic,
eth_l1_source_logic, eth_l1_sink_logic, eth_l2_source_logic,
eth_l2_sink_logic, eth_l3_source_logic, eth_l3_sink_logic,
eth_l4_source_logic, eth_l4_sink_logic, eth_l5_source_logic,
eth_l5_sink_logic, eth_l6_source_logic, eth_l6_sink_logic,
eth_l7_source_logic, eth_l7_sink_logic, eth_l8_source_logic,
eth_l8_sink_logic, eth_l9_source_logic, eth_l9_sink_logic,
eth_l10_source_logic, eth_l10_sink_logic, eth_l11_source_logic,
eth_l11_sink_logic)
def bench():
# Parameters
AXIS_PCIE_DATA_WIDTH = 256
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32)
AXIS_PCIE_RC_USER_WIDTH = 75
AXIS_PCIE_RQ_USER_WIDTH = 60
AXIS_PCIE_CQ_USER_WIDTH = 85
AXIS_PCIE_CC_USER_WIDTH = 33
RQ_SEQ_NUM_WIDTH = 4
BAR0_APERTURE = 24
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
btnu = Signal(bool(0))
btnl = Signal(bool(0))
btnd = Signal(bool(0))
btnr = Signal(bool(0))
btnc = Signal(bool(0))
sw = Signal(intbv(0)[4:])
i2c_scl_i = Signal(bool(1))
i2c_sda_i = Signal(bool(1))
m_axis_rq_tready = Signal(bool(0))
s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_rc_tlast = Signal(bool(0))
s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:])
s_axis_rc_tvalid = Signal(bool(0))
s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_cq_tlast = Signal(bool(0))
s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:])
s_axis_cq_tvalid = Signal(bool(0))
m_axis_cc_tready = Signal(bool(0))
s_axis_rq_seq_num = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
s_axis_rq_seq_num_valid = Signal(bool(0))
pcie_tfc_nph_av = Signal(intbv(0)[2:])
pcie_tfc_npd_av = Signal(intbv(0)[2:])
cfg_max_payload = Signal(intbv(0)[3:])
cfg_max_read_req = Signal(intbv(0)[3:])
cfg_mgmt_read_data = Signal(intbv(0)[32:])
cfg_mgmt_read_write_done = Signal(bool(0))
cfg_fc_ph = Signal(intbv(0)[8:])
cfg_fc_pd = Signal(intbv(0)[12:])
cfg_fc_nph = Signal(intbv(0)[8:])
cfg_fc_npd = Signal(intbv(0)[12:])
cfg_fc_cplh = Signal(intbv(0)[8:])
cfg_fc_cpld = Signal(intbv(0)[12:])
cfg_interrupt_msi_enable = Signal(intbv(0)[4:])
cfg_interrupt_msi_vf_enable = Signal(intbv(0)[8:])
cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:])
cfg_interrupt_msi_mask_update = Signal(bool(0))
cfg_interrupt_msi_data = Signal(intbv(0)[32:])
cfg_interrupt_msi_sent = Signal(bool(0))
cfg_interrupt_msi_fail = Signal(bool(0))
qsfp_tx_clk_1 = Signal(bool(0))
qsfp_tx_rst_1 = Signal(bool(0))
qsfp_rx_clk_1 = Signal(bool(0))
qsfp_rx_rst_1 = Signal(bool(0))
qsfp_rxd_1 = Signal(intbv(0)[64:])
qsfp_rxc_1 = Signal(intbv(0)[8:])
qsfp_tx_clk_2 = Signal(bool(0))
qsfp_tx_rst_2 = Signal(bool(0))
qsfp_rx_clk_2 = Signal(bool(0))
qsfp_rx_rst_2 = Signal(bool(0))
qsfp_rxd_2 = Signal(intbv(0)[64:])
qsfp_rxc_2 = Signal(intbv(0)[8:])
qsfp_tx_clk_3 = Signal(bool(0))
qsfp_tx_rst_3 = Signal(bool(0))
qsfp_rx_clk_3 = Signal(bool(0))
qsfp_rx_rst_3 = Signal(bool(0))
qsfp_rxd_3 = Signal(intbv(0)[64:])
qsfp_rxc_3 = Signal(intbv(0)[8:])
qsfp_tx_clk_4 = Signal(bool(0))
qsfp_tx_rst_4 = Signal(bool(0))
qsfp_rx_clk_4 = Signal(bool(0))
qsfp_rx_rst_4 = Signal(bool(0))
qsfp_rxd_4 = Signal(intbv(0)[64:])
qsfp_rxc_4 = Signal(intbv(0)[8:])
qsfp_modprsl = Signal(bool(1))
qsfp_intl = Signal(bool(1))
flash_dq_i = Signal(intbv(0)[16:])
# Outputs
led = Signal(intbv(0)[8:])
i2c_scl_o = Signal(bool(1))
i2c_scl_t = Signal(bool(1))
i2c_sda_o = Signal(bool(1))
i2c_sda_t = Signal(bool(1))
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_rq_tlast = Signal(bool(0))
m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
m_axis_rq_tvalid = Signal(bool(0))
s_axis_rc_tready = Signal(bool(0))
s_axis_cq_tready = Signal(bool(0))
m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_cc_tlast = Signal(bool(0))
m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:])
m_axis_cc_tvalid = Signal(bool(0))
status_error_cor = Signal(bool(0))
status_error_uncor = Signal(bool(0))
cfg_mgmt_addr = Signal(intbv(0)[19:])
cfg_mgmt_write = Signal(bool(0))
cfg_mgmt_write_data = Signal(intbv(0)[32:])
cfg_mgmt_byte_enable = Signal(intbv(0)[4:])
cfg_mgmt_read = Signal(bool(0))
cfg_fc_sel = Signal(intbv(4)[3:])
cfg_interrupt_msi_int = Signal(intbv(0)[32:])
cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:])
cfg_interrupt_msi_select = Signal(intbv(0)[4:])
cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[4:])
cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0))
cfg_interrupt_msi_attr = Signal(intbv(0)[3:])
cfg_interrupt_msi_tph_present = Signal(bool(0))
cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:])
cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[9:])
cfg_interrupt_msi_function_number = Signal(intbv(0)[4:])
qsfp_txd_1 = Signal(intbv(0)[64:])
qsfp_txc_1 = Signal(intbv(0)[8:])
qsfp_txd_2 = Signal(intbv(0)[64:])
qsfp_txc_2 = Signal(intbv(0)[8:])
qsfp_txd_3 = Signal(intbv(0)[64:])
qsfp_txc_3 = Signal(intbv(0)[8:])
qsfp_txd_4 = Signal(intbv(0)[64:])
qsfp_txc_4 = Signal(intbv(0)[8:])
qsfp_modsell = Signal(bool(0))
qsfp_resetl = Signal(bool(1))
qsfp_lpmode = Signal(bool(0))
flash_dq_o = Signal(intbv(0)[16:])
flash_dq_oe = Signal(bool(0))
flash_addr = Signal(intbv(0)[23:])
flash_region = Signal(bool(0))
flash_region_oe = Signal(bool(0))
flash_ce_n = Signal(bool(1))
flash_oe_n = Signal(bool(1))
flash_we_n = Signal(bool(1))
flash_adv_n = Signal(bool(1))
# sources and sinks
qsfp_1_source = xgmii_ep.XGMIISource()
qsfp_1_source_logic = qsfp_1_source.create_logic(qsfp_rx_clk_1,
qsfp_rx_rst_1,
txd=qsfp_rxd_1,
txc=qsfp_rxc_1,
name='qsfp_1_source')
qsfp_1_sink = xgmii_ep.XGMIISink()
qsfp_1_sink_logic = qsfp_1_sink.create_logic(qsfp_tx_clk_1,
qsfp_tx_rst_1,
rxd=qsfp_txd_1,
rxc=qsfp_txc_1,
name='qsfp_1_sink')
qsfp_2_source = xgmii_ep.XGMIISource()
qsfp_2_source_logic = qsfp_2_source.create_logic(qsfp_rx_clk_2,
qsfp_rx_rst_2,
txd=qsfp_rxd_2,
txc=qsfp_rxc_2,
name='qsfp_2_source')
qsfp_2_sink = xgmii_ep.XGMIISink()
qsfp_2_sink_logic = qsfp_2_sink.create_logic(qsfp_tx_clk_2,
qsfp_tx_rst_2,
rxd=qsfp_txd_2,
rxc=qsfp_txc_2,
name='qsfp_2_sink')
qsfp_3_source = xgmii_ep.XGMIISource()
qsfp_3_source_logic = qsfp_3_source.create_logic(qsfp_rx_clk_3,
qsfp_rx_rst_3,
txd=qsfp_rxd_3,
txc=qsfp_rxc_3,
name='qsfp_3_source')
qsfp_3_sink = xgmii_ep.XGMIISink()
qsfp_3_sink_logic = qsfp_3_sink.create_logic(qsfp_tx_clk_3,
qsfp_tx_rst_3,
rxd=qsfp_txd_3,
rxc=qsfp_txc_3,
name='qsfp_3_sink')
qsfp_4_source = xgmii_ep.XGMIISource()
qsfp_4_source_logic = qsfp_4_source.create_logic(qsfp_rx_clk_4,
qsfp_rx_rst_4,
txd=qsfp_rxd_4,
txc=qsfp_rxc_4,
name='qsfp_4_source')
qsfp_4_sink = xgmii_ep.XGMIISink()
qsfp_4_sink_logic = qsfp_4_sink.create_logic(qsfp_tx_clk_4,
qsfp_tx_rst_4,
rxd=qsfp_txd_4,
rxc=qsfp_txc_4,
name='qsfp_4_sink')
# Clock and Reset Interface
user_clk = Signal(bool(0))
user_reset = Signal(bool(0))
sys_clk = Signal(bool(0))
sys_reset = Signal(bool(0))
# PCIe devices
rc = pcie.RootComplex()
rc.max_payload_size = 0x1 # 256 bytes
rc.max_read_request_size = 0x5 # 4096 bytes
driver = mqnic.Driver(rc)
dev = pcie_us.UltrascalePCIe()
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.functions[0].msi_multiple_message_capable = 5
dev.functions[0].configure_bar(0,
2**BAR0_APERTURE,
ext=True,
prefetch=True)
rc.make_port().connect(dev)
pcie_logic = dev.create_logic(
# Completer reQuest Interface
m_axis_cq_tdata=s_axis_cq_tdata,
m_axis_cq_tuser=s_axis_cq_tuser,
m_axis_cq_tlast=s_axis_cq_tlast,
m_axis_cq_tkeep=s_axis_cq_tkeep,
m_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cq_tready=s_axis_cq_tready,
#pcie_cq_np_req=pcie_cq_np_req,
pcie_cq_np_req=Signal(bool(1)),
#pcie_cq_np_req_count=pcie_cq_np_req_count,
# Completer Completion Interface
s_axis_cc_tdata=m_axis_cc_tdata,
s_axis_cc_tuser=m_axis_cc_tuser,
s_axis_cc_tlast=m_axis_cc_tlast,
s_axis_cc_tkeep=m_axis_cc_tkeep,
s_axis_cc_tvalid=m_axis_cc_tvalid,
s_axis_cc_tready=m_axis_cc_tready,
# Requester reQuest Interface
s_axis_rq_tdata=m_axis_rq_tdata,
s_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_tlast=m_axis_rq_tlast,
s_axis_rq_tkeep=m_axis_rq_tkeep,
s_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rq_tready=m_axis_rq_tready,
pcie_rq_seq_num=s_axis_rq_seq_num,
pcie_rq_seq_num_vld=s_axis_rq_seq_num_valid,
#pcie_rq_tag=pcie_rq_tag,
#pcie_rq_tag_vld=pcie_rq_tag_vld,
# Requester Completion Interface
m_axis_rc_tdata=s_axis_rc_tdata,
m_axis_rc_tuser=s_axis_rc_tuser,
m_axis_rc_tlast=s_axis_rc_tlast,
m_axis_rc_tkeep=s_axis_rc_tkeep,
m_axis_rc_tvalid=s_axis_rc_tvalid,
m_axis_rc_tready=s_axis_rc_tready,
# Transmit Flow Control Interface
pcie_tfc_nph_av=pcie_tfc_nph_av,
pcie_tfc_npd_av=pcie_tfc_npd_av,
# Configuration Management Interface
cfg_mgmt_addr=cfg_mgmt_addr,
cfg_mgmt_write=cfg_mgmt_write,
cfg_mgmt_write_data=cfg_mgmt_write_data,
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
cfg_mgmt_read=cfg_mgmt_read,
cfg_mgmt_read_data=cfg_mgmt_read_data,
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
#cfg_mgmt_type1_cfg_reg_access=cfg_mgmt_type1_cfg_reg_access,
# Configuration Status Interface
#cfg_phy_link_down=cfg_phy_link_down,
#cfg_phy_link_status=cfg_phy_link_status,
#cfg_negotiated_width=cfg_negotiated_width,
#cfg_current_speed=cfg_current_speed,
cfg_max_payload=cfg_max_payload,
cfg_max_read_req=cfg_max_read_req,
#cfg_function_status=cfg_function_status,
#cfg_vf_status=cfg_vf_status,
#cfg_function_power_state=cfg_function_power_state,
#cfg_vf_power_state=cfg_vf_power_state,
#cfg_link_power_state=cfg_link_power_state,
#cfg_err_cor_out=cfg_err_cor_out,
#cfg_err_nonfatal_out=cfg_err_nonfatal_out,
#cfg_err_fatal_out=cfg_err_fatal_out,
#cfg_ltr_enable=cfg_ltr_enable,
#cfg_ltssm_state=cfg_ltssm_state,
#cfg_rcb_status=cfg_rcb_status,
#cfg_dpa_substate_change=cfg_dpa_substate_change,
#cfg_obff_enable=cfg_obff_enable,
#cfg_pl_status_change=cfg_pl_status_change,
#cfg_tph_requester_enable=cfg_tph_requester_enable,
#cfg_tph_st_mode=cfg_tph_st_mode,
#cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable,
#cfg_vf_tph_st_mode=cfg_vf_tph_st_mode,
# Configuration Received Message Interface
#cfg_msg_received=cfg_msg_received,
#cfg_msg_received_data=cfg_msg_received_data,
#cfg_msg_received_type=cfg_msg_received_type,
# Configuration Transmit Message Interface
#cfg_msg_transmit=cfg_msg_transmit,
#cfg_msg_transmit_type=cfg_msg_transmit_type,
#cfg_msg_transmit_data=cfg_msg_transmit_data,
#cfg_msg_transmit_done=cfg_msg_transmit_done,
# Configuration Flow Control Interface
cfg_fc_ph=cfg_fc_ph,
cfg_fc_pd=cfg_fc_pd,
cfg_fc_nph=cfg_fc_nph,
cfg_fc_npd=cfg_fc_npd,
cfg_fc_cplh=cfg_fc_cplh,
cfg_fc_cpld=cfg_fc_cpld,
cfg_fc_sel=cfg_fc_sel,
# Per-Function Status Interface
#cfg_per_func_status_control=cfg_per_func_status_control,
#cfg_per_func_status_data=cfg_per_func_status_data,
# Configuration Control Interface
#cfg_hot_reset_in=cfg_hot_reset_in,
#cfg_hot_reset_out=cfg_hot_reset_out,
#cfg_config_space_enable=cfg_config_space_enable,
#cfg_per_function_update_done=cfg_per_function_update_done,
#cfg_per_function_number=cfg_per_function_number,
#cfg_per_function_output_request=cfg_per_function_output_request,
#cfg_dsn=cfg_dsn,
#cfg_ds_bus_number=cfg_ds_bus_number,
#cfg_ds_device_number=cfg_ds_device_number,
#cfg_ds_function_number=cfg_ds_function_number,
#cfg_power_state_change_ack=cfg_power_state_change_ack,
#cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
cfg_err_cor_in=status_error_cor,
cfg_err_uncor_in=status_error_uncor,
#cfg_flr_done=cfg_flr_done,
#cfg_vf_flr_done=cfg_vf_flr_done,
#cfg_flr_in_process=cfg_flr_in_process,
#cfg_vf_flr_in_process=cfg_vf_flr_in_process,
#cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
#cfg_link_training_enable=cfg_link_training_enable,
# Configuration Interrupt Controller Interface
#cfg_interrupt_int=cfg_interrupt_int,
#cfg_interrupt_sent=cfg_interrupt_sent,
#cfg_interrupt_pending=cfg_interrupt_pending,
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_pending_status_data_enable=
cfg_interrupt_msi_pending_status_data_enable,
cfg_interrupt_msi_pending_status_function_num=
cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
#cfg_interrupt_msix_enable=cfg_interrupt_msix_enable,
#cfg_interrupt_msix_mask=cfg_interrupt_msix_mask,
#cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable,
#cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask,
#cfg_interrupt_msix_address=cfg_interrupt_msix_address,
#cfg_interrupt_msix_data=cfg_interrupt_msix_data,
#cfg_interrupt_msix_int=cfg_interrupt_msix_int,
#cfg_interrupt_msix_sent=cfg_interrupt_msix_sent,
#cfg_interrupt_msix_fail=cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
# Configuration Extend Interface
#cfg_ext_read_received=cfg_ext_read_received,
#cfg_ext_write_received=cfg_ext_write_received,
#cfg_ext_register_number=cfg_ext_register_number,
#cfg_ext_function_number=cfg_ext_function_number,
#cfg_ext_write_data=cfg_ext_write_data,
#cfg_ext_write_byte_enable=cfg_ext_write_byte_enable,
#cfg_ext_read_data=cfg_ext_read_data,
#cfg_ext_read_data_valid=cfg_ext_read_data_valid,
# Clock and Reset Interface
user_clk=user_clk,
user_reset=user_reset,
sys_clk=sys_clk,
sys_clk_gt=sys_clk,
sys_reset=sys_reset,
#pcie_perstn0_out=pcie_perstn0_out,
#pcie_perstn1_in=pcie_perstn1_in,
#pcie_perstn1_out=pcie_perstn1_out
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
btnu=btnu,
btnl=btnl,
btnd=btnd,
btnr=btnr,
btnc=btnc,
sw=sw,
led=led,
i2c_scl_i=i2c_scl_i,
i2c_scl_o=i2c_scl_o,
i2c_scl_t=i2c_scl_t,
i2c_sda_i=i2c_sda_i,
i2c_sda_o=i2c_sda_o,
i2c_sda_t=i2c_sda_t,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tlast=m_axis_rq_tlast,
m_axis_rq_tready=m_axis_rq_tready,
m_axis_rq_tuser=m_axis_rq_tuser,
m_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rc_tdata=s_axis_rc_tdata,
s_axis_rc_tkeep=s_axis_rc_tkeep,
s_axis_rc_tlast=s_axis_rc_tlast,
s_axis_rc_tready=s_axis_rc_tready,
s_axis_rc_tuser=s_axis_rc_tuser,
s_axis_rc_tvalid=s_axis_rc_tvalid,
s_axis_cq_tdata=s_axis_cq_tdata,
s_axis_cq_tkeep=s_axis_cq_tkeep,
s_axis_cq_tlast=s_axis_cq_tlast,
s_axis_cq_tready=s_axis_cq_tready,
s_axis_cq_tuser=s_axis_cq_tuser,
s_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cc_tdata=m_axis_cc_tdata,
m_axis_cc_tkeep=m_axis_cc_tkeep,
m_axis_cc_tlast=m_axis_cc_tlast,
m_axis_cc_tready=m_axis_cc_tready,
m_axis_cc_tuser=m_axis_cc_tuser,
m_axis_cc_tvalid=m_axis_cc_tvalid,
s_axis_rq_seq_num=s_axis_rq_seq_num,
s_axis_rq_seq_num_valid=s_axis_rq_seq_num_valid,
pcie_tfc_nph_av=pcie_tfc_nph_av,
pcie_tfc_npd_av=pcie_tfc_npd_av,
cfg_max_payload=cfg_max_payload,
cfg_max_read_req=cfg_max_read_req,
cfg_mgmt_addr=cfg_mgmt_addr,
cfg_mgmt_write=cfg_mgmt_write,
cfg_mgmt_write_data=cfg_mgmt_write_data,
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
cfg_mgmt_read=cfg_mgmt_read,
cfg_mgmt_read_data=cfg_mgmt_read_data,
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
cfg_fc_ph=cfg_fc_ph,
cfg_fc_pd=cfg_fc_pd,
cfg_fc_nph=cfg_fc_nph,
cfg_fc_npd=cfg_fc_npd,
cfg_fc_cplh=cfg_fc_cplh,
cfg_fc_cpld=cfg_fc_cpld,
cfg_fc_sel=cfg_fc_sel,
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
cfg_interrupt_msi_pending_status_function_num=
cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_pending_status_data_enable=
cfg_interrupt_msi_pending_status_data_enable,
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
status_error_cor=status_error_cor,
status_error_uncor=status_error_uncor,
qsfp_tx_clk_1=qsfp_tx_clk_1,
qsfp_tx_rst_1=qsfp_tx_rst_1,
qsfp_txd_1=qsfp_txd_1,
qsfp_txc_1=qsfp_txc_1,
qsfp_rx_clk_1=qsfp_rx_clk_1,
qsfp_rx_rst_1=qsfp_rx_rst_1,
qsfp_rxd_1=qsfp_rxd_1,
qsfp_rxc_1=qsfp_rxc_1,
qsfp_tx_clk_2=qsfp_tx_clk_2,
qsfp_tx_rst_2=qsfp_tx_rst_2,
qsfp_txd_2=qsfp_txd_2,
qsfp_txc_2=qsfp_txc_2,
qsfp_rx_clk_2=qsfp_rx_clk_2,
qsfp_rx_rst_2=qsfp_rx_rst_2,
qsfp_rxd_2=qsfp_rxd_2,
qsfp_rxc_2=qsfp_rxc_2,
qsfp_tx_clk_3=qsfp_tx_clk_3,
qsfp_tx_rst_3=qsfp_tx_rst_3,
qsfp_txd_3=qsfp_txd_3,
qsfp_txc_3=qsfp_txc_3,
qsfp_rx_clk_3=qsfp_rx_clk_3,
qsfp_rx_rst_3=qsfp_rx_rst_3,
qsfp_rxd_3=qsfp_rxd_3,
qsfp_rxc_3=qsfp_rxc_3,
qsfp_tx_clk_4=qsfp_tx_clk_4,
qsfp_tx_rst_4=qsfp_tx_rst_4,
qsfp_txd_4=qsfp_txd_4,
qsfp_txc_4=qsfp_txc_4,
qsfp_rx_clk_4=qsfp_rx_clk_4,
qsfp_rx_rst_4=qsfp_rx_rst_4,
qsfp_rxd_4=qsfp_rxd_4,
qsfp_rxc_4=qsfp_rxc_4,
qsfp_modsell=qsfp_modsell,
qsfp_resetl=qsfp_resetl,
qsfp_modprsl=qsfp_modprsl,
qsfp_intl=qsfp_intl,
qsfp_lpmode=qsfp_lpmode,
flash_dq_i=flash_dq_i,
flash_dq_o=flash_dq_o,
flash_dq_oe=flash_dq_oe,
flash_addr=flash_addr,
flash_region=flash_region,
flash_region_oe=flash_region_oe,
flash_ce_n=flash_ce_n,
flash_oe_n=flash_oe_n,
flash_we_n=flash_we_n,
flash_adv_n=flash_adv_n)
@always(delay(5))
def clkgen():
clk.next = not clk
@always(delay(3))
def clkgen2():
qsfp_tx_clk_1.next = not qsfp_tx_clk_1
qsfp_rx_clk_1.next = not qsfp_rx_clk_1
qsfp_tx_clk_2.next = not qsfp_tx_clk_2
qsfp_rx_clk_2.next = not qsfp_rx_clk_2
qsfp_tx_clk_3.next = not qsfp_tx_clk_3
qsfp_rx_clk_3.next = not qsfp_rx_clk_3
qsfp_tx_clk_4.next = not qsfp_tx_clk_4
qsfp_rx_clk_4.next = not qsfp_rx_clk_4
@always_comb
def clk_logic():
sys_clk.next = clk
sys_reset.next = not rst
loopback_enable = Signal(bool(0))
@instance
def loopback():
while True:
yield clk.posedge
if loopback_enable:
if not qsfp_1_sink.empty():
pkt = qsfp_1_sink.recv()
qsfp_1_source.send(pkt)
if not qsfp_2_sink.empty():
pkt = qsfp_2_sink.recv()
qsfp_2_source.send(pkt)
if not qsfp_3_sink.empty():
pkt = qsfp_3_sink.recv()
qsfp_3_source.send(pkt)
if not qsfp_4_sink.empty():
pkt = qsfp_4_sink.recv()
qsfp_4_source.send(pkt)
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
qsfp_tx_rst_1.next = 1
qsfp_rx_rst_1.next = 1
qsfp_tx_rst_2.next = 1
qsfp_rx_rst_2.next = 1
qsfp_tx_rst_3.next = 1
qsfp_rx_rst_3.next = 1
qsfp_tx_rst_4.next = 1
qsfp_rx_rst_4.next = 1
yield clk.posedge
rst.next = 0
qsfp_tx_rst_1.next = 0
qsfp_rx_rst_1.next = 0
qsfp_tx_rst_2.next = 0
qsfp_rx_rst_2.next = 0
qsfp_tx_rst_3.next = 0
qsfp_rx_rst_3.next = 0
qsfp_tx_rst_4.next = 0
qsfp_rx_rst_4.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
current_tag = 1
yield clk.posedge
print("test 1: enumeration")
current_test.next = 1
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
# enable queues
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_SCHED_ENABLE, 0x00000001)
for k in range(driver.interfaces[0].tx_queue_count):
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 4 * k,
0x00000003)
yield from rc.mem_read(driver.hw_addr,
4) # wait for all writes to complete
yield delay(100)
yield clk.posedge
print("test 3: send and receive a packet")
current_test.next = 3
data = bytearray([x % 256 for x in range(1024)])
yield from driver.interfaces[0].start_xmit(data, 0)
yield qsfp_1_sink.wait()
pkt = qsfp_1_sink.recv()
print(pkt)
qsfp_1_source.send(pkt)
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
yield delay(100)
yield clk.posedge
print("test 4: checksum tests")
current_test.next = 4
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80164
test_frame.ip_dest_ip = 0xc0a80165
test_frame.udp_source_port = 1
test_frame.udp_dest_port = 2
test_frame.udp_length = None
test_frame.udp_checksum = None
test_frame.payload = bytearray((x % 256 for x in range(256)))
test_frame.set_udp_pseudo_header_checksum()
axis_frame = test_frame.build_axis()
yield from driver.interfaces[0].start_xmit(axis_frame.data, 0, 34, 6)
yield qsfp_1_sink.wait()
pkt = qsfp_1_sink.recv()
print(pkt)
qsfp_1_source.send(pkt)
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.rx_checksum == frame_checksum(pkt.data)
check_frame = udp_ep.UDPFrame()
check_frame.parse_axis(pkt.data)
assert check_frame.verify_checksums()
yield delay(100)
yield clk.posedge
print("test 5: multiple small packets")
current_test.next = 5
count = 64
pkts = [
bytearray([(x + k) % 256 for x in range(64)]) for k in range(count)
]
loopback_enable.next = True
for p in pkts:
yield from driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.data == pkts[k]
assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(100)
yield clk.posedge
print("test 6: multiple large packets")
current_test.next = 6
count = 64
pkts = [
bytearray([(x + k) % 256 for x in range(1514)])
for k in range(count)
]
loopback_enable.next = True
for p in pkts:
yield from driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.data == pkts[k]
assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(1000)
yield clk.posedge
print("test 7s: TDMA")
current_test.next = 7
count = 16
pkts = [
bytearray([(x + k) % 256 for x in range(1514)])
for k in range(count)
]
loopback_enable.next = True
# configure TDMA
# configure TDMA scheduler
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_SCHED_PERIOD_FNS,
0) # schedule period fns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_SCHED_PERIOD_NS,
40000) # schedule period ns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_L,
0) # schedule period sec (low)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_H,
0) # schedule period sec (high)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_FNS,
0) # timeslot period fns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_NS,
10000) # timeslot period ns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_L,
0) # timeslot period sec (low)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_H,
0) # timeslot period sec (high)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_FNS,
0) # active period fns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_NS,
5000) # active period ns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L,
0) # active period sec (low)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H,
0) # active period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_TDMA_CTRL,
0x00000001) # enable TDMA
# enable queues with global enable off
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_SCHED_ENABLE, 0x00000001)
for k in range(driver.interfaces[0].tx_queue_count):
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 4 * k,
0x00000001)
# configure slots
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[1].hw_addr + 8 * 0,
0x00000001)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[1].hw_addr + 8 * 1,
0x00000002)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[1].hw_addr + 8 * 2,
0x00000004)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[1].hw_addr + 8 * 3,
0x00000008)
yield from rc.mem_read(driver.hw_addr,
4) # wait for all writes to complete
# send packets
for k in range(count):
yield from driver.interfaces[0].start_xmit(pkts[k], k % 4)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
#assert pkt.data == pkts[k]
#assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
DATA_WIDTH = 64
CTRL_WIDTH = (DATA_WIDTH/8)
HDR_WIDTH = 2
BIT_REVERSE = 0
SCRAMBLER_DISABLE = 0
COUNT_125US = 1250/6.4
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
serdes_rx_data = Signal(intbv(0)[DATA_WIDTH:])
serdes_rx_hdr = Signal(intbv(1)[HDR_WIDTH:])
serdes_rx_data_int = Signal(intbv(0)[DATA_WIDTH:])
serdes_rx_hdr_int = Signal(intbv(1)[HDR_WIDTH:])
# Outputs
xgmii_rxd = Signal(intbv(0)[DATA_WIDTH:])
xgmii_rxc = Signal(intbv(0)[CTRL_WIDTH:])
serdes_rx_bitslip = Signal(bool(0))
rx_bad_block = Signal(bool(0))
rx_block_lock = Signal(bool(0))
rx_high_ber = Signal(bool(0))
# sources and sinks
source = baser_serdes_ep.BaseRSerdesSource()
source_logic = source.create_logic(
clk,
tx_data=serdes_rx_data_int,
tx_header=serdes_rx_hdr_int,
name='source'
)
sink = xgmii_ep.XGMIISink()
sink_logic = sink.create_logic(
clk,
rst,
rxd=xgmii_rxd,
rxc=xgmii_rxc,
name='sink'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
xgmii_rxd=xgmii_rxd,
xgmii_rxc=xgmii_rxc,
serdes_rx_data=serdes_rx_data,
serdes_rx_hdr=serdes_rx_hdr,
serdes_rx_bitslip=serdes_rx_bitslip,
rx_bad_block=rx_bad_block,
rx_block_lock=rx_block_lock,
rx_high_ber=rx_high_ber
)
@always(delay(4))
def clkgen():
clk.next = not clk
load_bit_offset = []
@instance
def shift_bits():
bit_offset = 0
last_data = 0
while True:
yield clk.posedge
if load_bit_offset:
bit_offset = load_bit_offset.pop(0)
if serdes_rx_bitslip:
bit_offset += 1
bit_offset = bit_offset % 66
data = int(serdes_rx_data_int) << 2 | int(serdes_rx_hdr_int)
out_data = ((last_data | data << 66) >> 66-bit_offset) & 0x3ffffffffffffffff
last_data = data
serdes_rx_data.next = out_data >> 2
serdes_rx_hdr.next = out_data & 3
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
for payload_len in list(range(16,34)):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = bytearray(range(payload_len))
xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame)
source.send(xgmii_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == xgmii_frame.data
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = bytearray(range(payload_len))
test_frame2 = bytearray(range(payload_len))
xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame1)
xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame2)
source.send(xgmii_frame1)
source.send(xgmii_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == xgmii_frame1.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == xgmii_frame2.data
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: errored frame, length %d" % payload_len)
current_test.next = 3
test_frame1 = bytearray(range(payload_len))
test_frame2 = bytearray(range(payload_len))
xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame1)
xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame2)
xgmii_frame1.error = 1
source.send(xgmii_frame1)
source.send(xgmii_frame2)
yield sink.wait()
rx_frame = sink.recv()
#assert rx_frame.data == xgmii_frame1.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == xgmii_frame2.data
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 4: test frame sync")
current_test.next = 4
assert rx_block_lock
load_bit_offset.append(33)
yield delay(600)
assert not rx_block_lock
assert rx_high_ber
yield delay(3000)
assert rx_block_lock
yield delay(2000)
assert not rx_high_ber
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
btnu = Signal(bool(0))
btnl = Signal(bool(0))
btnd = Signal(bool(0))
btnr = Signal(bool(0))
btnc = Signal(bool(0))
sw = Signal(intbv(0)[4:])
i2c_scl_i = Signal(bool(1))
i2c_sda_i = Signal(bool(1))
m_axis_rq_tready = Signal(bool(0))
s_axis_rc_tdata = Signal(intbv(0)[256:])
s_axis_rc_tkeep = Signal(intbv(0)[8:])
s_axis_rc_tlast = Signal(bool(0))
s_axis_rc_tuser = Signal(intbv(0)[75:])
s_axis_rc_tvalid = Signal(bool(0))
s_axis_cq_tdata = Signal(intbv(0)[256:])
s_axis_cq_tkeep = Signal(intbv(0)[8:])
s_axis_cq_tlast = Signal(bool(0))
s_axis_cq_tuser = Signal(intbv(0)[85:])
s_axis_cq_tvalid = Signal(bool(0))
m_axis_cc_tready = Signal(bool(0))
pcie_tfc_nph_av = Signal(intbv(0)[2:])
pcie_tfc_npd_av = Signal(intbv(0)[2:])
cfg_max_payload = Signal(intbv(0)[3:])
cfg_max_read_req = Signal(intbv(0)[3:])
cfg_mgmt_read_data = Signal(intbv(0)[32:])
cfg_mgmt_read_write_done = Signal(bool(0))
cfg_interrupt_msi_enable = Signal(intbv(0)[4:])
cfg_interrupt_msi_vf_enable = Signal(intbv(0)[8:])
cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:])
cfg_interrupt_msi_mask_update = Signal(bool(0))
cfg_interrupt_msi_data = Signal(intbv(0)[32:])
cfg_interrupt_msi_sent = Signal(bool(0))
cfg_interrupt_msi_fail = Signal(bool(0))
qsfp_tx_clk_1 = Signal(bool(0))
qsfp_tx_rst_1 = Signal(bool(0))
qsfp_rx_clk_1 = Signal(bool(0))
qsfp_rx_rst_1 = Signal(bool(0))
qsfp_rxd_1 = Signal(intbv(0)[64:])
qsfp_rxc_1 = Signal(intbv(0)[8:])
qsfp_tx_clk_2 = Signal(bool(0))
qsfp_tx_rst_2 = Signal(bool(0))
qsfp_rx_clk_2 = Signal(bool(0))
qsfp_rx_rst_2 = Signal(bool(0))
qsfp_rxd_2 = Signal(intbv(0)[64:])
qsfp_rxc_2 = Signal(intbv(0)[8:])
qsfp_tx_clk_3 = Signal(bool(0))
qsfp_tx_rst_3 = Signal(bool(0))
qsfp_rx_clk_3 = Signal(bool(0))
qsfp_rx_rst_3 = Signal(bool(0))
qsfp_rxd_3 = Signal(intbv(0)[64:])
qsfp_rxc_3 = Signal(intbv(0)[8:])
qsfp_tx_clk_4 = Signal(bool(0))
qsfp_tx_rst_4 = Signal(bool(0))
qsfp_rx_clk_4 = Signal(bool(0))
qsfp_rx_rst_4 = Signal(bool(0))
qsfp_rxd_4 = Signal(intbv(0)[64:])
qsfp_rxc_4 = Signal(intbv(0)[8:])
qsfp_modprsl = Signal(bool(1))
qsfp_intl = Signal(bool(1))
flash_dq_i = Signal(intbv(0)[16:])
# Outputs
led = Signal(intbv(0)[8:])
i2c_scl_o = Signal(bool(1))
i2c_scl_t = Signal(bool(1))
i2c_sda_o = Signal(bool(1))
i2c_sda_t = Signal(bool(1))
m_axis_rq_tdata = Signal(intbv(0)[256:])
m_axis_rq_tkeep = Signal(intbv(0)[8:])
m_axis_rq_tlast = Signal(bool(0))
m_axis_rq_tuser = Signal(intbv(0)[60:])
m_axis_rq_tvalid = Signal(bool(0))
s_axis_rc_tready = Signal(bool(0))
s_axis_cq_tready = Signal(bool(0))
m_axis_cc_tdata = Signal(intbv(0)[256:])
m_axis_cc_tkeep = Signal(intbv(0)[8:])
m_axis_cc_tlast = Signal(bool(0))
m_axis_cc_tuser = Signal(intbv(0)[33:])
m_axis_cc_tvalid = Signal(bool(0))
status_error_cor = Signal(bool(0))
status_error_uncor = Signal(bool(0))
cfg_mgmt_addr = Signal(intbv(0)[19:])
cfg_mgmt_write = Signal(bool(0))
cfg_mgmt_write_data = Signal(intbv(0)[32:])
cfg_mgmt_byte_enable = Signal(intbv(0)[4:])
cfg_mgmt_read = Signal(bool(0))
cfg_interrupt_msi_int = Signal(intbv(0)[32:])
cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:])
cfg_interrupt_msi_select = Signal(intbv(0)[4:])
cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[4:])
cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0))
cfg_interrupt_msi_attr = Signal(intbv(0)[3:])
cfg_interrupt_msi_tph_present = Signal(bool(0))
cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:])
cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[9:])
cfg_interrupt_msi_function_number = Signal(intbv(0)[4:])
qsfp_txd_1 = Signal(intbv(0)[64:])
qsfp_txc_1 = Signal(intbv(0)[8:])
qsfp_txd_2 = Signal(intbv(0)[64:])
qsfp_txc_2 = Signal(intbv(0)[8:])
qsfp_txd_3 = Signal(intbv(0)[64:])
qsfp_txc_3 = Signal(intbv(0)[8:])
qsfp_txd_4 = Signal(intbv(0)[64:])
qsfp_txc_4 = Signal(intbv(0)[8:])
qsfp_modsell = Signal(bool(0))
qsfp_resetl = Signal(bool(1))
qsfp_lpmode = Signal(bool(0))
flash_dq_o = Signal(intbv(0)[16:])
flash_dq_oe = Signal(bool(0))
flash_addr = Signal(intbv(0)[23:])
flash_region = Signal(bool(0))
flash_region_oe = Signal(bool(0))
flash_ce_n = Signal(bool(1))
flash_oe_n = Signal(bool(1))
flash_we_n = Signal(bool(1))
flash_adv_n = Signal(bool(1))
# sources and sinks
qsfp_1_source = xgmii_ep.XGMIISource()
qsfp_1_source_logic = qsfp_1_source.create_logic(qsfp_rx_clk_1,
qsfp_rx_rst_1,
txd=qsfp_rxd_1,
txc=qsfp_rxc_1,
name='qsfp_1_source')
qsfp_1_sink = xgmii_ep.XGMIISink()
qsfp_1_sink_logic = qsfp_1_sink.create_logic(qsfp_tx_clk_1,
qsfp_tx_rst_1,
rxd=qsfp_txd_1,
rxc=qsfp_txc_1,
name='qsfp_1_sink')
qsfp_2_source = xgmii_ep.XGMIISource()
qsfp_2_source_logic = qsfp_2_source.create_logic(qsfp_rx_clk_2,
qsfp_rx_rst_2,
txd=qsfp_rxd_2,
txc=qsfp_rxc_2,
name='qsfp_2_source')
qsfp_2_sink = xgmii_ep.XGMIISink()
qsfp_2_sink_logic = qsfp_2_sink.create_logic(qsfp_tx_clk_2,
qsfp_tx_rst_2,
rxd=qsfp_txd_2,
rxc=qsfp_txc_2,
name='qsfp_2_sink')
qsfp_3_source = xgmii_ep.XGMIISource()
qsfp_3_source_logic = qsfp_3_source.create_logic(qsfp_rx_clk_3,
qsfp_rx_rst_3,
txd=qsfp_rxd_3,
txc=qsfp_rxc_3,
name='qsfp_3_source')
qsfp_3_sink = xgmii_ep.XGMIISink()
qsfp_3_sink_logic = qsfp_3_sink.create_logic(qsfp_tx_clk_3,
qsfp_tx_rst_3,
rxd=qsfp_txd_3,
rxc=qsfp_txc_3,
name='qsfp_3_sink')
qsfp_4_source = xgmii_ep.XGMIISource()
qsfp_4_source_logic = qsfp_4_source.create_logic(qsfp_rx_clk_4,
qsfp_rx_rst_4,
txd=qsfp_rxd_4,
txc=qsfp_rxc_4,
name='qsfp_4_source')
qsfp_4_sink = xgmii_ep.XGMIISink()
qsfp_4_sink_logic = qsfp_4_sink.create_logic(qsfp_tx_clk_4,
qsfp_tx_rst_4,
rxd=qsfp_txd_4,
rxc=qsfp_txc_4,
name='qsfp_4_sink')
# Clock and Reset Interface
user_clk = Signal(bool(0))
user_reset = Signal(bool(0))
sys_clk = Signal(bool(0))
sys_reset = Signal(bool(0))
# PCIe devices
rc = pcie.RootComplex()
rc.max_payload_size = 0x1 # 256 bytes
rc.max_read_request_size = 0x5 # 4096 bytes
driver = mqnic.Driver(rc)
dev = pcie_us.UltrascalePCIe()
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.functions[0].msi_multiple_message_capable = 5
dev.functions[0].configure_bar(0, 16 * 1024 * 1024)
dev.functions[0].configure_bar(1, 16 * 1024 * 1024)
rc.make_port().connect(dev)
pcie_logic = dev.create_logic(
# Completer reQuest Interface
m_axis_cq_tdata=s_axis_cq_tdata,
m_axis_cq_tuser=s_axis_cq_tuser,
m_axis_cq_tlast=s_axis_cq_tlast,
m_axis_cq_tkeep=s_axis_cq_tkeep,
m_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cq_tready=s_axis_cq_tready,
#pcie_cq_np_req=pcie_cq_np_req,
pcie_cq_np_req=Signal(bool(1)),
#pcie_cq_np_req_count=pcie_cq_np_req_count,
# Completer Completion Interface
s_axis_cc_tdata=m_axis_cc_tdata,
s_axis_cc_tuser=m_axis_cc_tuser,
s_axis_cc_tlast=m_axis_cc_tlast,
s_axis_cc_tkeep=m_axis_cc_tkeep,
s_axis_cc_tvalid=m_axis_cc_tvalid,
s_axis_cc_tready=m_axis_cc_tready,
# Requester reQuest Interface
s_axis_rq_tdata=m_axis_rq_tdata,
s_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_tlast=m_axis_rq_tlast,
s_axis_rq_tkeep=m_axis_rq_tkeep,
s_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rq_tready=m_axis_rq_tready,
#pcie_rq_seq_num=pcie_rq_seq_num,
#pcie_rq_seq_num_vld=pcie_rq_seq_num_vld,
#pcie_rq_tag=pcie_rq_tag,
#pcie_rq_tag_vld=pcie_rq_tag_vld,
# Requester Completion Interface
m_axis_rc_tdata=s_axis_rc_tdata,
m_axis_rc_tuser=s_axis_rc_tuser,
m_axis_rc_tlast=s_axis_rc_tlast,
m_axis_rc_tkeep=s_axis_rc_tkeep,
m_axis_rc_tvalid=s_axis_rc_tvalid,
m_axis_rc_tready=s_axis_rc_tready,
# Transmit Flow Control Interface
pcie_tfc_nph_av=pcie_tfc_nph_av,
pcie_tfc_npd_av=pcie_tfc_npd_av,
# Configuration Management Interface
cfg_mgmt_addr=cfg_mgmt_addr,
cfg_mgmt_write=cfg_mgmt_write,
cfg_mgmt_write_data=cfg_mgmt_write_data,
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
cfg_mgmt_read=cfg_mgmt_read,
cfg_mgmt_read_data=cfg_mgmt_read_data,
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
#cfg_mgmt_type1_cfg_reg_access=cfg_mgmt_type1_cfg_reg_access,
# Configuration Status Interface
#cfg_phy_link_down=cfg_phy_link_down,
#cfg_phy_link_status=cfg_phy_link_status,
#cfg_negotiated_width=cfg_negotiated_width,
#cfg_current_speed=cfg_current_speed,
cfg_max_payload=cfg_max_payload,
cfg_max_read_req=cfg_max_read_req,
#cfg_function_status=cfg_function_status,
#cfg_vf_status=cfg_vf_status,
#cfg_function_power_state=cfg_function_power_state,
#cfg_vf_power_state=cfg_vf_power_state,
#cfg_link_power_state=cfg_link_power_state,
#cfg_err_cor_out=cfg_err_cor_out,
#cfg_err_nonfatal_out=cfg_err_nonfatal_out,
#cfg_err_fatal_out=cfg_err_fatal_out,
#cfg_ltr_enable=cfg_ltr_enable,
#cfg_ltssm_state=cfg_ltssm_state,
#cfg_rcb_status=cfg_rcb_status,
#cfg_dpa_substate_change=cfg_dpa_substate_change,
#cfg_obff_enable=cfg_obff_enable,
#cfg_pl_status_change=cfg_pl_status_change,
#cfg_tph_requester_enable=cfg_tph_requester_enable,
#cfg_tph_st_mode=cfg_tph_st_mode,
#cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable,
#cfg_vf_tph_st_mode=cfg_vf_tph_st_mode,
# Configuration Received Message Interface
#cfg_msg_received=cfg_msg_received,
#cfg_msg_received_data=cfg_msg_received_data,
#cfg_msg_received_type=cfg_msg_received_type,
# Configuration Transmit Message Interface
#cfg_msg_transmit=cfg_msg_transmit,
#cfg_msg_transmit_type=cfg_msg_transmit_type,
#cfg_msg_transmit_data=cfg_msg_transmit_data,
#cfg_msg_transmit_done=cfg_msg_transmit_done,
# Configuration Flow Control Interface
#cfg_fc_ph=cfg_fc_ph,
#cfg_fc_pd=cfg_fc_pd,
#cfg_fc_nph=cfg_fc_nph,
#cfg_fc_npd=cfg_fc_npd,
#cfg_fc_cplh=cfg_fc_cplh,
#cfg_fc_cpld=cfg_fc_cpld,
#cfg_fc_sel=cfg_fc_sel,
# Per-Function Status Interface
#cfg_per_func_status_control=cfg_per_func_status_control,
#cfg_per_func_status_data=cfg_per_func_status_data,
# Configuration Control Interface
#cfg_hot_reset_in=cfg_hot_reset_in,
#cfg_hot_reset_out=cfg_hot_reset_out,
#cfg_config_space_enable=cfg_config_space_enable,
#cfg_per_function_update_done=cfg_per_function_update_done,
#cfg_per_function_number=cfg_per_function_number,
#cfg_per_function_output_request=cfg_per_function_output_request,
#cfg_dsn=cfg_dsn,
#cfg_ds_bus_number=cfg_ds_bus_number,
#cfg_ds_device_number=cfg_ds_device_number,
#cfg_ds_function_number=cfg_ds_function_number,
#cfg_power_state_change_ack=cfg_power_state_change_ack,
#cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
cfg_err_cor_in=status_error_cor,
cfg_err_uncor_in=status_error_uncor,
#cfg_flr_done=cfg_flr_done,
#cfg_vf_flr_done=cfg_vf_flr_done,
#cfg_flr_in_process=cfg_flr_in_process,
#cfg_vf_flr_in_process=cfg_vf_flr_in_process,
#cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
#cfg_link_training_enable=cfg_link_training_enable,
# Configuration Interrupt Controller Interface
#cfg_interrupt_int=cfg_interrupt_int,
#cfg_interrupt_sent=cfg_interrupt_sent,
#cfg_interrupt_pending=cfg_interrupt_pending,
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_pending_status_data_enable=
cfg_interrupt_msi_pending_status_data_enable,
cfg_interrupt_msi_pending_status_function_num=
cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
#cfg_interrupt_msix_enable=cfg_interrupt_msix_enable,
#cfg_interrupt_msix_mask=cfg_interrupt_msix_mask,
#cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable,
#cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask,
#cfg_interrupt_msix_address=cfg_interrupt_msix_address,
#cfg_interrupt_msix_data=cfg_interrupt_msix_data,
#cfg_interrupt_msix_int=cfg_interrupt_msix_int,
#cfg_interrupt_msix_sent=cfg_interrupt_msix_sent,
#cfg_interrupt_msix_fail=cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
# Configuration Extend Interface
#cfg_ext_read_received=cfg_ext_read_received,
#cfg_ext_write_received=cfg_ext_write_received,
#cfg_ext_register_number=cfg_ext_register_number,
#cfg_ext_function_number=cfg_ext_function_number,
#cfg_ext_write_data=cfg_ext_write_data,
#cfg_ext_write_byte_enable=cfg_ext_write_byte_enable,
#cfg_ext_read_data=cfg_ext_read_data,
#cfg_ext_read_data_valid=cfg_ext_read_data_valid,
# Clock and Reset Interface
user_clk=user_clk,
user_reset=user_reset,
sys_clk=sys_clk,
sys_clk_gt=sys_clk,
sys_reset=sys_reset,
#pcie_perstn0_out=pcie_perstn0_out,
#pcie_perstn1_in=pcie_perstn1_in,
#pcie_perstn1_out=pcie_perstn1_out
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
btnu=btnu,
btnl=btnl,
btnd=btnd,
btnr=btnr,
btnc=btnc,
sw=sw,
led=led,
i2c_scl_i=i2c_scl_i,
i2c_scl_o=i2c_scl_o,
i2c_scl_t=i2c_scl_t,
i2c_sda_i=i2c_sda_i,
i2c_sda_o=i2c_sda_o,
i2c_sda_t=i2c_sda_t,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tlast=m_axis_rq_tlast,
m_axis_rq_tready=m_axis_rq_tready,
m_axis_rq_tuser=m_axis_rq_tuser,
m_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rc_tdata=s_axis_rc_tdata,
s_axis_rc_tkeep=s_axis_rc_tkeep,
s_axis_rc_tlast=s_axis_rc_tlast,
s_axis_rc_tready=s_axis_rc_tready,
s_axis_rc_tuser=s_axis_rc_tuser,
s_axis_rc_tvalid=s_axis_rc_tvalid,
s_axis_cq_tdata=s_axis_cq_tdata,
s_axis_cq_tkeep=s_axis_cq_tkeep,
s_axis_cq_tlast=s_axis_cq_tlast,
s_axis_cq_tready=s_axis_cq_tready,
s_axis_cq_tuser=s_axis_cq_tuser,
s_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cc_tdata=m_axis_cc_tdata,
m_axis_cc_tkeep=m_axis_cc_tkeep,
m_axis_cc_tlast=m_axis_cc_tlast,
m_axis_cc_tready=m_axis_cc_tready,
m_axis_cc_tuser=m_axis_cc_tuser,
m_axis_cc_tvalid=m_axis_cc_tvalid,
pcie_tfc_nph_av=pcie_tfc_nph_av,
pcie_tfc_npd_av=pcie_tfc_npd_av,
cfg_max_payload=cfg_max_payload,
cfg_max_read_req=cfg_max_read_req,
cfg_mgmt_addr=cfg_mgmt_addr,
cfg_mgmt_write=cfg_mgmt_write,
cfg_mgmt_write_data=cfg_mgmt_write_data,
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
cfg_mgmt_read=cfg_mgmt_read,
cfg_mgmt_read_data=cfg_mgmt_read_data,
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
cfg_interrupt_msi_pending_status_function_num=
cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_pending_status_data_enable=
cfg_interrupt_msi_pending_status_data_enable,
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
status_error_cor=status_error_cor,
status_error_uncor=status_error_uncor,
qsfp_tx_clk_1=qsfp_tx_clk_1,
qsfp_tx_rst_1=qsfp_tx_rst_1,
qsfp_txd_1=qsfp_txd_1,
qsfp_txc_1=qsfp_txc_1,
qsfp_rx_clk_1=qsfp_rx_clk_1,
qsfp_rx_rst_1=qsfp_rx_rst_1,
qsfp_rxd_1=qsfp_rxd_1,
qsfp_rxc_1=qsfp_rxc_1,
qsfp_tx_clk_2=qsfp_tx_clk_2,
qsfp_tx_rst_2=qsfp_tx_rst_2,
qsfp_txd_2=qsfp_txd_2,
qsfp_txc_2=qsfp_txc_2,
qsfp_rx_clk_2=qsfp_rx_clk_2,
qsfp_rx_rst_2=qsfp_rx_rst_2,
qsfp_rxd_2=qsfp_rxd_2,
qsfp_rxc_2=qsfp_rxc_2,
qsfp_tx_clk_3=qsfp_tx_clk_3,
qsfp_tx_rst_3=qsfp_tx_rst_3,
qsfp_txd_3=qsfp_txd_3,
qsfp_txc_3=qsfp_txc_3,
qsfp_rx_clk_3=qsfp_rx_clk_3,
qsfp_rx_rst_3=qsfp_rx_rst_3,
qsfp_rxd_3=qsfp_rxd_3,
qsfp_rxc_3=qsfp_rxc_3,
qsfp_tx_clk_4=qsfp_tx_clk_4,
qsfp_tx_rst_4=qsfp_tx_rst_4,
qsfp_txd_4=qsfp_txd_4,
qsfp_txc_4=qsfp_txc_4,
qsfp_rx_clk_4=qsfp_rx_clk_4,
qsfp_rx_rst_4=qsfp_rx_rst_4,
qsfp_rxd_4=qsfp_rxd_4,
qsfp_rxc_4=qsfp_rxc_4,
qsfp_modsell=qsfp_modsell,
qsfp_resetl=qsfp_resetl,
qsfp_modprsl=qsfp_modprsl,
qsfp_intl=qsfp_intl,
qsfp_lpmode=qsfp_lpmode,
flash_dq_i=flash_dq_i,
flash_dq_o=flash_dq_o,
flash_dq_oe=flash_dq_oe,
flash_addr=flash_addr,
flash_region=flash_region,
flash_region_oe=flash_region_oe,
flash_ce_n=flash_ce_n,
flash_oe_n=flash_oe_n,
flash_we_n=flash_we_n,
flash_adv_n=flash_adv_n)
@always(delay(5))
def clkgen():
clk.next = not clk
@always(delay(3))
def clkgen2():
qsfp_tx_clk_1.next = not qsfp_tx_clk_1
qsfp_rx_clk_1.next = not qsfp_rx_clk_1
qsfp_tx_clk_2.next = not qsfp_tx_clk_2
qsfp_rx_clk_2.next = not qsfp_rx_clk_2
qsfp_tx_clk_3.next = not qsfp_tx_clk_3
qsfp_rx_clk_3.next = not qsfp_rx_clk_3
qsfp_tx_clk_4.next = not qsfp_tx_clk_4
qsfp_rx_clk_4.next = not qsfp_rx_clk_4
@always_comb
def clk_logic():
sys_clk.next = clk
sys_reset.next = not rst
loopback_enable = Signal(bool(0))
@instance
def loopback():
while True:
yield clk.posedge
if loopback_enable:
if not qsfp_1_sink.empty():
pkt = qsfp_1_sink.recv()
qsfp_1_source.send(pkt)
if not qsfp_2_sink.empty():
pkt = qsfp_2_sink.recv()
qsfp_2_source.send(pkt)
if not qsfp_3_sink.empty():
pkt = qsfp_3_sink.recv()
qsfp_3_source.send(pkt)
if not qsfp_4_sink.empty():
pkt = qsfp_4_sink.recv()
qsfp_4_source.send(pkt)
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
qsfp_tx_rst_1.next = 1
qsfp_rx_rst_1.next = 1
qsfp_tx_rst_2.next = 1
qsfp_rx_rst_2.next = 1
qsfp_tx_rst_3.next = 1
qsfp_rx_rst_3.next = 1
qsfp_tx_rst_4.next = 1
qsfp_rx_rst_4.next = 1
yield clk.posedge
rst.next = 0
qsfp_tx_rst_1.next = 0
qsfp_rx_rst_1.next = 0
qsfp_tx_rst_2.next = 0
qsfp_rx_rst_2.next = 0
qsfp_tx_rst_3.next = 0
qsfp_rx_rst_3.next = 0
qsfp_tx_rst_4.next = 0
qsfp_rx_rst_4.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
current_tag = 1
yield clk.posedge
print("test 1: enumeration")
current_test.next = 1
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x270, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x274, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x278, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x27C, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x290, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x294, 1000)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x298, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x29C, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x280, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x284, 2000)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x288, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x28C, 0)
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
# enable queues
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr + 0x0040, 0x00000001)
for k in range(32):
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 4 * k,
0x00000001)
yield from rc.mem_read(driver.hw_addr,
4) # wait for all writes to complete
yield delay(100)
yield clk.posedge
print("test 3: send and receive a packet")
current_test.next = 3
data = bytearray([x % 256 for x in range(1024)])
yield from driver.interfaces[0].start_xmit(data, 0)
yield qsfp_1_sink.wait()
pkt = qsfp_1_sink.recv()
print(pkt)
qsfp_1_source.send(pkt)
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
yield delay(100)
yield clk.posedge
print("test 4: multiple small packets")
current_test.next = 4
count = 64
pkts = [
bytearray([(x + k) % 256 for x in range(64)]) for k in range(count)
]
loopback_enable.next = True
for p in pkts:
yield from driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.data == pkts[k]
assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(100)
yield clk.posedge
print("test 5: multiple large packets")
current_test.next = 5
count = 64
pkts = [
bytearray([(x + k) % 256 for x in range(1514)])
for k in range(count)
]
loopback_enable.next = True
for p in pkts:
yield from driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.data == pkts[k]
assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
AXIS_PCIE_DATA_WIDTH = 256
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32)
AXIS_PCIE_RC_USER_WIDTH = 75
AXIS_PCIE_RQ_USER_WIDTH = 60
AXIS_PCIE_CQ_USER_WIDTH = 85
AXIS_PCIE_CC_USER_WIDTH = 33
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
m_axis_rq_tready = Signal(bool(0))
s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_rc_tlast = Signal(bool(0))
s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:])
s_axis_rc_tvalid = Signal(bool(0))
s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_cq_tlast = Signal(bool(0))
s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:])
s_axis_cq_tvalid = Signal(bool(0))
m_axis_cc_tready = Signal(bool(0))
pcie_tfc_nph_av = Signal(intbv(0)[2:])
pcie_tfc_npd_av = Signal(intbv(0)[2:])
cfg_max_payload = Signal(intbv(0)[3:])
cfg_max_read_req = Signal(intbv(0)[3:])
cfg_mgmt_read_data = Signal(intbv(0)[32:])
cfg_mgmt_read_write_done = Signal(bool(0))
cfg_interrupt_msi_enable = Signal(intbv(0)[4:])
cfg_interrupt_msi_vf_enable = Signal(intbv(0)[8:])
cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:])
cfg_interrupt_msi_mask_update = Signal(bool(0))
cfg_interrupt_msi_data = Signal(intbv(0)[32:])
cfg_interrupt_msi_sent = Signal(bool(0))
cfg_interrupt_msi_fail = Signal(bool(0))
sfp_1_tx_clk = Signal(bool(0))
sfp_1_tx_rst = Signal(bool(0))
sfp_1_rx_clk = Signal(bool(0))
sfp_1_rx_rst = Signal(bool(0))
sfp_1_rxd = Signal(intbv(0)[64:])
sfp_1_rxc = Signal(intbv(0)[8:])
sfp_2_tx_clk = Signal(bool(0))
sfp_2_tx_rst = Signal(bool(0))
sfp_2_rx_clk = Signal(bool(0))
sfp_2_rx_rst = Signal(bool(0))
sfp_2_rxd = Signal(intbv(0)[64:])
sfp_2_rxc = Signal(intbv(0)[8:])
sfp_i2c_scl_i = Signal(bool(1))
sfp_1_i2c_sda_i = Signal(bool(1))
sfp_2_i2c_sda_i = Signal(bool(1))
eeprom_i2c_scl_i = Signal(bool(1))
eeprom_i2c_sda_i = Signal(bool(1))
flash_dq_i = Signal(intbv(0)[16:])
# Outputs
sfp_1_led = Signal(intbv(0)[2:])
sfp_2_led = Signal(intbv(0)[2:])
sma_led = Signal(intbv(0)[2:])
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_rq_tlast = Signal(bool(0))
m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
m_axis_rq_tvalid = Signal(bool(0))
s_axis_rc_tready = Signal(bool(0))
s_axis_cq_tready = Signal(bool(0))
m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_cc_tlast = Signal(bool(0))
m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:])
m_axis_cc_tvalid = Signal(bool(0))
status_error_cor = Signal(bool(0))
status_error_uncor = Signal(bool(0))
cfg_mgmt_addr = Signal(intbv(0)[19:])
cfg_mgmt_write = Signal(bool(0))
cfg_mgmt_write_data = Signal(intbv(0)[32:])
cfg_mgmt_byte_enable = Signal(intbv(0)[4:])
cfg_mgmt_read = Signal(bool(0))
cfg_interrupt_msi_int = Signal(intbv(0)[32:])
cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:])
cfg_interrupt_msi_select = Signal(intbv(0)[4:])
cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[4:])
cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0))
cfg_interrupt_msi_attr = Signal(intbv(0)[3:])
cfg_interrupt_msi_tph_present = Signal(bool(0))
cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:])
cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[9:])
cfg_interrupt_msi_function_number = Signal(intbv(0)[4:])
sfp_1_txd = Signal(intbv(0)[64:])
sfp_1_txc = Signal(intbv(0)[8:])
sfp_2_txd = Signal(intbv(0)[64:])
sfp_2_txc = Signal(intbv(0)[8:])
sfp_i2c_scl_o = Signal(bool(1))
sfp_i2c_scl_t = Signal(bool(1))
sfp_1_i2c_sda_o = Signal(bool(1))
sfp_1_i2c_sda_t = Signal(bool(1))
sfp_2_i2c_sda_o = Signal(bool(1))
sfp_2_i2c_sda_t = Signal(bool(1))
eeprom_i2c_scl_o = Signal(bool(1))
eeprom_i2c_scl_t = Signal(bool(1))
eeprom_i2c_sda_o = Signal(bool(1))
eeprom_i2c_sda_t = Signal(bool(1))
flash_dq_o = Signal(intbv(0)[16:])
flash_dq_oe = Signal(bool(0))
flash_addr = Signal(intbv(0)[23:])
flash_region = Signal(bool(0))
flash_region_oe = Signal(bool(0))
flash_ce_n = Signal(bool(1))
flash_oe_n = Signal(bool(1))
flash_we_n = Signal(bool(1))
flash_adv_n = Signal(bool(1))
# sources and sinks
sfp_1_source = xgmii_ep.XGMIISource()
sfp_1_source_logic = sfp_1_source.create_logic(sfp_1_rx_clk,
sfp_1_rx_rst,
txd=sfp_1_rxd,
txc=sfp_1_rxc,
name='sfp_1_source')
sfp_1_sink = xgmii_ep.XGMIISink()
sfp_1_sink_logic = sfp_1_sink.create_logic(sfp_1_tx_clk,
sfp_1_tx_rst,
rxd=sfp_1_txd,
rxc=sfp_1_txc,
name='sfp_1_sink')
sfp_2_source = xgmii_ep.XGMIISource()
sfp_2_source_logic = sfp_2_source.create_logic(sfp_2_rx_clk,
sfp_2_rx_rst,
txd=sfp_2_rxd,
txc=sfp_2_rxc,
name='sfp_2_source')
sfp_2_sink = xgmii_ep.XGMIISink()
sfp_2_sink_logic = sfp_2_sink.create_logic(sfp_2_tx_clk,
sfp_2_tx_rst,
rxd=sfp_2_txd,
rxc=sfp_2_txc,
name='sfp_2_sink')
# Clock and Reset Interface
user_clk = Signal(bool(0))
user_reset = Signal(bool(0))
sys_clk = Signal(bool(0))
sys_reset = Signal(bool(0))
# PCIe devices
rc = pcie.RootComplex()
rc.max_payload_size = 0x1 # 256 bytes
rc.max_read_request_size = 0x5 # 4096 bytes
driver = mqnic.Driver(rc)
dev = pcie_us.UltrascalePCIe()
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.functions[0].msi_multiple_message_capable = 5
dev.functions[0].configure_bar(0, 16 * 1024 * 1024)
dev.functions[0].configure_bar(1, 16 * 1024 * 1024)
rc.make_port().connect(dev)
pcie_logic = dev.create_logic(
# Completer reQuest Interface
m_axis_cq_tdata=s_axis_cq_tdata,
m_axis_cq_tuser=s_axis_cq_tuser,
m_axis_cq_tlast=s_axis_cq_tlast,
m_axis_cq_tkeep=s_axis_cq_tkeep,
m_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cq_tready=s_axis_cq_tready,
#pcie_cq_np_req=pcie_cq_np_req,
pcie_cq_np_req=Signal(bool(1)),
#pcie_cq_np_req_count=pcie_cq_np_req_count,
# Completer Completion Interface
s_axis_cc_tdata=m_axis_cc_tdata,
s_axis_cc_tuser=m_axis_cc_tuser,
s_axis_cc_tlast=m_axis_cc_tlast,
s_axis_cc_tkeep=m_axis_cc_tkeep,
s_axis_cc_tvalid=m_axis_cc_tvalid,
s_axis_cc_tready=m_axis_cc_tready,
# Requester reQuest Interface
s_axis_rq_tdata=m_axis_rq_tdata,
s_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_tlast=m_axis_rq_tlast,
s_axis_rq_tkeep=m_axis_rq_tkeep,
s_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rq_tready=m_axis_rq_tready,
#pcie_rq_seq_num=pcie_rq_seq_num,
#pcie_rq_seq_num_vld=pcie_rq_seq_num_vld,
#pcie_rq_tag=pcie_rq_tag,
#pcie_rq_tag_vld=pcie_rq_tag_vld,
# Requester Completion Interface
m_axis_rc_tdata=s_axis_rc_tdata,
m_axis_rc_tuser=s_axis_rc_tuser,
m_axis_rc_tlast=s_axis_rc_tlast,
m_axis_rc_tkeep=s_axis_rc_tkeep,
m_axis_rc_tvalid=s_axis_rc_tvalid,
m_axis_rc_tready=s_axis_rc_tready,
# Transmit Flow Control Interface
pcie_tfc_nph_av=pcie_tfc_nph_av,
pcie_tfc_npd_av=pcie_tfc_npd_av,
# Configuration Management Interface
cfg_mgmt_addr=cfg_mgmt_addr,
cfg_mgmt_write=cfg_mgmt_write,
cfg_mgmt_write_data=cfg_mgmt_write_data,
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
cfg_mgmt_read=cfg_mgmt_read,
cfg_mgmt_read_data=cfg_mgmt_read_data,
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
#cfg_mgmt_type1_cfg_reg_access=cfg_mgmt_type1_cfg_reg_access,
# Configuration Status Interface
#cfg_phy_link_down=cfg_phy_link_down,
#cfg_phy_link_status=cfg_phy_link_status,
#cfg_negotiated_width=cfg_negotiated_width,
#cfg_current_speed=cfg_current_speed,
cfg_max_payload=cfg_max_payload,
cfg_max_read_req=cfg_max_read_req,
#cfg_function_status=cfg_function_status,
#cfg_vf_status=cfg_vf_status,
#cfg_function_power_state=cfg_function_power_state,
#cfg_vf_power_state=cfg_vf_power_state,
#cfg_link_power_state=cfg_link_power_state,
#cfg_err_cor_out=cfg_err_cor_out,
#cfg_err_nonfatal_out=cfg_err_nonfatal_out,
#cfg_err_fatal_out=cfg_err_fatal_out,
#cfg_ltr_enable=cfg_ltr_enable,
#cfg_ltssm_state=cfg_ltssm_state,
#cfg_rcb_status=cfg_rcb_status,
#cfg_dpa_substate_change=cfg_dpa_substate_change,
#cfg_obff_enable=cfg_obff_enable,
#cfg_pl_status_change=cfg_pl_status_change,
#cfg_tph_requester_enable=cfg_tph_requester_enable,
#cfg_tph_st_mode=cfg_tph_st_mode,
#cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable,
#cfg_vf_tph_st_mode=cfg_vf_tph_st_mode,
# Configuration Received Message Interface
#cfg_msg_received=cfg_msg_received,
#cfg_msg_received_data=cfg_msg_received_data,
#cfg_msg_received_type=cfg_msg_received_type,
# Configuration Transmit Message Interface
#cfg_msg_transmit=cfg_msg_transmit,
#cfg_msg_transmit_type=cfg_msg_transmit_type,
#cfg_msg_transmit_data=cfg_msg_transmit_data,
#cfg_msg_transmit_done=cfg_msg_transmit_done,
# Configuration Flow Control Interface
#cfg_fc_ph=cfg_fc_ph,
#cfg_fc_pd=cfg_fc_pd,
#cfg_fc_nph=cfg_fc_nph,
#cfg_fc_npd=cfg_fc_npd,
#cfg_fc_cplh=cfg_fc_cplh,
#cfg_fc_cpld=cfg_fc_cpld,
#cfg_fc_sel=cfg_fc_sel,
# Per-Function Status Interface
#cfg_per_func_status_control=cfg_per_func_status_control,
#cfg_per_func_status_data=cfg_per_func_status_data,
# Configuration Control Interface
#cfg_hot_reset_in=cfg_hot_reset_in,
#cfg_hot_reset_out=cfg_hot_reset_out,
#cfg_config_space_enable=cfg_config_space_enable,
#cfg_per_function_update_done=cfg_per_function_update_done,
#cfg_per_function_number=cfg_per_function_number,
#cfg_per_function_output_request=cfg_per_function_output_request,
#cfg_dsn=cfg_dsn,
#cfg_ds_bus_number=cfg_ds_bus_number,
#cfg_ds_device_number=cfg_ds_device_number,
#cfg_ds_function_number=cfg_ds_function_number,
#cfg_power_state_change_ack=cfg_power_state_change_ack,
#cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
cfg_err_cor_in=status_error_cor,
cfg_err_uncor_in=status_error_uncor,
#cfg_flr_done=cfg_flr_done,
#cfg_vf_flr_done=cfg_vf_flr_done,
#cfg_flr_in_process=cfg_flr_in_process,
#cfg_vf_flr_in_process=cfg_vf_flr_in_process,
#cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
#cfg_link_training_enable=cfg_link_training_enable,
# Configuration Interrupt Controller Interface
#cfg_interrupt_int=cfg_interrupt_int,
#cfg_interrupt_sent=cfg_interrupt_sent,
#cfg_interrupt_pending=cfg_interrupt_pending,
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_pending_status_data_enable=
cfg_interrupt_msi_pending_status_data_enable,
cfg_interrupt_msi_pending_status_function_num=
cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
#cfg_interrupt_msix_enable=cfg_interrupt_msix_enable,
#cfg_interrupt_msix_mask=cfg_interrupt_msix_mask,
#cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable,
#cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask,
#cfg_interrupt_msix_address=cfg_interrupt_msix_address,
#cfg_interrupt_msix_data=cfg_interrupt_msix_data,
#cfg_interrupt_msix_int=cfg_interrupt_msix_int,
#cfg_interrupt_msix_sent=cfg_interrupt_msix_sent,
#cfg_interrupt_msix_fail=cfg_interrupt_msix_fail,
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
# Configuration Extend Interface
#cfg_ext_read_received=cfg_ext_read_received,
#cfg_ext_write_received=cfg_ext_write_received,
#cfg_ext_register_number=cfg_ext_register_number,
#cfg_ext_function_number=cfg_ext_function_number,
#cfg_ext_write_data=cfg_ext_write_data,
#cfg_ext_write_byte_enable=cfg_ext_write_byte_enable,
#cfg_ext_read_data=cfg_ext_read_data,
#cfg_ext_read_data_valid=cfg_ext_read_data_valid,
# Clock and Reset Interface
user_clk=user_clk,
user_reset=user_reset,
sys_clk=sys_clk,
sys_clk_gt=sys_clk,
sys_reset=sys_reset,
#pcie_perstn0_out=pcie_perstn0_out,
#pcie_perstn1_in=pcie_perstn1_in,
#pcie_perstn1_out=pcie_perstn1_out
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
sfp_1_led=sfp_1_led,
sfp_2_led=sfp_2_led,
sma_led=sma_led,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tlast=m_axis_rq_tlast,
m_axis_rq_tready=m_axis_rq_tready,
m_axis_rq_tuser=m_axis_rq_tuser,
m_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rc_tdata=s_axis_rc_tdata,
s_axis_rc_tkeep=s_axis_rc_tkeep,
s_axis_rc_tlast=s_axis_rc_tlast,
s_axis_rc_tready=s_axis_rc_tready,
s_axis_rc_tuser=s_axis_rc_tuser,
s_axis_rc_tvalid=s_axis_rc_tvalid,
s_axis_cq_tdata=s_axis_cq_tdata,
s_axis_cq_tkeep=s_axis_cq_tkeep,
s_axis_cq_tlast=s_axis_cq_tlast,
s_axis_cq_tready=s_axis_cq_tready,
s_axis_cq_tuser=s_axis_cq_tuser,
s_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cc_tdata=m_axis_cc_tdata,
m_axis_cc_tkeep=m_axis_cc_tkeep,
m_axis_cc_tlast=m_axis_cc_tlast,
m_axis_cc_tready=m_axis_cc_tready,
m_axis_cc_tuser=m_axis_cc_tuser,
m_axis_cc_tvalid=m_axis_cc_tvalid,
pcie_tfc_nph_av=pcie_tfc_nph_av,
pcie_tfc_npd_av=pcie_tfc_npd_av,
cfg_max_payload=cfg_max_payload,
cfg_max_read_req=cfg_max_read_req,
cfg_mgmt_addr=cfg_mgmt_addr,
cfg_mgmt_write=cfg_mgmt_write,
cfg_mgmt_write_data=cfg_mgmt_write_data,
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
cfg_mgmt_read=cfg_mgmt_read,
cfg_mgmt_read_data=cfg_mgmt_read_data,
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable,
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
cfg_interrupt_msi_pending_status_function_num=
cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_pending_status_data_enable=
cfg_interrupt_msi_pending_status_data_enable,
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
status_error_cor=status_error_cor,
status_error_uncor=status_error_uncor,
sfp_1_tx_clk=sfp_1_tx_clk,
sfp_1_tx_rst=sfp_1_tx_rst,
sfp_1_txd=sfp_1_txd,
sfp_1_txc=sfp_1_txc,
sfp_1_rx_clk=sfp_1_rx_clk,
sfp_1_rx_rst=sfp_1_rx_rst,
sfp_1_rxd=sfp_1_rxd,
sfp_1_rxc=sfp_1_rxc,
sfp_2_tx_clk=sfp_2_tx_clk,
sfp_2_tx_rst=sfp_2_tx_rst,
sfp_2_txd=sfp_2_txd,
sfp_2_txc=sfp_2_txc,
sfp_2_rx_clk=sfp_2_rx_clk,
sfp_2_rx_rst=sfp_2_rx_rst,
sfp_2_rxd=sfp_2_rxd,
sfp_2_rxc=sfp_2_rxc,
sfp_i2c_scl_i=sfp_i2c_scl_i,
sfp_i2c_scl_o=sfp_i2c_scl_o,
sfp_i2c_scl_t=sfp_i2c_scl_t,
sfp_1_i2c_sda_i=sfp_1_i2c_sda_i,
sfp_1_i2c_sda_o=sfp_1_i2c_sda_o,
sfp_1_i2c_sda_t=sfp_1_i2c_sda_t,
sfp_2_i2c_sda_i=sfp_2_i2c_sda_i,
sfp_2_i2c_sda_o=sfp_2_i2c_sda_o,
sfp_2_i2c_sda_t=sfp_2_i2c_sda_t,
eeprom_i2c_scl_i=eeprom_i2c_scl_i,
eeprom_i2c_scl_o=eeprom_i2c_scl_o,
eeprom_i2c_scl_t=eeprom_i2c_scl_t,
eeprom_i2c_sda_i=eeprom_i2c_sda_i,
eeprom_i2c_sda_o=eeprom_i2c_sda_o,
eeprom_i2c_sda_t=eeprom_i2c_sda_t,
flash_dq_i=flash_dq_i,
flash_dq_o=flash_dq_o,
flash_dq_oe=flash_dq_oe,
flash_addr=flash_addr,
flash_region=flash_region,
flash_region_oe=flash_region_oe,
flash_ce_n=flash_ce_n,
flash_oe_n=flash_oe_n,
flash_we_n=flash_we_n,
flash_adv_n=flash_adv_n)
@always(delay(5))
def clkgen():
clk.next = not clk
@always_comb
def clk_logic():
sys_clk.next = clk
sys_reset.next = not rst
sfp_1_tx_clk.next = clk
sfp_1_tx_rst.next = rst
sfp_1_rx_clk.next = clk
sfp_1_rx_rst.next = rst
sfp_2_tx_clk.next = clk
sfp_2_tx_rst.next = rst
sfp_2_rx_clk.next = clk
sfp_2_rx_rst.next = rst
loopback_enable = Signal(bool(0))
@instance
def loopback():
while True:
yield clk.posedge
if loopback_enable:
if not sfp_1_sink.empty():
pkt = sfp_1_sink.recv()
sfp_1_source.send(pkt)
if not sfp_2_sink.empty():
pkt = sfp_2_sink.recv()
sfp_2_source.send(pkt)
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
current_tag = 1
yield clk.posedge
print("test 1: enumeration")
current_test.next = 1
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x270, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x274, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x278, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x27C, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x290, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x294, 1000)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x298, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x29C, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x280, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x284, 2000)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x288, 0)
yield from rc.mem_write_dword(dev_pf0_bar0 + 0x28C, 0)
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
# enable queues
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0200,
0xffffffff)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0300,
0xffffffff)
yield from rc.mem_read(driver.hw_addr,
4) # wait for all writes to complete
yield delay(100)
yield clk.posedge
print("test 3: send and receive a packet")
current_test.next = 3
data = bytearray([x % 256 for x in range(1024)])
yield from driver.interfaces[0].start_xmit(data, 0)
yield sfp_1_sink.wait()
pkt = sfp_1_sink.recv()
print(pkt)
sfp_1_source.send(pkt)
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
yield delay(100)
yield clk.posedge
print("test 4: checksum tests")
current_test.next = 4
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80164
test_frame.ip_dest_ip = 0xc0a80165
test_frame.udp_source_port = 1
test_frame.udp_dest_port = 2
test_frame.udp_length = None
test_frame.udp_checksum = None
test_frame.payload = bytearray((x % 256 for x in range(256)))
test_frame.set_udp_pseudo_header_checksum()
axis_frame = test_frame.build_axis()
yield from driver.interfaces[0].start_xmit(axis_frame.data, 0, 34, 6)
yield sfp_1_sink.wait()
pkt = sfp_1_sink.recv()
print(pkt)
sfp_1_source.send(pkt)
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.rx_checksum == frame_checksum(pkt.data)
check_frame = udp_ep.UDPFrame()
check_frame.parse_axis(pkt.data)
assert check_frame.verify_checksums()
yield delay(100)
yield clk.posedge
print("test 5: multiple small packets")
current_test.next = 5
count = 64
pkts = [
bytearray([(x + k) % 256 for x in range(64)]) for k in range(count)
]
loopback_enable.next = True
for p in pkts:
yield from driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.data == pkts[k]
assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(100)
yield clk.posedge
print("test 6: multiple large packets")
current_test.next = 6
count = 64
pkts = [
bytearray([(x + k) % 256 for x in range(1514)])
for k in range(count)
]
loopback_enable.next = True
for p in pkts:
yield from driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.data == pkts[k]
assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(1000)
yield clk.posedge
print("test 7: TDMA")
current_test.next = 7
count = 16
pkts = [
bytearray([(x + k) % 256 for x in range(1514)])
for k in range(count)
]
loopback_enable.next = True
# configure TDMA
# configure TDMA scheduler
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00120,
0) # schedule period fns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00124,
40000) # schedule period ns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00128,
0) # schedule period sec (low)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0012c,
0) # schedule period sec (high)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00130,
0) # timeslot period fns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00134,
10000) # timeslot period ns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00138,
0) # timeslot period sec (low)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0013c,
0) # timeslot period sec (high)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00140,
0) # active period fns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00144,
5000) # active period ns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00148,
0) # active period sec (low)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0014c,
0) # active period sec (high)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00110,
0) # schedule start fns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00114,
200000) # schedule start ns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00118,
0) # schedule start sec (low)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0011c,
0) # schedule start sec (high)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00100,
0x00000001)
# enable queues
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00200,
0xffffffff)
# disable global enable
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00300,
0x00000000)
# configure slots
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10000,
0x00000001)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10100,
0x00000002)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10200,
0x00000004)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10300,
0x00000008)
yield from rc.mem_read(driver.hw_addr,
4) # wait for all writes to complete
# send packets
for k in range(count):
yield from driver.interfaces[0].start_xmit(pkts[k], k % 4)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
#assert pkt.data == pkts[k]
#assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
btn = Signal(intbv(0)[4:])
sw = Signal(intbv(0)[4:])
sfp_a_rxd = Signal(intbv(0)[64:])
sfp_a_rxc = Signal(intbv(0)[8:])
sfp_b_rxd = Signal(intbv(0)[64:])
sfp_b_rxc = Signal(intbv(0)[8:])
sfp_c_rxd = Signal(intbv(0)[64:])
sfp_c_rxc = Signal(intbv(0)[8:])
sfp_d_rxd = Signal(intbv(0)[64:])
sfp_d_rxc = Signal(intbv(0)[8:])
# Outputs
led = Signal(intbv(0)[4:])
led_bkt = Signal(intbv(0)[4:])
led_hex0_d = Signal(intbv(0)[7:])
led_hex0_dp = Signal(bool(0))
led_hex1_d = Signal(intbv(0)[7:])
led_hex1_dp = Signal(bool(0))
sfp_a_txd = Signal(intbv(0)[64:])
sfp_a_txc = Signal(intbv(0)[8:])
sfp_b_txd = Signal(intbv(0)[64:])
sfp_b_txc = Signal(intbv(0)[8:])
sfp_c_txd = Signal(intbv(0)[64:])
sfp_c_txc = Signal(intbv(0)[8:])
sfp_d_txd = Signal(intbv(0)[64:])
sfp_d_txc = Signal(intbv(0)[8:])
# sources and sinks
sfp_a_source = xgmii_ep.XGMIISource()
sfp_a_source_logic = sfp_a_source.create_logic(clk,
rst,
txd=sfp_a_rxd,
txc=sfp_a_rxc,
name='sfp_a_source')
sfp_a_sink = xgmii_ep.XGMIISink()
sfp_a_sink_logic = sfp_a_sink.create_logic(clk,
rst,
rxd=sfp_a_txd,
rxc=sfp_a_txc,
name='sfp_a_sink')
sfp_b_source = xgmii_ep.XGMIISource()
sfp_b_source_logic = sfp_b_source.create_logic(clk,
rst,
txd=sfp_b_rxd,
txc=sfp_b_rxc,
name='sfp_b_source')
sfp_b_sink = xgmii_ep.XGMIISink()
sfp_b_sink_logic = sfp_b_sink.create_logic(clk,
rst,
rxd=sfp_b_txd,
rxc=sfp_b_txc,
name='sfp_b_sink')
sfp_c_source = xgmii_ep.XGMIISource()
sfp_c_source_logic = sfp_c_source.create_logic(clk,
rst,
txd=sfp_c_rxd,
txc=sfp_c_rxc,
name='sfp_c_source')
sfp_c_sink = xgmii_ep.XGMIISink()
sfp_c_sink_logic = sfp_c_sink.create_logic(clk,
rst,
rxd=sfp_c_txd,
rxc=sfp_c_txc,
name='sfp_c_sink')
sfp_d_source = xgmii_ep.XGMIISource()
sfp_d_source_logic = sfp_d_source.create_logic(clk,
rst,
txd=sfp_d_rxd,
txc=sfp_d_rxc,
name='sfp_d_source')
sfp_d_sink = xgmii_ep.XGMIISink()
sfp_d_sink_logic = sfp_d_sink.create_logic(clk,
rst,
rxd=sfp_d_txd,
rxc=sfp_d_txc,
name='sfp_d_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
btn=btn,
sw=sw,
led=led,
led_bkt=led_bkt,
led_hex0_d=led_hex0_d,
led_hex0_dp=led_hex0_dp,
led_hex1_d=led_hex1_d,
led_hex1_dp=led_hex1_dp,
sfp_a_txd=sfp_a_txd,
sfp_a_txc=sfp_a_txc,
sfp_a_rxd=sfp_a_rxd,
sfp_a_rxc=sfp_a_rxc,
sfp_b_txd=sfp_b_txd,
sfp_b_txc=sfp_b_txc,
sfp_b_rxd=sfp_b_rxd,
sfp_b_rxc=sfp_b_rxc,
sfp_c_txd=sfp_c_txd,
sfp_c_txc=sfp_c_txc,
sfp_c_rxd=sfp_c_rxd,
sfp_c_rxc=sfp_c_rxc,
sfp_d_txd=sfp_d_txd,
sfp_d_txc=sfp_d_txc,
sfp_d_rxd=sfp_d_rxd,
sfp_d_rxc=sfp_d_rxc)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test UDP RX packet")
current_test.next = 1
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 5678
test_frame.udp_dest_port = 1234
test_frame.payload = bytearray(range(32))
test_frame.build()
sfp_a_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame.build_eth().build_axis_fcs().data)
# wait for ARP request packet
while sfp_a_sink.empty():
yield clk.posedge
rx_frame = sfp_a_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 1
assert check_frame.arp_sha == 0x020000000000
assert check_frame.arp_spa == 0xc0a80180
assert check_frame.arp_tha == 0x000000000000
assert check_frame.arp_tpa == 0xc0a80181
# generate response
arp_frame = arp_ep.ARPFrame()
arp_frame.eth_dest_mac = 0x020000000000
arp_frame.eth_src_mac = 0xDAD1D2D3D4D5
arp_frame.eth_type = 0x0806
arp_frame.arp_htype = 0x0001
arp_frame.arp_ptype = 0x0800
arp_frame.arp_hlen = 6
arp_frame.arp_plen = 4
arp_frame.arp_oper = 2
arp_frame.arp_sha = 0xDAD1D2D3D4D5
arp_frame.arp_spa = 0xc0a80181
arp_frame.arp_tha = 0x020000000000
arp_frame.arp_tpa = 0xc0a80180
sfp_a_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
arp_frame.build_eth().build_axis_fcs().data)
while sfp_a_sink.empty():
yield clk.posedge
rx_frame = sfp_a_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 1234
assert check_frame.udp_dest_port == 5678
assert check_frame.payload.data == bytearray(range(32))
assert sfp_a_source.empty()
assert sfp_a_sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
btnu = Signal(bool(0))
btnl = Signal(bool(0))
btnd = Signal(bool(0))
btnr = Signal(bool(0))
btnc = Signal(bool(0))
sw = Signal(intbv(0)[4:])
qsfp_rxd_1 = Signal(intbv(0)[64:])
qsfp_rxc_1 = Signal(intbv(0)[8:])
qsfp_rxd_2 = Signal(intbv(0)[64:])
qsfp_rxc_2 = Signal(intbv(0)[8:])
qsfp_rxd_3 = Signal(intbv(0)[64:])
qsfp_rxc_3 = Signal(intbv(0)[8:])
qsfp_rxd_4 = Signal(intbv(0)[64:])
qsfp_rxc_4 = Signal(intbv(0)[8:])
phy_gmii_clk = Signal(bool(0))
phy_gmii_rst = Signal(bool(0))
phy_gmii_clk_en = Signal(bool(0))
phy_gmii_rxd = Signal(intbv(0)[8:])
phy_gmii_rx_dv = Signal(bool(0))
phy_gmii_rx_er = Signal(bool(0))
phy_int_n = Signal(bool(1))
uart_rxd = Signal(bool(0))
uart_cts = Signal(bool(0))
# Outputs
led = Signal(intbv(0)[8:])
qsfp_txd_1 = Signal(intbv(0)[64:])
qsfp_txc_1 = Signal(intbv(0)[8:])
qsfp_txd_2 = Signal(intbv(0)[64:])
qsfp_txc_2 = Signal(intbv(0)[8:])
qsfp_txd_3 = Signal(intbv(0)[64:])
qsfp_txc_3 = Signal(intbv(0)[8:])
qsfp_txd_4 = Signal(intbv(0)[64:])
qsfp_txc_4 = Signal(intbv(0)[8:])
phy_gmii_txd = Signal(intbv(0)[8:])
phy_gmii_tx_en = Signal(bool(0))
phy_gmii_tx_er = Signal(bool(0))
phy_reset_n = Signal(bool(0))
uart_txd = Signal(bool(0))
uart_rts = Signal(bool(0))
# sources and sinks
qsfp_1_source = xgmii_ep.XGMIISource()
qsfp_1_source_logic = qsfp_1_source.create_logic(clk, rst, txd=qsfp_rxd_1, txc=qsfp_rxc_1, name='qsfp_1_source')
qsfp_1_sink = xgmii_ep.XGMIISink()
qsfp_1_sink_logic = qsfp_1_sink.create_logic(clk, rst, rxd=qsfp_txd_1, rxc=qsfp_txc_1, name='qsfp_1_sink')
qsfp_2_source = xgmii_ep.XGMIISource()
qsfp_2_source_logic = qsfp_2_source.create_logic(clk, rst, txd=qsfp_rxd_2, txc=qsfp_rxc_2, name='qsfp_2_source')
qsfp_2_sink = xgmii_ep.XGMIISink()
qsfp_2_sink_logic = qsfp_2_sink.create_logic(clk, rst, rxd=qsfp_txd_2, rxc=qsfp_txc_2, name='qsfp_2_sink')
qsfp_3_source = xgmii_ep.XGMIISource()
qsfp_3_source_logic = qsfp_3_source.create_logic(clk, rst, txd=qsfp_rxd_3, txc=qsfp_rxc_3, name='qsfp_3_source')
qsfp_3_sink = xgmii_ep.XGMIISink()
qsfp_3_sink_logic = qsfp_3_sink.create_logic(clk, rst, rxd=qsfp_txd_3, rxc=qsfp_txc_3, name='qsfp_3_sink')
qsfp_4_source = xgmii_ep.XGMIISource()
qsfp_4_source_logic = qsfp_4_source.create_logic(clk, rst, txd=qsfp_rxd_4, txc=qsfp_rxc_4, name='qsfp_4_source')
qsfp_4_sink = xgmii_ep.XGMIISink()
qsfp_4_sink_logic = qsfp_4_sink.create_logic(clk, rst, rxd=qsfp_txd_4, rxc=qsfp_txc_4, name='qsfp_4_sink')
gmii_source = gmii_ep.GMIISource()
gmii_source_logic = gmii_source.create_logic(
phy_gmii_clk,
phy_gmii_rst,
txd=phy_gmii_rxd,
tx_en=phy_gmii_rx_dv,
tx_er=phy_gmii_rx_er,
clk_enable=phy_gmii_clk_en,
name='gmii_source'
)
gmii_sink = gmii_ep.GMIISink()
gmii_sink_logic = gmii_sink.create_logic(
phy_gmii_clk,
phy_gmii_rst,
rxd=phy_gmii_txd,
rx_dv=phy_gmii_tx_en,
rx_er=phy_gmii_tx_er,
clk_enable=phy_gmii_clk_en,
name='gmii_sink'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
btnu=btnu,
btnl=btnl,
btnd=btnd,
btnr=btnr,
btnc=btnc,
sw=sw,
led=led,
qsfp_txd_1=qsfp_txd_1,
qsfp_txc_1=qsfp_txc_1,
qsfp_rxd_1=qsfp_rxd_1,
qsfp_rxc_1=qsfp_rxc_1,
qsfp_txd_2=qsfp_txd_2,
qsfp_txc_2=qsfp_txc_2,
qsfp_rxd_2=qsfp_rxd_2,
qsfp_rxc_2=qsfp_rxc_2,
qsfp_txd_3=qsfp_txd_3,
qsfp_txc_3=qsfp_txc_3,
qsfp_rxd_3=qsfp_rxd_3,
qsfp_rxc_3=qsfp_rxc_3,
qsfp_txd_4=qsfp_txd_4,
qsfp_txc_4=qsfp_txc_4,
qsfp_rxd_4=qsfp_rxd_4,
qsfp_rxc_4=qsfp_rxc_4,
phy_gmii_clk=phy_gmii_clk,
phy_gmii_rst=phy_gmii_rst,
phy_gmii_clk_en=phy_gmii_clk_en,
phy_gmii_rxd=phy_gmii_rxd,
phy_gmii_rx_dv=phy_gmii_rx_dv,
phy_gmii_rx_er=phy_gmii_rx_er,
phy_gmii_txd=phy_gmii_txd,
phy_gmii_tx_en=phy_gmii_tx_en,
phy_gmii_tx_er=phy_gmii_tx_er,
phy_reset_n=phy_reset_n,
phy_int_n=phy_int_n,
uart_rxd=uart_rxd,
uart_txd=uart_txd,
uart_rts=uart_rts,
uart_cts=uart_cts
)
@always(delay(4))
def clkgen():
clk.next = not clk
phy_gmii_clk.next = not phy_gmii_clk
clk_enable_rate = Signal(int(0))
clk_enable_div = Signal(int(0))
@always(clk.posedge)
def clk_enable_gen():
if clk_enable_div.next > 0:
phy_gmii_clk_en.next = 0
clk_enable_div.next = clk_enable_div - 1
else:
phy_gmii_clk_en.next = 1
clk_enable_div.next = clk_enable_rate - 1
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
phy_gmii_rst.next = 1
yield clk.posedge
rst.next = 0
phy_gmii_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test UDP RX packet")
current_test.next = 1
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 5678
test_frame.udp_dest_port = 1234
test_frame.payload = bytearray(range(32))
test_frame.build()
qsfp_1_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame.build_eth().build_axis_fcs().data)
# wait for ARP request packet
while qsfp_1_sink.empty():
yield clk.posedge
rx_frame = qsfp_1_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 1
assert check_frame.arp_sha == 0x020000000000
assert check_frame.arp_spa == 0xc0a80180
assert check_frame.arp_tha == 0x000000000000
assert check_frame.arp_tpa == 0xc0a80181
# generate response
arp_frame = arp_ep.ARPFrame()
arp_frame.eth_dest_mac = 0x020000000000
arp_frame.eth_src_mac = 0xDAD1D2D3D4D5
arp_frame.eth_type = 0x0806
arp_frame.arp_htype = 0x0001
arp_frame.arp_ptype = 0x0800
arp_frame.arp_hlen = 6
arp_frame.arp_plen = 4
arp_frame.arp_oper = 2
arp_frame.arp_sha = 0xDAD1D2D3D4D5
arp_frame.arp_spa = 0xc0a80181
arp_frame.arp_tha = 0x020000000000
arp_frame.arp_tpa = 0xc0a80180
qsfp_1_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+arp_frame.build_eth().build_axis_fcs().data)
while qsfp_1_sink.empty():
yield clk.posedge
rx_frame = qsfp_1_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 1234
assert check_frame.udp_dest_port == 5678
assert check_frame.payload.data == bytearray(range(32))
assert qsfp_1_source.empty()
assert qsfp_1_sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: test gigabit tap")
current_test.next = 2
sw.next = 0x8 # enable tap on RX
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 5678
test_frame.udp_dest_port = 1234
test_frame.payload = bytearray(range(32))
test_frame.build()
gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame.build_eth().build_axis_fcs().data)
# loop packet back through on XGMII interface
while qsfp_1_sink.empty():
yield clk.posedge
qsfp_1_source.send(qsfp_1_sink.recv())
while gmii_sink.empty():
yield clk.posedge
rx_frame = gmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 1234
assert check_frame.udp_dest_port == 5678
assert check_frame.payload.data == bytearray(range(32))
assert gmii_source.empty()
assert gmii_sink.empty()
assert qsfp_1_source.empty()
assert qsfp_1_sink.empty()
yield delay(100)
sw.next = 0xc # enable tap on TX
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 5678
test_frame.udp_dest_port = 1234
test_frame.payload = bytearray(range(32))
test_frame.build()
gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame.build_eth().build_axis_fcs().data)
# loop packet back through on XGMII interface
while qsfp_1_sink.empty():
yield clk.posedge
qsfp_1_source.send(qsfp_1_sink.recv())
while gmii_sink.empty():
yield clk.posedge
rx_frame = gmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 1234
assert check_frame.udp_dest_port == 5678
assert check_frame.payload.data == bytearray(range(32))
assert gmii_source.empty()
assert gmii_sink.empty()
assert qsfp_1_source.empty()
assert qsfp_1_sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
ENABLE_PADDING = 1
ENABLE_DIC = 1
MIN_FRAME_LENGTH = 64
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
rx_clk = Signal(bool(0))
rx_rst = Signal(bool(0))
tx_clk = Signal(bool(0))
tx_rst = Signal(bool(0))
tx_axis_tdata = Signal(intbv(0)[64:])
tx_axis_tkeep = Signal(intbv(0)[8:])
tx_axis_tvalid = Signal(bool(0))
tx_axis_tlast = Signal(bool(0))
tx_axis_tuser = Signal(bool(0))
xgmii_rxd = Signal(intbv(0x0707070707070707)[64:])
xgmii_rxc = Signal(intbv(0xff)[8:])
ifg_delay = Signal(intbv(0)[8:])
# Outputs
tx_axis_tready = Signal(bool(0))
rx_axis_tdata = Signal(intbv(0)[64:])
rx_axis_tkeep = Signal(intbv(0)[8:])
rx_axis_tvalid = Signal(bool(0))
rx_axis_tlast = Signal(bool(0))
rx_axis_tuser = Signal(bool(0))
xgmii_txd = Signal(intbv(0x0707070707070707)[64:])
xgmii_txc = Signal(intbv(0xff)[8:])
rx_error_bad_frame = Signal(bool(0))
rx_error_bad_fcs = Signal(bool(0))
# sources and sinks
axis_source_pause = Signal(bool(0))
xgmii_source = xgmii_ep.XGMIISource()
xgmii_source_logic = xgmii_source.create_logic(clk,
rst,
txd=xgmii_rxd,
txc=xgmii_rxc,
name='xgmii_source')
xgmii_sink = xgmii_ep.XGMIISink()
xgmii_sink_logic = xgmii_sink.create_logic(clk,
rst,
rxd=xgmii_txd,
rxc=xgmii_txc,
name='xgmii_sink')
axis_source = axis_ep.AXIStreamSource()
axis_source_logic = axis_source.create_logic(clk,
rst,
tdata=tx_axis_tdata,
tkeep=tx_axis_tkeep,
tvalid=tx_axis_tvalid,
tready=tx_axis_tready,
tlast=tx_axis_tlast,
tuser=tx_axis_tuser,
pause=axis_source_pause,
name='axis_source')
axis_sink = axis_ep.AXIStreamSink()
axis_sink_logic = axis_sink.create_logic(clk,
rst,
tdata=rx_axis_tdata,
tkeep=rx_axis_tkeep,
tvalid=rx_axis_tvalid,
tlast=rx_axis_tlast,
tuser=rx_axis_tuser,
name='axis_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
rx_clk=rx_clk,
rx_rst=rx_rst,
tx_clk=tx_clk,
tx_rst=tx_rst,
tx_axis_tdata=tx_axis_tdata,
tx_axis_tkeep=tx_axis_tkeep,
tx_axis_tvalid=tx_axis_tvalid,
tx_axis_tready=tx_axis_tready,
tx_axis_tlast=tx_axis_tlast,
tx_axis_tuser=tx_axis_tuser,
rx_axis_tdata=rx_axis_tdata,
rx_axis_tkeep=rx_axis_tkeep,
rx_axis_tvalid=rx_axis_tvalid,
rx_axis_tlast=rx_axis_tlast,
rx_axis_tuser=rx_axis_tuser,
xgmii_rxd=xgmii_rxd,
xgmii_rxc=xgmii_rxc,
xgmii_txd=xgmii_txd,
xgmii_txc=xgmii_txc,
rx_error_bad_frame=rx_error_bad_frame,
rx_error_bad_fcs=rx_error_bad_fcs,
ifg_delay=ifg_delay)
@always(delay(4))
def clkgen():
clk.next = not clk
tx_clk.next = not tx_clk
rx_clk.next = not rx_clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
tx_rst.next = 1
rx_rst.next = 1
yield clk.posedge
rst.next = 0
tx_rst.next = 0
rx_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
yield clk.posedge
print("test 1: test rx packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
xgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
bytearray(axis_frame))
yield clk.posedge
yield clk.posedge
while xgmii_rxc != 0xff or rx_axis_tvalid or not xgmii_source.empty():
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = axis_sink.recv()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: test tx packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
axis_source.send(axis_frame)
yield clk.posedge
yield clk.posedge
while xgmii_txc != 0xff or tx_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = xgmii_sink.recv()
assert rx_frame.data[0:8] == bytearray(
b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == 46
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
yield delay(100)
raise StopSimulation
return dut, axis_source_logic, axis_sink_logic, xgmii_source_logic, xgmii_sink_logic, clkgen, check
def bench():
# Parameters
DATA_WIDTH = 64
CTRL_WIDTH = (DATA_WIDTH / 8)
HDR_WIDTH = 2
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
encoded_rx_data = Signal(intbv(0)[DATA_WIDTH:])
encoded_rx_hdr = Signal(intbv(0)[HDR_WIDTH:])
# Outputs
xgmii_rxd = Signal(intbv(0)[DATA_WIDTH:])
xgmii_rxc = Signal(intbv(0)[CTRL_WIDTH:])
rx_bad_block = Signal(bool(0))
# sources and sinks
source = baser_serdes_ep.BaseRSerdesSource()
source_logic = source.create_logic(clk,
tx_data=encoded_rx_data,
tx_header=encoded_rx_hdr,
scramble=False,
name='source')
sink = xgmii_ep.XGMIISink()
sink_logic = sink.create_logic(clk,
rst,
rxd=xgmii_rxd,
rxc=xgmii_rxc,
name='sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
xgmii_rxd=xgmii_rxd,
xgmii_rxc=xgmii_rxc,
encoded_rx_data=encoded_rx_data,
encoded_rx_hdr=encoded_rx_hdr,
rx_bad_block=rx_bad_block)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
for payload_len in list(range(16, 34)):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = bytearray(range(payload_len))
xgmii_frame = xgmii_ep.XGMIIFrame(
b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame)
source.send(xgmii_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == xgmii_frame.data
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = bytearray(range(payload_len))
test_frame2 = bytearray(range(payload_len))
xgmii_frame1 = xgmii_ep.XGMIIFrame(
b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame1)
xgmii_frame2 = xgmii_ep.XGMIIFrame(
b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame2)
source.send(xgmii_frame1)
source.send(xgmii_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == xgmii_frame1.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == xgmii_frame2.data
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: errored frame, length %d" % payload_len)
current_test.next = 3
test_frame1 = bytearray(range(payload_len))
test_frame2 = bytearray(range(payload_len))
xgmii_frame1 = xgmii_ep.XGMIIFrame(
b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame1)
xgmii_frame2 = xgmii_ep.XGMIIFrame(
b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame2)
xgmii_frame1.error = 1
source.send(xgmii_frame1)
source.send(xgmii_frame2)
yield sink.wait()
rx_frame = sink.recv()
#assert rx_frame.data == xgmii_frame1.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == xgmii_frame2.data
assert sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
ENABLE_PADDING = 1
MIN_FRAME_LENGTH = 64
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
ifg_delay = Signal(intbv(0)[8:])
# Outputs
input_axis_tready = Signal(bool(0))
xgmii_txd = Signal(intbv(0x0707070707070707)[64:])
xgmii_txc = Signal(intbv(0xff)[8:])
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = xgmii_ep.XGMIISink(clk,
rst,
rxd=xgmii_txd,
rxc=xgmii_txc,
fifo=sink_queue,
name='sink')
# DUT
dut = dut_eth_mac_10g_tx(clk, rst, current_test, input_axis_tdata,
input_axis_tkeep, input_axis_tvalid,
input_axis_tready, input_axis_tlast,
input_axis_tuser, xgmii_txd, xgmii_txc, ifg_delay)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
for payload_len in list(range(1, 18)) + list(range(40, 58)):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(payload_len))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
source_queue.put(axis_frame)
yield clk.posedge
yield clk.posedge
while xgmii_txc != 0xff or input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame.data[0:8] == bytearray(
b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
assert sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
source_queue.put(axis_frame1)
source_queue.put(axis_frame2)
yield clk.posedge
yield clk.posedge
while xgmii_txc != 0xff or input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame.data[0:8] == bytearray(
b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame1.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame1.eth_src_mac
assert eth_frame.eth_type == test_frame1.eth_type
assert eth_frame.payload.data.index(test_frame1.payload.data) == 0
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame.data[0:8] == bytearray(
b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
assert eth_frame.eth_type == test_frame2.eth_type
assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
assert sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
axis_frame1.user = 1
source_queue.put(axis_frame1)
source_queue.put(axis_frame2)
yield clk.posedge
yield clk.posedge
while xgmii_txc != 0xff or input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame.data[0:8] == bytearray(
b'\x55\x55\x55\x55\x55\x55\x55\xD5')
assert rx_frame.error[-1]
# bad packet
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame.data[0:8] == bytearray(
b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
assert eth_frame.eth_type == test_frame2.eth_type
assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
assert sink_queue.empty()
yield delay(100)
for payload_len in list(range(46, 54)):
yield clk.posedge
print("test 4: test stream, length %d" % payload_len)
current_test.next = 4
for i in range(10):
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(payload_len))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
source_queue.put(axis_frame)
yield clk.posedge
yield clk.posedge
while xgmii_txc != 0xff or input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def bench():
# Parameters
DATA_WIDTH = 64
CTRL_WIDTH = (DATA_WIDTH / 8)
HDR_WIDTH = 2
BIT_REVERSE = 0
SCRAMBLER_DISABLE = 0
PRBS31_ENABLE = 1
TX_SERDES_PIPELINE = 2
RX_SERDES_PIPELINE = 2
SLIP_COUNT_WIDTH = 3
COUNT_125US = 1250 / 6.4
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
rx_clk = Signal(bool(0))
rx_rst = Signal(bool(0))
tx_clk = Signal(bool(0))
tx_rst = Signal(bool(0))
xgmii_txd = Signal(intbv(0)[DATA_WIDTH:])
xgmii_txc = Signal(intbv(0)[CTRL_WIDTH:])
serdes_rx_data = Signal(intbv(0)[DATA_WIDTH:])
serdes_rx_hdr = Signal(intbv(1)[HDR_WIDTH:])
tx_prbs31_enable = Signal(bool(0))
rx_prbs31_enable = Signal(bool(0))
serdes_rx_data_int = Signal(intbv(0)[DATA_WIDTH:])
serdes_rx_hdr_int = Signal(intbv(1)[HDR_WIDTH:])
# Outputs
xgmii_rxd = Signal(intbv(0)[DATA_WIDTH:])
xgmii_rxc = Signal(intbv(0)[CTRL_WIDTH:])
serdes_tx_data = Signal(intbv(0)[DATA_WIDTH:])
serdes_tx_hdr = Signal(intbv(0)[HDR_WIDTH:])
serdes_rx_bitslip = Signal(bool(0))
rx_error_count = Signal(intbv(0)[7:])
rx_bad_block = Signal(bool(0))
rx_block_lock = Signal(bool(0))
rx_high_ber = Signal(bool(0))
# sources and sinks
xgmii_source = xgmii_ep.XGMIISource()
xgmii_source_logic = xgmii_source.create_logic(tx_clk,
tx_rst,
txd=xgmii_txd,
txc=xgmii_txc,
name='xgmii_source')
xgmii_sink = xgmii_ep.XGMIISink()
xgmii_sink_logic = xgmii_sink.create_logic(rx_clk,
rx_rst,
rxd=xgmii_rxd,
rxc=xgmii_rxc,
name='xgmii_sink')
serdes_source = baser_serdes_ep.BaseRSerdesSource()
serdes_source_logic = serdes_source.create_logic(
rx_clk,
tx_data=serdes_rx_data_int,
tx_header=serdes_rx_hdr_int,
name='serdes_source')
serdes_sink = baser_serdes_ep.BaseRSerdesSink()
serdes_sink_logic = serdes_sink.create_logic(tx_clk,
rx_data=serdes_tx_data,
rx_header=serdes_tx_hdr,
name='serdes_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
rx_clk=rx_clk,
rx_rst=rx_rst,
tx_clk=tx_clk,
tx_rst=tx_rst,
xgmii_txd=xgmii_txd,
xgmii_txc=xgmii_txc,
xgmii_rxd=xgmii_rxd,
xgmii_rxc=xgmii_rxc,
serdes_tx_data=serdes_tx_data,
serdes_tx_hdr=serdes_tx_hdr,
serdes_rx_data=serdes_rx_data,
serdes_rx_hdr=serdes_rx_hdr,
serdes_rx_bitslip=serdes_rx_bitslip,
rx_error_count=rx_error_count,
rx_bad_block=rx_bad_block,
rx_block_lock=rx_block_lock,
rx_high_ber=rx_high_ber,
tx_prbs31_enable=tx_prbs31_enable,
rx_prbs31_enable=rx_prbs31_enable)
@always(delay(4))
def clkgen():
clk.next = not clk
rx_clk.next = not rx_clk
tx_clk.next = not tx_clk
load_bit_offset = []
@instance
def shift_bits():
bit_offset = 0
last_data = 0
while True:
yield clk.posedge
if load_bit_offset:
bit_offset = load_bit_offset.pop(0)
if serdes_rx_bitslip:
bit_offset += 1
bit_offset = bit_offset % 66
data = int(serdes_rx_data_int) << 2 | int(serdes_rx_hdr_int)
out_data = ((last_data | data << 66) >>
66 - bit_offset) & 0x3ffffffffffffffff
last_data = data
serdes_rx_data.next = out_data >> 2
serdes_rx_hdr.next = out_data & 3
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
tx_rst.next = 1
rx_rst.next = 1
yield clk.posedge
rst.next = 0
tx_rst.next = 0
rx_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
# wait for block lock
while not rx_block_lock:
yield clk.posedge
# dump garbage
while not xgmii_sink.empty():
xgmii_sink.recv()
yield clk.posedge
print("test 1: test RX packet")
current_test.next = 1
test_frame = bytearray(range(128))
xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame)
xgmii_source.send(xgmii_frame)
yield serdes_sink.wait()
rx_frame = serdes_sink.recv()
assert rx_frame.data == xgmii_frame.data
assert xgmii_sink.empty()
assert serdes_sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: test TX packet")
current_test.next = 2
test_frame = bytearray(range(128))
xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame)
serdes_source.send(xgmii_frame)
yield xgmii_sink.wait()
rx_frame = xgmii_sink.recv()
assert rx_frame.data == xgmii_frame.data
assert xgmii_sink.empty()
assert serdes_sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
DATA_WIDTH = 64
KEEP_WIDTH = (DATA_WIDTH / 8)
CTRL_WIDTH = (DATA_WIDTH / 8)
ENABLE_PADDING = 1
ENABLE_DIC = 1
MIN_FRAME_LENGTH = 64
PTP_PERIOD_NS = 0x6
PTP_PERIOD_FNS = 0x6666
TX_PTP_TS_ENABLE = 0
TX_PTP_TS_WIDTH = 96
TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE
TX_PTP_TAG_WIDTH = 16
RX_PTP_TS_ENABLE = 0
RX_PTP_TS_WIDTH = 96
TX_USER_WIDTH = (TX_PTP_TAG_WIDTH if TX_PTP_TAG_ENABLE else 0) + 1
RX_USER_WIDTH = (RX_PTP_TS_WIDTH if RX_PTP_TS_ENABLE else 0) + 1
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
rx_clk = Signal(bool(0))
rx_rst = Signal(bool(0))
tx_clk = Signal(bool(0))
tx_rst = Signal(bool(0))
tx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
tx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
tx_axis_tvalid = Signal(bool(0))
tx_axis_tlast = Signal(bool(0))
tx_axis_tuser = Signal(intbv(0)[TX_USER_WIDTH:])
xgmii_rxd = Signal(intbv(0x0707070707070707)[DATA_WIDTH:])
xgmii_rxc = Signal(intbv(0xff)[CTRL_WIDTH:])
tx_ptp_ts = Signal(intbv(0)[TX_PTP_TS_WIDTH:])
rx_ptp_ts = Signal(intbv(0)[RX_PTP_TS_WIDTH:])
ifg_delay = Signal(intbv(0)[8:])
# Outputs
tx_axis_tready = Signal(bool(0))
rx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
rx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
rx_axis_tvalid = Signal(bool(0))
rx_axis_tlast = Signal(bool(0))
rx_axis_tuser = Signal(intbv(0)[RX_USER_WIDTH:])
xgmii_txd = Signal(intbv(0x0707070707070707)[DATA_WIDTH:])
xgmii_txc = Signal(intbv(0xff)[CTRL_WIDTH:])
tx_axis_ptp_ts = Signal(intbv(0)[TX_PTP_TS_WIDTH:])
tx_axis_ptp_ts_tag = Signal(intbv(0)[TX_PTP_TAG_WIDTH:])
tx_axis_ptp_ts_valid = Signal(bool(0))
tx_start_packet = Signal(intbv(0)[2:])
tx_error_underflow = Signal(bool(0))
rx_start_packet = Signal(intbv(0)[2:])
rx_error_bad_frame = Signal(bool(0))
rx_error_bad_fcs = Signal(bool(0))
# sources and sinks
axis_source_pause = Signal(bool(0))
xgmii_source = xgmii_ep.XGMIISource()
xgmii_source_logic = xgmii_source.create_logic(clk,
rst,
txd=xgmii_rxd,
txc=xgmii_rxc,
name='xgmii_source')
xgmii_sink = xgmii_ep.XGMIISink()
xgmii_sink_logic = xgmii_sink.create_logic(clk,
rst,
rxd=xgmii_txd,
rxc=xgmii_txc,
name='xgmii_sink')
axis_source = axis_ep.AXIStreamSource()
axis_source_logic = axis_source.create_logic(clk,
rst,
tdata=tx_axis_tdata,
tkeep=tx_axis_tkeep,
tvalid=tx_axis_tvalid,
tready=tx_axis_tready,
tlast=tx_axis_tlast,
tuser=tx_axis_tuser,
pause=axis_source_pause,
name='axis_source')
axis_sink = axis_ep.AXIStreamSink()
axis_sink_logic = axis_sink.create_logic(clk,
rst,
tdata=rx_axis_tdata,
tkeep=rx_axis_tkeep,
tvalid=rx_axis_tvalid,
tlast=rx_axis_tlast,
tuser=rx_axis_tuser,
name='axis_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
rx_clk=rx_clk,
rx_rst=rx_rst,
tx_clk=tx_clk,
tx_rst=tx_rst,
tx_axis_tdata=tx_axis_tdata,
tx_axis_tkeep=tx_axis_tkeep,
tx_axis_tvalid=tx_axis_tvalid,
tx_axis_tready=tx_axis_tready,
tx_axis_tlast=tx_axis_tlast,
tx_axis_tuser=tx_axis_tuser,
rx_axis_tdata=rx_axis_tdata,
rx_axis_tkeep=rx_axis_tkeep,
rx_axis_tvalid=rx_axis_tvalid,
rx_axis_tlast=rx_axis_tlast,
rx_axis_tuser=rx_axis_tuser,
xgmii_rxd=xgmii_rxd,
xgmii_rxc=xgmii_rxc,
xgmii_txd=xgmii_txd,
xgmii_txc=xgmii_txc,
tx_ptp_ts=tx_ptp_ts,
rx_ptp_ts=rx_ptp_ts,
tx_axis_ptp_ts=tx_axis_ptp_ts,
tx_axis_ptp_ts_tag=tx_axis_ptp_ts_tag,
tx_axis_ptp_ts_valid=tx_axis_ptp_ts_valid,
tx_start_packet=tx_start_packet,
tx_error_underflow=tx_error_underflow,
rx_start_packet=rx_start_packet,
rx_error_bad_frame=rx_error_bad_frame,
rx_error_bad_fcs=rx_error_bad_fcs,
ifg_delay=ifg_delay)
@always(delay(4))
def clkgen():
clk.next = not clk
tx_clk.next = not tx_clk
rx_clk.next = not rx_clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
tx_rst.next = 1
rx_rst.next = 1
yield clk.posedge
rst.next = 0
tx_rst.next = 0
rx_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
yield clk.posedge
print("test 1: test rx packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
xgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
bytearray(axis_frame))
yield axis_sink.wait()
rx_frame = axis_sink.recv()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: test tx packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
axis_source.send(axis_frame)
yield xgmii_sink.wait()
rx_frame = xgmii_sink.recv()
assert rx_frame.data[0:8] == bytearray(
b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == 46
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
DATA_WIDTH = 32
CTRL_WIDTH = (DATA_WIDTH / 8)
AXIS_DATA_WIDTH = DATA_WIDTH
AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH > 8)
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH / 8)
ENABLE_PADDING = 1
ENABLE_DIC = 1
MIN_FRAME_LENGTH = 64
TX_FIFO_DEPTH = 4096
TX_FIFO_PIPELINE_OUTPUT = 2
TX_FRAME_FIFO = 1
TX_DROP_BAD_FRAME = TX_FRAME_FIFO
TX_DROP_WHEN_FULL = 0
RX_FIFO_DEPTH = 4096
RX_FIFO_PIPELINE_OUTPUT = 2
RX_FRAME_FIFO = 1
RX_DROP_BAD_FRAME = RX_FRAME_FIFO
RX_DROP_WHEN_FULL = RX_FRAME_FIFO
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
rx_clk = Signal(bool(0))
rx_rst = Signal(bool(0))
tx_clk = Signal(bool(0))
tx_rst = Signal(bool(0))
logic_clk = Signal(bool(0))
logic_rst = Signal(bool(0))
tx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
tx_axis_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:])
tx_axis_tvalid = Signal(bool(0))
tx_axis_tlast = Signal(bool(0))
tx_axis_tuser = Signal(bool(0))
rx_axis_tready = Signal(bool(0))
xgmii_rxd = Signal(intbv(0x0707070707070707)[DATA_WIDTH:])
xgmii_rxc = Signal(intbv(0xff)[CTRL_WIDTH:])
ifg_delay = Signal(intbv(0)[8:])
# Outputs
tx_axis_tready = Signal(bool(0))
rx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
rx_axis_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:])
rx_axis_tvalid = Signal(bool(0))
rx_axis_tlast = Signal(bool(0))
rx_axis_tuser = Signal(bool(0))
xgmii_txd = Signal(intbv(0x0707070707070707)[DATA_WIDTH:])
xgmii_txc = Signal(intbv(0xff)[CTRL_WIDTH:])
tx_error_underflow = Signal(bool(0))
tx_fifo_overflow = Signal(bool(0))
tx_fifo_bad_frame = Signal(bool(0))
tx_fifo_good_frame = Signal(bool(0))
rx_error_bad_frame = Signal(bool(0))
rx_error_bad_fcs = Signal(bool(0))
rx_fifo_overflow = Signal(bool(0))
rx_fifo_bad_frame = Signal(bool(0))
rx_fifo_good_frame = Signal(bool(0))
# sources and sinks
axis_source_pause = Signal(bool(0))
axis_sink_pause = Signal(bool(0))
xgmii_source = xgmii_ep.XGMIISource()
xgmii_source_logic = xgmii_source.create_logic(rx_clk,
rx_rst,
txd=xgmii_rxd,
txc=xgmii_rxc,
name='xgmii_source')
xgmii_sink = xgmii_ep.XGMIISink()
xgmii_sink_logic = xgmii_sink.create_logic(tx_clk,
tx_rst,
rxd=xgmii_txd,
rxc=xgmii_txc,
name='xgmii_sink')
axis_source = axis_ep.AXIStreamSource()
axis_source_logic = axis_source.create_logic(logic_clk,
logic_rst,
tdata=tx_axis_tdata,
tkeep=tx_axis_tkeep,
tvalid=tx_axis_tvalid,
tready=tx_axis_tready,
tlast=tx_axis_tlast,
tuser=tx_axis_tuser,
pause=axis_source_pause,
name='axis_source')
axis_sink = axis_ep.AXIStreamSink()
axis_sink_logic = axis_sink.create_logic(logic_clk,
logic_rst,
tdata=rx_axis_tdata,
tkeep=rx_axis_tkeep,
tvalid=rx_axis_tvalid,
tready=rx_axis_tready,
tlast=rx_axis_tlast,
tuser=rx_axis_tuser,
pause=axis_sink_pause,
name='axis_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
rx_clk=rx_clk,
rx_rst=rx_rst,
tx_clk=tx_clk,
tx_rst=tx_rst,
logic_clk=logic_clk,
logic_rst=logic_rst,
tx_axis_tdata=tx_axis_tdata,
tx_axis_tkeep=tx_axis_tkeep,
tx_axis_tvalid=tx_axis_tvalid,
tx_axis_tready=tx_axis_tready,
tx_axis_tlast=tx_axis_tlast,
tx_axis_tuser=tx_axis_tuser,
rx_axis_tdata=rx_axis_tdata,
rx_axis_tkeep=rx_axis_tkeep,
rx_axis_tvalid=rx_axis_tvalid,
rx_axis_tready=rx_axis_tready,
rx_axis_tlast=rx_axis_tlast,
rx_axis_tuser=rx_axis_tuser,
xgmii_rxd=xgmii_rxd,
xgmii_rxc=xgmii_rxc,
xgmii_txd=xgmii_txd,
xgmii_txc=xgmii_txc,
tx_error_underflow=tx_error_underflow,
tx_fifo_overflow=tx_fifo_overflow,
tx_fifo_bad_frame=tx_fifo_bad_frame,
tx_fifo_good_frame=tx_fifo_good_frame,
rx_error_bad_frame=rx_error_bad_frame,
rx_error_bad_fcs=rx_error_bad_fcs,
rx_fifo_overflow=rx_fifo_overflow,
rx_fifo_bad_frame=rx_fifo_bad_frame,
rx_fifo_good_frame=rx_fifo_good_frame,
ifg_delay=ifg_delay)
@always(delay(4))
def clkgen():
clk.next = not clk
tx_clk.next = not tx_clk
rx_clk.next = not rx_clk
logic_clk.next = not logic_clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
tx_rst.next = 1
rx_rst.next = 1
logic_rst.next = 1
yield clk.posedge
rst.next = 0
tx_rst.next = 0
rx_rst.next = 0
logic_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
yield clk.posedge
print("test 1: test rx packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
xgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
bytearray(axis_frame))
yield axis_sink.wait()
rx_frame = axis_sink.recv()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: test tx packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
axis_source.send(axis_frame)
yield xgmii_sink.wait()
rx_frame = xgmii_sink.recv()
assert rx_frame.data[0:8] == bytearray(
b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == 46
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
sw = Signal(intbv(0)[2:])
jp = Signal(intbv(0)[4:])
uart_suspend = Signal(bool(0))
uart_dtr = Signal(bool(0))
uart_txd = Signal(bool(0))
uart_rts = Signal(bool(0))
amh_right_mdio_i = Signal(bool(0))
amh_left_mdio_i = Signal(bool(0))
eth_r0_rxd = Signal(intbv(0)[64:])
eth_r0_rxc = Signal(intbv(0)[8:])
eth_r1_rxd = Signal(intbv(0)[64:])
eth_r1_rxc = Signal(intbv(0)[8:])
eth_r2_rxd = Signal(intbv(0)[64:])
eth_r2_rxc = Signal(intbv(0)[8:])
eth_r3_rxd = Signal(intbv(0)[64:])
eth_r3_rxc = Signal(intbv(0)[8:])
eth_r4_rxd = Signal(intbv(0)[64:])
eth_r4_rxc = Signal(intbv(0)[8:])
eth_r5_rxd = Signal(intbv(0)[64:])
eth_r5_rxc = Signal(intbv(0)[8:])
eth_r6_rxd = Signal(intbv(0)[64:])
eth_r6_rxc = Signal(intbv(0)[8:])
eth_r7_rxd = Signal(intbv(0)[64:])
eth_r7_rxc = Signal(intbv(0)[8:])
eth_r8_rxd = Signal(intbv(0)[64:])
eth_r8_rxc = Signal(intbv(0)[8:])
eth_r9_rxd = Signal(intbv(0)[64:])
eth_r9_rxc = Signal(intbv(0)[8:])
eth_r10_rxd = Signal(intbv(0)[64:])
eth_r10_rxc = Signal(intbv(0)[8:])
eth_r11_rxd = Signal(intbv(0)[64:])
eth_r11_rxc = Signal(intbv(0)[8:])
eth_l0_rxd = Signal(intbv(0)[64:])
eth_l0_rxc = Signal(intbv(0)[8:])
eth_l1_rxd = Signal(intbv(0)[64:])
eth_l1_rxc = Signal(intbv(0)[8:])
eth_l2_rxd = Signal(intbv(0)[64:])
eth_l2_rxc = Signal(intbv(0)[8:])
eth_l3_rxd = Signal(intbv(0)[64:])
eth_l3_rxc = Signal(intbv(0)[8:])
eth_l4_rxd = Signal(intbv(0)[64:])
eth_l4_rxc = Signal(intbv(0)[8:])
eth_l5_rxd = Signal(intbv(0)[64:])
eth_l5_rxc = Signal(intbv(0)[8:])
eth_l6_rxd = Signal(intbv(0)[64:])
eth_l6_rxc = Signal(intbv(0)[8:])
eth_l7_rxd = Signal(intbv(0)[64:])
eth_l7_rxc = Signal(intbv(0)[8:])
eth_l8_rxd = Signal(intbv(0)[64:])
eth_l8_rxc = Signal(intbv(0)[8:])
eth_l9_rxd = Signal(intbv(0)[64:])
eth_l9_rxc = Signal(intbv(0)[8:])
eth_l10_rxd = Signal(intbv(0)[64:])
eth_l10_rxc = Signal(intbv(0)[8:])
eth_l11_rxd = Signal(intbv(0)[64:])
eth_l11_rxc = Signal(intbv(0)[8:])
# Outputs
led = Signal(intbv(0)[4:])
uart_rst = Signal(bool(0))
uart_ri = Signal(bool(0))
uart_dcd = Signal(bool(0))
uart_dsr = Signal(bool(0))
uart_rxd = Signal(bool(1))
uart_cts = Signal(bool(0))
amh_right_mdc = Signal(bool(1))
amh_right_mdio_o = Signal(bool(1))
amh_right_mdio_t = Signal(bool(1))
amh_left_mdc = Signal(bool(1))
amh_left_mdio_o = Signal(bool(1))
amh_left_mdio_t = Signal(bool(1))
eth_r0_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r0_txc = Signal(intbv(0xff)[8:])
eth_r1_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r1_txc = Signal(intbv(0xff)[8:])
eth_r2_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r2_txc = Signal(intbv(0xff)[8:])
eth_r3_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r3_txc = Signal(intbv(0xff)[8:])
eth_r4_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r4_txc = Signal(intbv(0xff)[8:])
eth_r5_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r5_txc = Signal(intbv(0xff)[8:])
eth_r6_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r6_txc = Signal(intbv(0xff)[8:])
eth_r7_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r7_txc = Signal(intbv(0xff)[8:])
eth_r8_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r8_txc = Signal(intbv(0xff)[8:])
eth_r9_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r9_txc = Signal(intbv(0xff)[8:])
eth_r10_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r10_txc = Signal(intbv(0xff)[8:])
eth_r11_txd = Signal(intbv(0x0707070707070707)[64:])
eth_r11_txc = Signal(intbv(0xff)[8:])
eth_l0_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l0_txc = Signal(intbv(0xff)[8:])
eth_l1_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l1_txc = Signal(intbv(0xff)[8:])
eth_l2_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l2_txc = Signal(intbv(0xff)[8:])
eth_l3_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l3_txc = Signal(intbv(0xff)[8:])
eth_l4_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l4_txc = Signal(intbv(0xff)[8:])
eth_l5_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l5_txc = Signal(intbv(0xff)[8:])
eth_l6_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l6_txc = Signal(intbv(0xff)[8:])
eth_l7_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l7_txc = Signal(intbv(0xff)[8:])
eth_l8_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l8_txc = Signal(intbv(0xff)[8:])
eth_l9_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l9_txc = Signal(intbv(0xff)[8:])
eth_l10_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l10_txc = Signal(intbv(0xff)[8:])
eth_l11_txd = Signal(intbv(0x0707070707070707)[64:])
eth_l11_txc = Signal(intbv(0xff)[8:])
# sources and sinks
eth_r0_source = xgmii_ep.XGMIISource()
eth_r0_source_logic = eth_r0_source.create_logic(clk,
rst,
txd=eth_r0_rxd,
txc=eth_r0_rxc,
name='eth_r0_source')
eth_r0_sink = xgmii_ep.XGMIISink()
eth_r0_sink_logic = eth_r0_sink.create_logic(clk,
rst,
rxd=eth_r0_txd,
rxc=eth_r0_txc,
name='eth_r0_sink')
eth_r1_source = xgmii_ep.XGMIISource()
eth_r1_source_logic = eth_r1_source.create_logic(clk,
rst,
txd=eth_r1_rxd,
txc=eth_r1_rxc,
name='eth_r1_source')
eth_r1_sink = xgmii_ep.XGMIISink()
eth_r1_sink_logic = eth_r1_sink.create_logic(clk,
rst,
rxd=eth_r1_txd,
rxc=eth_r1_txc,
name='eth_r1_sink')
eth_r2_source = xgmii_ep.XGMIISource()
eth_r2_source_logic = eth_r2_source.create_logic(clk,
rst,
txd=eth_r2_rxd,
txc=eth_r2_rxc,
name='eth_r2_source')
eth_r2_sink = xgmii_ep.XGMIISink()
eth_r2_sink_logic = eth_r2_sink.create_logic(clk,
rst,
rxd=eth_r2_txd,
rxc=eth_r2_txc,
name='eth_r2_sink')
eth_r3_source = xgmii_ep.XGMIISource()
eth_r3_source_logic = eth_r3_source.create_logic(clk,
rst,
txd=eth_r3_rxd,
txc=eth_r3_rxc,
name='eth_r3_source')
eth_r3_sink = xgmii_ep.XGMIISink()
eth_r3_sink_logic = eth_r3_sink.create_logic(clk,
rst,
rxd=eth_r3_txd,
rxc=eth_r3_txc,
name='eth_r3_sink')
eth_r4_source = xgmii_ep.XGMIISource()
eth_r4_source_logic = eth_r4_source.create_logic(clk,
rst,
txd=eth_r4_rxd,
txc=eth_r4_rxc,
name='eth_r4_source')
eth_r4_sink = xgmii_ep.XGMIISink()
eth_r4_sink_logic = eth_r4_sink.create_logic(clk,
rst,
rxd=eth_r4_txd,
rxc=eth_r4_txc,
name='eth_r4_sink')
eth_r5_source = xgmii_ep.XGMIISource()
eth_r5_source_logic = eth_r5_source.create_logic(clk,
rst,
txd=eth_r5_rxd,
txc=eth_r5_rxc,
name='eth_r5_source')
eth_r5_sink = xgmii_ep.XGMIISink()
eth_r5_sink_logic = eth_r5_sink.create_logic(clk,
rst,
rxd=eth_r5_txd,
rxc=eth_r5_txc,
name='eth_r5_sink')
eth_r6_source = xgmii_ep.XGMIISource()
eth_r6_source_logic = eth_r6_source.create_logic(clk,
rst,
txd=eth_r6_rxd,
txc=eth_r6_rxc,
name='eth_r6_source')
eth_r6_sink = xgmii_ep.XGMIISink()
eth_r6_sink_logic = eth_r6_sink.create_logic(clk,
rst,
rxd=eth_r6_txd,
rxc=eth_r6_txc,
name='eth_r6_sink')
eth_r7_source = xgmii_ep.XGMIISource()
eth_r7_source_logic = eth_r7_source.create_logic(clk,
rst,
txd=eth_r7_rxd,
txc=eth_r7_rxc,
name='eth_r7_source')
eth_r7_sink = xgmii_ep.XGMIISink()
eth_r7_sink_logic = eth_r7_sink.create_logic(clk,
rst,
rxd=eth_r7_txd,
rxc=eth_r7_txc,
name='eth_r7_sink')
eth_r8_source = xgmii_ep.XGMIISource()
eth_r8_source_logic = eth_r8_source.create_logic(clk,
rst,
txd=eth_r8_rxd,
txc=eth_r8_rxc,
name='eth_r8_source')
eth_r8_sink = xgmii_ep.XGMIISink()
eth_r8_sink_logic = eth_r8_sink.create_logic(clk,
rst,
rxd=eth_r8_txd,
rxc=eth_r8_txc,
name='eth_r8_sink')
eth_r9_source = xgmii_ep.XGMIISource()
eth_r9_source_logic = eth_r9_source.create_logic(clk,
rst,
txd=eth_r9_rxd,
txc=eth_r9_rxc,
name='eth_r9_source')
eth_r9_sink = xgmii_ep.XGMIISink()
eth_r9_sink_logic = eth_r9_sink.create_logic(clk,
rst,
rxd=eth_r9_txd,
rxc=eth_r9_txc,
name='eth_r9_sink')
eth_r10_source = xgmii_ep.XGMIISource()
eth_r10_source_logic = eth_r10_source.create_logic(clk,
rst,
txd=eth_r10_rxd,
txc=eth_r10_rxc,
name='eth_r10_source')
eth_r10_sink = xgmii_ep.XGMIISink()
eth_r10_sink_logic = eth_r10_sink.create_logic(clk,
rst,
rxd=eth_r10_txd,
rxc=eth_r10_txc,
name='eth_r10_sink')
eth_r11_source = xgmii_ep.XGMIISource()
eth_r11_source_logic = eth_r11_source.create_logic(clk,
rst,
txd=eth_r11_rxd,
txc=eth_r11_rxc,
name='eth_r11_source')
eth_r11_sink = xgmii_ep.XGMIISink()
eth_r11_sink_logic = eth_r11_sink.create_logic(clk,
rst,
rxd=eth_r11_txd,
rxc=eth_r11_txc,
name='eth_r11_sink')
eth_l0_source = xgmii_ep.XGMIISource()
eth_l0_source_logic = eth_l0_source.create_logic(clk,
rst,
txd=eth_l0_rxd,
txc=eth_l0_rxc,
name='eth_l0_source')
eth_l0_sink = xgmii_ep.XGMIISink()
eth_l0_sink_logic = eth_l0_sink.create_logic(clk,
rst,
rxd=eth_l0_txd,
rxc=eth_l0_txc,
name='eth_l0_sink')
eth_l1_source = xgmii_ep.XGMIISource()
eth_l1_source_logic = eth_l1_source.create_logic(clk,
rst,
txd=eth_l1_rxd,
txc=eth_l1_rxc,
name='eth_l1_source')
eth_l1_sink = xgmii_ep.XGMIISink()
eth_l1_sink_logic = eth_l1_sink.create_logic(clk,
rst,
rxd=eth_l1_txd,
rxc=eth_l1_txc,
name='eth_l1_sink')
eth_l2_source = xgmii_ep.XGMIISource()
eth_l2_source_logic = eth_l2_source.create_logic(clk,
rst,
txd=eth_l2_rxd,
txc=eth_l2_rxc,
name='eth_l2_source')
eth_l2_sink = xgmii_ep.XGMIISink()
eth_l2_sink_logic = eth_l2_sink.create_logic(clk,
rst,
rxd=eth_l2_txd,
rxc=eth_l2_txc,
name='eth_l2_sink')
eth_l3_source = xgmii_ep.XGMIISource()
eth_l3_source_logic = eth_l3_source.create_logic(clk,
rst,
txd=eth_l3_rxd,
txc=eth_l3_rxc,
name='eth_l3_source')
eth_l3_sink = xgmii_ep.XGMIISink()
eth_l3_sink_logic = eth_l3_sink.create_logic(clk,
rst,
rxd=eth_l3_txd,
rxc=eth_l3_txc,
name='eth_l3_sink')
eth_l4_source = xgmii_ep.XGMIISource()
eth_l4_source_logic = eth_l4_source.create_logic(clk,
rst,
txd=eth_l4_rxd,
txc=eth_l4_rxc,
name='eth_l4_source')
eth_l4_sink = xgmii_ep.XGMIISink()
eth_l4_sink_logic = eth_l4_sink.create_logic(clk,
rst,
rxd=eth_l4_txd,
rxc=eth_l4_txc,
name='eth_l4_sink')
eth_l5_source = xgmii_ep.XGMIISource()
eth_l5_source_logic = eth_l5_source.create_logic(clk,
rst,
txd=eth_l5_rxd,
txc=eth_l5_rxc,
name='eth_l5_source')
eth_l5_sink = xgmii_ep.XGMIISink()
eth_l5_sink_logic = eth_l5_sink.create_logic(clk,
rst,
rxd=eth_l5_txd,
rxc=eth_l5_txc,
name='eth_l5_sink')
eth_l6_source = xgmii_ep.XGMIISource()
eth_l6_source_logic = eth_l6_source.create_logic(clk,
rst,
txd=eth_l6_rxd,
txc=eth_l6_rxc,
name='eth_l6_source')
eth_l6_sink = xgmii_ep.XGMIISink()
eth_l6_sink_logic = eth_l6_sink.create_logic(clk,
rst,
rxd=eth_l6_txd,
rxc=eth_l6_txc,
name='eth_l6_sink')
eth_l7_source = xgmii_ep.XGMIISource()
eth_l7_source_logic = eth_l7_source.create_logic(clk,
rst,
txd=eth_l7_rxd,
txc=eth_l7_rxc,
name='eth_l7_source')
eth_l7_sink = xgmii_ep.XGMIISink()
eth_l7_sink_logic = eth_l7_sink.create_logic(clk,
rst,
rxd=eth_l7_txd,
rxc=eth_l7_txc,
name='eth_l7_sink')
eth_l8_source = xgmii_ep.XGMIISource()
eth_l8_source_logic = eth_l8_source.create_logic(clk,
rst,
txd=eth_l8_rxd,
txc=eth_l8_rxc,
name='eth_l8_source')
eth_l8_sink = xgmii_ep.XGMIISink()
eth_l8_sink_logic = eth_l8_sink.create_logic(clk,
rst,
rxd=eth_l8_txd,
rxc=eth_l8_txc,
name='eth_l8_sink')
eth_l9_source = xgmii_ep.XGMIISource()
eth_l9_source_logic = eth_l9_source.create_logic(clk,
rst,
txd=eth_l9_rxd,
txc=eth_l9_rxc,
name='eth_l9_source')
eth_l9_sink = xgmii_ep.XGMIISink()
eth_l9_sink_logic = eth_l9_sink.create_logic(clk,
rst,
rxd=eth_l9_txd,
rxc=eth_l9_txc,
name='eth_l9_sink')
eth_l10_source = xgmii_ep.XGMIISource()
eth_l10_source_logic = eth_l10_source.create_logic(clk,
rst,
txd=eth_l10_rxd,
txc=eth_l10_rxc,
name='eth_l10_source')
eth_l10_sink = xgmii_ep.XGMIISink()
eth_l10_sink_logic = eth_l10_sink.create_logic(clk,
rst,
rxd=eth_l10_txd,
rxc=eth_l10_txc,
name='eth_l10_sink')
eth_l11_source = xgmii_ep.XGMIISource()
eth_l11_source_logic = eth_l11_source.create_logic(clk,
rst,
txd=eth_l11_rxd,
txc=eth_l11_rxc,
name='eth_l11_source')
eth_l11_sink = xgmii_ep.XGMIISink()
eth_l11_sink_logic = eth_l11_sink.create_logic(clk,
rst,
rxd=eth_l11_txd,
rxc=eth_l11_txc,
name='eth_l11_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
sw=sw,
jp=jp,
led=led,
uart_rst=uart_rst,
uart_suspend=uart_suspend,
uart_ri=uart_ri,
uart_dcd=uart_dcd,
uart_dtr=uart_dtr,
uart_dsr=uart_dsr,
uart_txd=uart_txd,
uart_rxd=uart_rxd,
uart_rts=uart_rts,
uart_cts=uart_cts,
amh_right_mdc=amh_right_mdc,
amh_right_mdio_i=amh_right_mdio_i,
amh_right_mdio_o=amh_right_mdio_o,
amh_right_mdio_t=amh_right_mdio_t,
amh_left_mdc=amh_left_mdc,
amh_left_mdio_i=amh_left_mdio_i,
amh_left_mdio_o=amh_left_mdio_o,
amh_left_mdio_t=amh_left_mdio_t,
eth_r0_txd=eth_r0_txd,
eth_r0_txc=eth_r0_txc,
eth_r0_rxd=eth_r0_rxd,
eth_r0_rxc=eth_r0_rxc,
eth_r1_txd=eth_r1_txd,
eth_r1_txc=eth_r1_txc,
eth_r1_rxd=eth_r1_rxd,
eth_r1_rxc=eth_r1_rxc,
eth_r2_txd=eth_r2_txd,
eth_r2_txc=eth_r2_txc,
eth_r2_rxd=eth_r2_rxd,
eth_r2_rxc=eth_r2_rxc,
eth_r3_txd=eth_r3_txd,
eth_r3_txc=eth_r3_txc,
eth_r3_rxd=eth_r3_rxd,
eth_r3_rxc=eth_r3_rxc,
eth_r4_txd=eth_r4_txd,
eth_r4_txc=eth_r4_txc,
eth_r4_rxd=eth_r4_rxd,
eth_r4_rxc=eth_r4_rxc,
eth_r5_txd=eth_r5_txd,
eth_r5_txc=eth_r5_txc,
eth_r5_rxd=eth_r5_rxd,
eth_r5_rxc=eth_r5_rxc,
eth_r6_txd=eth_r6_txd,
eth_r6_txc=eth_r6_txc,
eth_r6_rxd=eth_r6_rxd,
eth_r6_rxc=eth_r6_rxc,
eth_r7_txd=eth_r7_txd,
eth_r7_txc=eth_r7_txc,
eth_r7_rxd=eth_r7_rxd,
eth_r7_rxc=eth_r7_rxc,
eth_r8_txd=eth_r8_txd,
eth_r8_txc=eth_r8_txc,
eth_r8_rxd=eth_r8_rxd,
eth_r8_rxc=eth_r8_rxc,
eth_r9_txd=eth_r9_txd,
eth_r9_txc=eth_r9_txc,
eth_r9_rxd=eth_r9_rxd,
eth_r9_rxc=eth_r9_rxc,
eth_r10_txd=eth_r10_txd,
eth_r10_txc=eth_r10_txc,
eth_r10_rxd=eth_r10_rxd,
eth_r10_rxc=eth_r10_rxc,
eth_r11_txd=eth_r11_txd,
eth_r11_txc=eth_r11_txc,
eth_r11_rxd=eth_r11_rxd,
eth_r11_rxc=eth_r11_rxc,
eth_l0_txd=eth_l0_txd,
eth_l0_txc=eth_l0_txc,
eth_l0_rxd=eth_l0_rxd,
eth_l0_rxc=eth_l0_rxc,
eth_l1_txd=eth_l1_txd,
eth_l1_txc=eth_l1_txc,
eth_l1_rxd=eth_l1_rxd,
eth_l1_rxc=eth_l1_rxc,
eth_l2_txd=eth_l2_txd,
eth_l2_txc=eth_l2_txc,
eth_l2_rxd=eth_l2_rxd,
eth_l2_rxc=eth_l2_rxc,
eth_l3_txd=eth_l3_txd,
eth_l3_txc=eth_l3_txc,
eth_l3_rxd=eth_l3_rxd,
eth_l3_rxc=eth_l3_rxc,
eth_l4_txd=eth_l4_txd,
eth_l4_txc=eth_l4_txc,
eth_l4_rxd=eth_l4_rxd,
eth_l4_rxc=eth_l4_rxc,
eth_l5_txd=eth_l5_txd,
eth_l5_txc=eth_l5_txc,
eth_l5_rxd=eth_l5_rxd,
eth_l5_rxc=eth_l5_rxc,
eth_l6_txd=eth_l6_txd,
eth_l6_txc=eth_l6_txc,
eth_l6_rxd=eth_l6_rxd,
eth_l6_rxc=eth_l6_rxc,
eth_l7_txd=eth_l7_txd,
eth_l7_txc=eth_l7_txc,
eth_l7_rxd=eth_l7_rxd,
eth_l7_rxc=eth_l7_rxc,
eth_l8_txd=eth_l8_txd,
eth_l8_txc=eth_l8_txc,
eth_l8_rxd=eth_l8_rxd,
eth_l8_rxc=eth_l8_rxc,
eth_l9_txd=eth_l9_txd,
eth_l9_txc=eth_l9_txc,
eth_l9_rxd=eth_l9_rxd,
eth_l9_rxc=eth_l9_rxc,
eth_l10_txd=eth_l10_txd,
eth_l10_txc=eth_l10_txc,
eth_l10_rxd=eth_l10_rxd,
eth_l10_rxc=eth_l10_rxc,
eth_l11_txd=eth_l11_txd,
eth_l11_txc=eth_l11_txc,
eth_l11_rxd=eth_l11_rxd,
eth_l11_rxc=eth_l11_rxc)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test UDP RX packet")
current_test.next = 1
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 5678
test_frame.udp_dest_port = 1234
test_frame.payload = bytearray(range(32))
test_frame.build()
eth_l0_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame.build_eth().build_axis_fcs().data)
# wait for ARP request packet
while eth_l0_sink.empty():
yield clk.posedge
rx_frame = eth_l0_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 1
assert check_frame.arp_sha == 0x020000000000
assert check_frame.arp_spa == 0xc0a80180
assert check_frame.arp_tha == 0x000000000000
assert check_frame.arp_tpa == 0xc0a80181
# generate response
arp_frame = arp_ep.ARPFrame()
arp_frame.eth_dest_mac = 0x020000000000
arp_frame.eth_src_mac = 0xDAD1D2D3D4D5
arp_frame.eth_type = 0x0806
arp_frame.arp_htype = 0x0001
arp_frame.arp_ptype = 0x0800
arp_frame.arp_hlen = 6
arp_frame.arp_plen = 4
arp_frame.arp_oper = 2
arp_frame.arp_sha = 0xDAD1D2D3D4D5
arp_frame.arp_spa = 0xc0a80181
arp_frame.arp_tha = 0x020000000000
arp_frame.arp_tpa = 0xc0a80180
eth_l0_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
arp_frame.build_eth().build_axis_fcs().data)
while eth_l0_sink.empty():
yield clk.posedge
rx_frame = eth_l0_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 1234
assert check_frame.udp_dest_port == 5678
assert check_frame.payload.data == bytearray(range(32))
assert eth_l0_source.empty()
assert eth_l0_sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
AXIS_PCIE_DATA_WIDTH = 512
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32)
AXIS_PCIE_RC_USER_WIDTH = 161
AXIS_PCIE_RQ_USER_WIDTH = 137
AXIS_PCIE_CQ_USER_WIDTH = 183
AXIS_PCIE_CC_USER_WIDTH = 81
RQ_SEQ_NUM_WIDTH = 6
BAR0_APERTURE = 24
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
m_axis_rq_tready = Signal(bool(0))
s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_rc_tlast = Signal(bool(0))
s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:])
s_axis_rc_tvalid = Signal(bool(0))
s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_cq_tlast = Signal(bool(0))
s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:])
s_axis_cq_tvalid = Signal(bool(0))
m_axis_cc_tready = Signal(bool(0))
s_axis_rq_seq_num_0 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
s_axis_rq_seq_num_valid_0 = Signal(bool(0))
s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
s_axis_rq_seq_num_valid_1 = Signal(bool(0))
pcie_tfc_nph_av = Signal(intbv(15)[4:])
pcie_tfc_npd_av = Signal(intbv(15)[4:])
cfg_max_payload = Signal(intbv(0)[2:])
cfg_max_read_req = Signal(intbv(0)[3:])
cfg_mgmt_read_data = Signal(intbv(0)[32:])
cfg_mgmt_read_write_done = Signal(bool(0))
cfg_fc_ph = Signal(intbv(0)[8:])
cfg_fc_pd = Signal(intbv(0)[12:])
cfg_fc_nph = Signal(intbv(0)[8:])
cfg_fc_npd = Signal(intbv(0)[12:])
cfg_fc_cplh = Signal(intbv(0)[8:])
cfg_fc_cpld = Signal(intbv(0)[12:])
cfg_interrupt_msi_enable = Signal(intbv(0)[4:])
cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:])
cfg_interrupt_msi_mask_update = Signal(bool(0))
cfg_interrupt_msi_data = Signal(intbv(0)[32:])
cfg_interrupt_msi_sent = Signal(bool(0))
cfg_interrupt_msi_fail = Signal(bool(0))
qsfp0_tx_clk_1 = Signal(bool(0))
qsfp0_tx_rst_1 = Signal(bool(0))
qsfp0_rx_clk_1 = Signal(bool(0))
qsfp0_rx_rst_1 = Signal(bool(0))
qsfp0_rxd_1 = Signal(intbv(0)[64:])
qsfp0_rxc_1 = Signal(intbv(0)[8:])
qsfp0_tx_clk_2 = Signal(bool(0))
qsfp0_tx_rst_2 = Signal(bool(0))
qsfp0_rx_clk_2 = Signal(bool(0))
qsfp0_rx_rst_2 = Signal(bool(0))
qsfp0_rxd_2 = Signal(intbv(0)[64:])
qsfp0_rxc_2 = Signal(intbv(0)[8:])
qsfp0_tx_clk_3 = Signal(bool(0))
qsfp0_tx_rst_3 = Signal(bool(0))
qsfp0_rx_clk_3 = Signal(bool(0))
qsfp0_rx_rst_3 = Signal(bool(0))
qsfp0_rxd_3 = Signal(intbv(0)[64:])
qsfp0_rxc_3 = Signal(intbv(0)[8:])
qsfp0_tx_clk_4 = Signal(bool(0))
qsfp0_tx_rst_4 = Signal(bool(0))
qsfp0_rx_clk_4 = Signal(bool(0))
qsfp0_rx_rst_4 = Signal(bool(0))
qsfp0_rxd_4 = Signal(intbv(0)[64:])
qsfp0_rxc_4 = Signal(intbv(0)[8:])
qsfp1_tx_clk_1 = Signal(bool(0))
qsfp1_tx_rst_1 = Signal(bool(0))
qsfp1_rx_clk_1 = Signal(bool(0))
qsfp1_rx_rst_1 = Signal(bool(0))
qsfp1_rxd_1 = Signal(intbv(0)[64:])
qsfp1_rxc_1 = Signal(intbv(0)[8:])
qsfp1_tx_clk_2 = Signal(bool(0))
qsfp1_tx_rst_2 = Signal(bool(0))
qsfp1_rx_clk_2 = Signal(bool(0))
qsfp1_rx_rst_2 = Signal(bool(0))
qsfp1_rxd_2 = Signal(intbv(0)[64:])
qsfp1_rxc_2 = Signal(intbv(0)[8:])
qsfp1_tx_clk_3 = Signal(bool(0))
qsfp1_tx_rst_3 = Signal(bool(0))
qsfp1_rx_clk_3 = Signal(bool(0))
qsfp1_rx_rst_3 = Signal(bool(0))
qsfp1_rxd_3 = Signal(intbv(0)[64:])
qsfp1_rxc_3 = Signal(intbv(0)[8:])
qsfp1_tx_clk_4 = Signal(bool(0))
qsfp1_tx_rst_4 = Signal(bool(0))
qsfp1_rx_clk_4 = Signal(bool(0))
qsfp1_rx_rst_4 = Signal(bool(0))
qsfp1_rxd_4 = Signal(intbv(0)[64:])
qsfp1_rxc_4 = Signal(intbv(0)[8:])
# Outputs
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_rq_tlast = Signal(bool(0))
m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
m_axis_rq_tvalid = Signal(bool(0))
s_axis_rc_tready = Signal(bool(0))
s_axis_cq_tready = Signal(bool(0))
m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_cc_tlast = Signal(bool(0))
m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:])
m_axis_cc_tvalid = Signal(bool(0))
status_error_cor = Signal(bool(0))
status_error_uncor = Signal(bool(0))
cfg_mgmt_addr = Signal(intbv(0)[10:])
cfg_mgmt_function_number = Signal(intbv(0)[8:])
cfg_mgmt_write = Signal(bool(0))
cfg_mgmt_write_data = Signal(intbv(0)[32:])
cfg_mgmt_byte_enable = Signal(intbv(0)[4:])
cfg_mgmt_read = Signal(bool(0))
cfg_fc_sel = Signal(intbv(4)[3:])
cfg_interrupt_msi_int = Signal(intbv(0)[32:])
cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:])
cfg_interrupt_msi_select = Signal(intbv(0)[2:])
cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[2:])
cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0))
cfg_interrupt_msi_attr = Signal(intbv(0)[3:])
cfg_interrupt_msi_tph_present = Signal(bool(0))
cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:])
cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[8:])
cfg_interrupt_msi_function_number = Signal(intbv(0)[8:])
qsfp0_txd_1 = Signal(intbv(0)[64:])
qsfp0_txc_1 = Signal(intbv(0)[8:])
qsfp0_txd_2 = Signal(intbv(0)[64:])
qsfp0_txc_2 = Signal(intbv(0)[8:])
qsfp0_txd_3 = Signal(intbv(0)[64:])
qsfp0_txc_3 = Signal(intbv(0)[8:])
qsfp0_txd_4 = Signal(intbv(0)[64:])
qsfp0_txc_4 = Signal(intbv(0)[8:])
qsfp1_txd_1 = Signal(intbv(0)[64:])
qsfp1_txc_1 = Signal(intbv(0)[8:])
qsfp1_txd_2 = Signal(intbv(0)[64:])
qsfp1_txc_2 = Signal(intbv(0)[8:])
qsfp1_txd_3 = Signal(intbv(0)[64:])
qsfp1_txc_3 = Signal(intbv(0)[8:])
qsfp1_txd_4 = Signal(intbv(0)[64:])
qsfp1_txc_4 = Signal(intbv(0)[8:])
# sources and sinks
qsfp0_1_source = xgmii_ep.XGMIISource()
qsfp0_1_source_logic = qsfp0_1_source.create_logic(qsfp0_rx_clk_1,
qsfp0_rx_rst_1,
txd=qsfp0_rxd_1,
txc=qsfp0_rxc_1,
name='qsfp0_1_source')
qsfp0_1_sink = xgmii_ep.XGMIISink()
qsfp0_1_sink_logic = qsfp0_1_sink.create_logic(qsfp0_tx_clk_1,
qsfp0_tx_rst_1,
rxd=qsfp0_txd_1,
rxc=qsfp0_txc_1,
name='qsfp0_1_sink')
qsfp0_2_source = xgmii_ep.XGMIISource()
qsfp0_2_source_logic = qsfp0_2_source.create_logic(qsfp0_rx_clk_2,
qsfp0_rx_rst_2,
txd=qsfp0_rxd_2,
txc=qsfp0_rxc_2,
name='qsfp0_2_source')
qsfp0_2_sink = xgmii_ep.XGMIISink()
qsfp0_2_sink_logic = qsfp0_2_sink.create_logic(qsfp0_tx_clk_2,
qsfp0_tx_rst_2,
rxd=qsfp0_txd_2,
rxc=qsfp0_txc_2,
name='qsfp0_2_sink')
qsfp0_3_source = xgmii_ep.XGMIISource()
qsfp0_3_source_logic = qsfp0_3_source.create_logic(qsfp0_rx_clk_3,
qsfp0_rx_rst_3,
txd=qsfp0_rxd_3,
txc=qsfp0_rxc_3,
name='qsfp0_3_source')
qsfp0_3_sink = xgmii_ep.XGMIISink()
qsfp0_3_sink_logic = qsfp0_3_sink.create_logic(qsfp0_tx_clk_3,
qsfp0_tx_rst_3,
rxd=qsfp0_txd_3,
rxc=qsfp0_txc_3,
name='qsfp0_3_sink')
qsfp0_4_source = xgmii_ep.XGMIISource()
qsfp0_4_source_logic = qsfp0_4_source.create_logic(qsfp0_rx_clk_4,
qsfp0_rx_rst_4,
txd=qsfp0_rxd_4,
txc=qsfp0_rxc_4,
name='qsfp0_4_source')
qsfp0_4_sink = xgmii_ep.XGMIISink()
qsfp0_4_sink_logic = qsfp0_4_sink.create_logic(qsfp0_tx_clk_4,
qsfp0_tx_rst_4,
rxd=qsfp0_txd_4,
rxc=qsfp0_txc_4,
name='qsfp0_4_sink')
qsfp1_1_source = xgmii_ep.XGMIISource()
qsfp1_1_source_logic = qsfp1_1_source.create_logic(qsfp1_rx_clk_1,
qsfp1_rx_rst_1,
txd=qsfp1_rxd_1,
txc=qsfp1_rxc_1,
name='qsfp1_1_source')
qsfp1_1_sink = xgmii_ep.XGMIISink()
qsfp1_1_sink_logic = qsfp1_1_sink.create_logic(qsfp1_tx_clk_1,
qsfp1_tx_rst_1,
rxd=qsfp1_txd_1,
rxc=qsfp1_txc_1,
name='qsfp1_1_sink')
qsfp1_2_source = xgmii_ep.XGMIISource()
qsfp1_2_source_logic = qsfp1_2_source.create_logic(qsfp1_rx_clk_2,
qsfp1_rx_rst_2,
txd=qsfp1_rxd_2,
txc=qsfp1_rxc_2,
name='qsfp1_2_source')
qsfp1_2_sink = xgmii_ep.XGMIISink()
qsfp1_2_sink_logic = qsfp1_2_sink.create_logic(qsfp1_tx_clk_2,
qsfp1_tx_rst_2,
rxd=qsfp1_txd_2,
rxc=qsfp1_txc_2,
name='qsfp1_2_sink')
qsfp1_3_source = xgmii_ep.XGMIISource()
qsfp1_3_source_logic = qsfp1_3_source.create_logic(qsfp1_rx_clk_3,
qsfp1_rx_rst_3,
txd=qsfp1_rxd_3,
txc=qsfp1_rxc_3,
name='qsfp1_3_source')
qsfp1_3_sink = xgmii_ep.XGMIISink()
qsfp1_3_sink_logic = qsfp1_3_sink.create_logic(qsfp1_tx_clk_3,
qsfp1_tx_rst_3,
rxd=qsfp1_txd_3,
rxc=qsfp1_txc_3,
name='qsfp1_3_sink')
qsfp1_4_source = xgmii_ep.XGMIISource()
qsfp1_4_source_logic = qsfp1_4_source.create_logic(qsfp1_rx_clk_4,
qsfp1_rx_rst_4,
txd=qsfp1_rxd_4,
txc=qsfp1_rxc_4,
name='qsfp1_4_source')
qsfp1_4_sink = xgmii_ep.XGMIISink()
qsfp1_4_sink_logic = qsfp1_4_sink.create_logic(qsfp1_tx_clk_4,
qsfp1_tx_rst_4,
rxd=qsfp1_txd_4,
rxc=qsfp1_txc_4,
name='qsfp1_4_sink')
# Clock and Reset Interface
user_clk = Signal(bool(0))
user_reset = Signal(bool(0))
sys_clk = Signal(bool(0))
sys_reset = Signal(bool(0))
# PCIe devices
rc = pcie.RootComplex()
rc.max_payload_size = 0x1 # 256 bytes
rc.max_read_request_size = 0x5 # 4096 bytes
driver = mqnic.Driver(rc)
dev = pcie_usp.UltrascalePlusPCIe()
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5
dev.functions[0].configure_bar(0,
2**BAR0_APERTURE,
ext=True,
prefetch=True)
rc.make_port().connect(dev)
cq_pause = Signal(bool(0))
cc_pause = Signal(bool(0))
rq_pause = Signal(bool(0))
rc_pause = Signal(bool(0))
pcie_logic = dev.create_logic(
# Completer reQuest Interface
m_axis_cq_tdata=s_axis_cq_tdata,
m_axis_cq_tuser=s_axis_cq_tuser,
m_axis_cq_tlast=s_axis_cq_tlast,
m_axis_cq_tkeep=s_axis_cq_tkeep,
m_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cq_tready=s_axis_cq_tready,
#pcie_cq_np_req=pcie_cq_np_req,
pcie_cq_np_req=Signal(intbv(3)[2:]),
#pcie_cq_np_req_count=pcie_cq_np_req_count,
# Completer Completion Interface
s_axis_cc_tdata=m_axis_cc_tdata,
s_axis_cc_tuser=m_axis_cc_tuser,
s_axis_cc_tlast=m_axis_cc_tlast,
s_axis_cc_tkeep=m_axis_cc_tkeep,
s_axis_cc_tvalid=m_axis_cc_tvalid,
s_axis_cc_tready=m_axis_cc_tready,
# Requester reQuest Interface
s_axis_rq_tdata=m_axis_rq_tdata,
s_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_tlast=m_axis_rq_tlast,
s_axis_rq_tkeep=m_axis_rq_tkeep,
s_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rq_tready=m_axis_rq_tready,
pcie_rq_seq_num0=s_axis_rq_seq_num_0,
pcie_rq_seq_num_vld0=s_axis_rq_seq_num_valid_0,
pcie_rq_seq_num1=s_axis_rq_seq_num_1,
pcie_rq_seq_num_vld1=s_axis_rq_seq_num_valid_1,
#pcie_rq_tag0=pcie_rq_tag0,
#pcie_rq_tag1=pcie_rq_tag1,
#pcie_rq_tag_av=pcie_rq_tag_av,
#pcie_rq_tag_vld0=pcie_rq_tag_vld0,
#pcie_rq_tag_vld1=pcie_rq_tag_vld1,
# Requester Completion Interface
m_axis_rc_tdata=s_axis_rc_tdata,
m_axis_rc_tuser=s_axis_rc_tuser,
m_axis_rc_tlast=s_axis_rc_tlast,
m_axis_rc_tkeep=s_axis_rc_tkeep,
m_axis_rc_tvalid=s_axis_rc_tvalid,
m_axis_rc_tready=s_axis_rc_tready,
# Transmit Flow Control Interface
#pcie_tfc_nph_av=pcie_tfc_nph_av,
#pcie_tfc_npd_av=pcie_tfc_npd_av,
# Configuration Management Interface
cfg_mgmt_addr=cfg_mgmt_addr,
cfg_mgmt_function_number=cfg_mgmt_function_number,
cfg_mgmt_write=cfg_mgmt_write,
cfg_mgmt_write_data=cfg_mgmt_write_data,
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
cfg_mgmt_read=cfg_mgmt_read,
cfg_mgmt_read_data=cfg_mgmt_read_data,
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
#cfg_mgmt_debug_access=cfg_mgmt_debug_access,
# Configuration Status Interface
#cfg_phy_link_down=cfg_phy_link_down,
#cfg_phy_link_status=cfg_phy_link_status,
#cfg_negotiated_width=cfg_negotiated_width,
#cfg_current_speed=cfg_current_speed,
cfg_max_payload=cfg_max_payload,
cfg_max_read_req=cfg_max_read_req,
#cfg_function_status=cfg_function_status,
#cfg_vf_status=cfg_vf_status,
#cfg_function_power_state=cfg_function_power_state,
#cfg_vf_power_state=cfg_vf_power_state,
#cfg_link_power_state=cfg_link_power_state,
#cfg_err_cor_out=cfg_err_cor_out,
#cfg_err_nonfatal_out=cfg_err_nonfatal_out,
#cfg_err_fatal_out=cfg_err_fatal_out,
#cfg_local_err_out=cfg_local_err_out,
#cfg_local_err_valid=cfg_local_err_valid,
#cfg_rx_pm_state=cfg_rx_pm_state,
#cfg_tx_pm_state=cfg_tx_pm_state,
#cfg_ltssm_state=cfg_ltssm_state,
#cfg_rcb_status=cfg_rcb_status,
#cfg_obff_enable=cfg_obff_enable,
#cfg_pl_status_change=cfg_pl_status_change,
#cfg_tph_requester_enable=cfg_tph_requester_enable,
#cfg_tph_st_mode=cfg_tph_st_mode,
#cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable,
#cfg_vf_tph_st_mode=cfg_vf_tph_st_mode,
# Configuration Received Message Interface
#cfg_msg_received=cfg_msg_received,
#cfg_msg_received_data=cfg_msg_received_data,
#cfg_msg_received_type=cfg_msg_received_type,
# Configuration Transmit Message Interface
#cfg_msg_transmit=cfg_msg_transmit,
#cfg_msg_transmit_type=cfg_msg_transmit_type,
#cfg_msg_transmit_data=cfg_msg_transmit_data,
#cfg_msg_transmit_done=cfg_msg_transmit_done,
# Configuration Flow Control Interface
cfg_fc_ph=cfg_fc_ph,
cfg_fc_pd=cfg_fc_pd,
cfg_fc_nph=cfg_fc_nph,
cfg_fc_npd=cfg_fc_npd,
cfg_fc_cplh=cfg_fc_cplh,
cfg_fc_cpld=cfg_fc_cpld,
cfg_fc_sel=cfg_fc_sel,
# Configuration Control Interface
#cfg_hot_reset_in=cfg_hot_reset_in,
#cfg_hot_reset_out=cfg_hot_reset_out,
#cfg_config_space_enable=cfg_config_space_enable,
#cfg_dsn=cfg_dsn,
#cfg_ds_port_number=cfg_ds_port_number,
#cfg_ds_bus_number=cfg_ds_bus_number,
#cfg_ds_device_number=cfg_ds_device_number,
#cfg_ds_function_number=cfg_ds_function_number,
#cfg_power_state_change_ack=cfg_power_state_change_ack,
#cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
cfg_err_cor_in=status_error_cor,
cfg_err_uncor_in=status_error_uncor,
#cfg_flr_done=cfg_flr_done,
#cfg_vf_flr_done=cfg_vf_flr_done,
#cfg_flr_in_process=cfg_flr_in_process,
#cfg_vf_flr_in_process=cfg_vf_flr_in_process,
#cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
#cfg_link_training_enable=cfg_link_training_enable,
# Configuration Interrupt Controller Interface
#cfg_interrupt_int=cfg_interrupt_int,
#cfg_interrupt_sent=cfg_interrupt_sent,
#cfg_interrupt_pending=cfg_interrupt_pending,
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_pending_status_data_enable=
cfg_interrupt_msi_pending_status_data_enable,
cfg_interrupt_msi_pending_status_function_num=
cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
#cfg_interrupt_msix_enable=cfg_interrupt_msix_enable,
#cfg_interrupt_msix_mask=cfg_interrupt_msix_mask,
#cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable,
#cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask,
#cfg_interrupt_msix_address=cfg_interrupt_msix_address,
#cfg_interrupt_msix_data=cfg_interrupt_msix_data,
#cfg_interrupt_msix_int=cfg_interrupt_msix_int,
#cfg_interrupt_msix_vec_pending=cfg_interrupt_msix_vec_pending,
#cfg_interrupt_msix_vec_pending_status=cfg_interrupt_msix_vec_pending_status,
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
# Configuration Extend Interface
#cfg_ext_read_received=cfg_ext_read_received,
#cfg_ext_write_received=cfg_ext_write_received,
#cfg_ext_register_number=cfg_ext_register_number,
#cfg_ext_function_number=cfg_ext_function_number,
#cfg_ext_write_data=cfg_ext_write_data,
#cfg_ext_write_byte_enable=cfg_ext_write_byte_enable,
#cfg_ext_read_data=cfg_ext_read_data,
#cfg_ext_read_data_valid=cfg_ext_read_data_valid,
# Clock and Reset Interface
user_clk=user_clk,
user_reset=user_reset,
sys_clk=sys_clk,
sys_clk_gt=sys_clk,
sys_reset=sys_reset,
#phy_rdy_out=phy_rdy_out,
cq_pause=cq_pause,
cc_pause=cc_pause,
rq_pause=rq_pause,
rc_pause=rc_pause)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tlast=m_axis_rq_tlast,
m_axis_rq_tready=m_axis_rq_tready,
m_axis_rq_tuser=m_axis_rq_tuser,
m_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rc_tdata=s_axis_rc_tdata,
s_axis_rc_tkeep=s_axis_rc_tkeep,
s_axis_rc_tlast=s_axis_rc_tlast,
s_axis_rc_tready=s_axis_rc_tready,
s_axis_rc_tuser=s_axis_rc_tuser,
s_axis_rc_tvalid=s_axis_rc_tvalid,
s_axis_cq_tdata=s_axis_cq_tdata,
s_axis_cq_tkeep=s_axis_cq_tkeep,
s_axis_cq_tlast=s_axis_cq_tlast,
s_axis_cq_tready=s_axis_cq_tready,
s_axis_cq_tuser=s_axis_cq_tuser,
s_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cc_tdata=m_axis_cc_tdata,
m_axis_cc_tkeep=m_axis_cc_tkeep,
m_axis_cc_tlast=m_axis_cc_tlast,
m_axis_cc_tready=m_axis_cc_tready,
m_axis_cc_tuser=m_axis_cc_tuser,
m_axis_cc_tvalid=m_axis_cc_tvalid,
s_axis_rq_seq_num_0=s_axis_rq_seq_num_0,
s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0,
s_axis_rq_seq_num_1=s_axis_rq_seq_num_1,
s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1,
pcie_tfc_nph_av=pcie_tfc_nph_av,
pcie_tfc_npd_av=pcie_tfc_npd_av,
cfg_max_payload=cfg_max_payload,
cfg_max_read_req=cfg_max_read_req,
cfg_mgmt_addr=cfg_mgmt_addr,
cfg_mgmt_function_number=cfg_mgmt_function_number,
cfg_mgmt_write=cfg_mgmt_write,
cfg_mgmt_write_data=cfg_mgmt_write_data,
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
cfg_mgmt_read=cfg_mgmt_read,
cfg_mgmt_read_data=cfg_mgmt_read_data,
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
cfg_fc_ph=cfg_fc_ph,
cfg_fc_pd=cfg_fc_pd,
cfg_fc_nph=cfg_fc_nph,
cfg_fc_npd=cfg_fc_npd,
cfg_fc_cplh=cfg_fc_cplh,
cfg_fc_cpld=cfg_fc_cpld,
cfg_fc_sel=cfg_fc_sel,
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
cfg_interrupt_msi_pending_status_function_num=
cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_pending_status_data_enable=
cfg_interrupt_msi_pending_status_data_enable,
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
status_error_cor=status_error_cor,
status_error_uncor=status_error_uncor,
qsfp0_tx_clk_1=qsfp0_tx_clk_1,
qsfp0_tx_rst_1=qsfp0_tx_rst_1,
qsfp0_txd_1=qsfp0_txd_1,
qsfp0_txc_1=qsfp0_txc_1,
qsfp0_rx_clk_1=qsfp0_rx_clk_1,
qsfp0_rx_rst_1=qsfp0_rx_rst_1,
qsfp0_rxd_1=qsfp0_rxd_1,
qsfp0_rxc_1=qsfp0_rxc_1,
qsfp0_tx_clk_2=qsfp0_tx_clk_2,
qsfp0_tx_rst_2=qsfp0_tx_rst_2,
qsfp0_txd_2=qsfp0_txd_2,
qsfp0_txc_2=qsfp0_txc_2,
qsfp0_rx_clk_2=qsfp0_rx_clk_2,
qsfp0_rx_rst_2=qsfp0_rx_rst_2,
qsfp0_rxd_2=qsfp0_rxd_2,
qsfp0_rxc_2=qsfp0_rxc_2,
qsfp0_tx_clk_3=qsfp0_tx_clk_3,
qsfp0_tx_rst_3=qsfp0_tx_rst_3,
qsfp0_txd_3=qsfp0_txd_3,
qsfp0_txc_3=qsfp0_txc_3,
qsfp0_rx_clk_3=qsfp0_rx_clk_3,
qsfp0_rx_rst_3=qsfp0_rx_rst_3,
qsfp0_rxd_3=qsfp0_rxd_3,
qsfp0_rxc_3=qsfp0_rxc_3,
qsfp0_tx_clk_4=qsfp0_tx_clk_4,
qsfp0_tx_rst_4=qsfp0_tx_rst_4,
qsfp0_txd_4=qsfp0_txd_4,
qsfp0_txc_4=qsfp0_txc_4,
qsfp0_rx_clk_4=qsfp0_rx_clk_4,
qsfp0_rx_rst_4=qsfp0_rx_rst_4,
qsfp0_rxd_4=qsfp0_rxd_4,
qsfp0_rxc_4=qsfp0_rxc_4,
qsfp1_tx_clk_1=qsfp1_tx_clk_1,
qsfp1_tx_rst_1=qsfp1_tx_rst_1,
qsfp1_txd_1=qsfp1_txd_1,
qsfp1_txc_1=qsfp1_txc_1,
qsfp1_rx_clk_1=qsfp1_rx_clk_1,
qsfp1_rx_rst_1=qsfp1_rx_rst_1,
qsfp1_rxd_1=qsfp1_rxd_1,
qsfp1_rxc_1=qsfp1_rxc_1,
qsfp1_tx_clk_2=qsfp1_tx_clk_2,
qsfp1_tx_rst_2=qsfp1_tx_rst_2,
qsfp1_txd_2=qsfp1_txd_2,
qsfp1_txc_2=qsfp1_txc_2,
qsfp1_rx_clk_2=qsfp1_rx_clk_2,
qsfp1_rx_rst_2=qsfp1_rx_rst_2,
qsfp1_rxd_2=qsfp1_rxd_2,
qsfp1_rxc_2=qsfp1_rxc_2,
qsfp1_tx_clk_3=qsfp1_tx_clk_3,
qsfp1_tx_rst_3=qsfp1_tx_rst_3,
qsfp1_txd_3=qsfp1_txd_3,
qsfp1_txc_3=qsfp1_txc_3,
qsfp1_rx_clk_3=qsfp1_rx_clk_3,
qsfp1_rx_rst_3=qsfp1_rx_rst_3,
qsfp1_rxd_3=qsfp1_rxd_3,
qsfp1_rxc_3=qsfp1_rxc_3,
qsfp1_tx_clk_4=qsfp1_tx_clk_4,
qsfp1_tx_rst_4=qsfp1_tx_rst_4,
qsfp1_txd_4=qsfp1_txd_4,
qsfp1_txc_4=qsfp1_txc_4,
qsfp1_rx_clk_4=qsfp1_rx_clk_4,
qsfp1_rx_rst_4=qsfp1_rx_rst_4,
qsfp1_rxd_4=qsfp1_rxd_4,
qsfp1_rxc_4=qsfp1_rxc_4)
@always(delay(5))
def clkgen():
clk.next = not clk
@always(delay(3))
def qsfp_clkgen():
qsfp0_tx_clk_1.next = not qsfp0_tx_clk_1
qsfp0_rx_clk_1.next = not qsfp0_rx_clk_1
qsfp0_tx_clk_2.next = not qsfp0_tx_clk_2
qsfp0_rx_clk_2.next = not qsfp0_rx_clk_2
qsfp0_tx_clk_3.next = not qsfp0_tx_clk_3
qsfp0_rx_clk_3.next = not qsfp0_rx_clk_3
qsfp0_tx_clk_4.next = not qsfp0_tx_clk_4
qsfp0_rx_clk_4.next = not qsfp0_rx_clk_4
qsfp1_tx_clk_1.next = not qsfp1_tx_clk_1
qsfp1_rx_clk_1.next = not qsfp1_rx_clk_1
qsfp1_tx_clk_2.next = not qsfp1_tx_clk_2
qsfp1_rx_clk_2.next = not qsfp1_rx_clk_2
qsfp1_tx_clk_3.next = not qsfp1_tx_clk_3
qsfp1_rx_clk_3.next = not qsfp1_rx_clk_3
qsfp1_tx_clk_4.next = not qsfp1_tx_clk_4
qsfp1_rx_clk_4.next = not qsfp1_rx_clk_4
@always_comb
def clk_logic():
sys_clk.next = clk
sys_reset.next = not rst
loopback_enable = Signal(bool(0))
@instance
def loopback():
while True:
yield clk.posedge
if loopback_enable:
if not qsfp0_1_sink.empty():
pkt = qsfp0_1_sink.recv()
qsfp0_1_source.send(pkt)
if not qsfp0_2_sink.empty():
pkt = qsfp0_2_sink.recv()
qsfp0_2_source.send(pkt)
if not qsfp0_3_sink.empty():
pkt = qsfp0_3_sink.recv()
qsfp0_3_source.send(pkt)
if not qsfp0_4_sink.empty():
pkt = qsfp0_4_sink.recv()
qsfp0_4_source.send(pkt)
if not qsfp1_1_sink.empty():
pkt = qsfp1_1_sink.recv()
qsfp1_1_source.send(pkt)
if not qsfp1_2_sink.empty():
pkt = qsfp1_2_sink.recv()
qsfp1_2_source.send(pkt)
if not qsfp1_3_sink.empty():
pkt = qsfp1_3_sink.recv()
qsfp1_3_source.send(pkt)
if not qsfp1_4_sink.empty():
pkt = qsfp1_4_sink.recv()
qsfp1_4_source.send(pkt)
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
qsfp0_tx_rst_1.next = 1
qsfp0_rx_rst_1.next = 1
qsfp0_tx_rst_2.next = 1
qsfp0_rx_rst_2.next = 1
qsfp0_tx_rst_3.next = 1
qsfp0_rx_rst_3.next = 1
qsfp0_tx_rst_4.next = 1
qsfp0_rx_rst_4.next = 1
qsfp1_tx_rst_1.next = 1
qsfp1_rx_rst_1.next = 1
qsfp1_tx_rst_2.next = 1
qsfp1_rx_rst_2.next = 1
qsfp1_tx_rst_3.next = 1
qsfp1_rx_rst_3.next = 1
qsfp1_tx_rst_4.next = 1
qsfp1_rx_rst_4.next = 1
yield clk.posedge
yield delay(100)
rst.next = 0
qsfp0_tx_rst_1.next = 0
qsfp0_rx_rst_1.next = 0
qsfp0_tx_rst_2.next = 0
qsfp0_rx_rst_2.next = 0
qsfp0_tx_rst_3.next = 0
qsfp0_rx_rst_3.next = 0
qsfp0_tx_rst_4.next = 0
qsfp0_rx_rst_4.next = 0
qsfp1_tx_rst_1.next = 0
qsfp1_rx_rst_1.next = 0
qsfp1_tx_rst_2.next = 0
qsfp1_rx_rst_2.next = 0
qsfp1_tx_rst_3.next = 0
qsfp1_rx_rst_3.next = 0
qsfp1_tx_rst_4.next = 0
qsfp1_rx_rst_4.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
current_tag = 1
yield clk.posedge
print("test 1: enumeration")
current_test.next = 1
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()
# enable queues
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].hw_addr +
mqnic.MQNIC_PORT_REG_SCHED_ENABLE, 0x00000001)
for k in range(driver.interfaces[0].tx_queue_count):
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 4 * k,
0x00000003)
yield from rc.mem_read(driver.hw_addr,
4) # wait for all writes to complete
yield delay(100)
yield clk.posedge
print("test 3: send and receive a packet")
current_test.next = 3
# test bad packet
#qsfp0_1_source.send(b'\x55\x55\x55\x55\x55\xd5'+bytearray(range(128)))
data = bytearray([x % 256 for x in range(1024)])
yield from driver.interfaces[0].start_xmit(data, 0)
yield qsfp0_1_sink.wait()
pkt = qsfp0_1_sink.recv()
print(pkt)
qsfp0_1_source.send(pkt)
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert frame_checksum(pkt.data) == pkt.rx_checksum
# yield from driver.interfaces[1].start_xmit(data, 0)
# yield qsfp0_1_sink.wait()
# pkt = qsfp0_1_sink.recv()
# print(pkt)
# qsfp0_1_source.send(pkt)
# yield driver.interfaces[1].wait()
# pkt = driver.interfaces[1].recv()
# print(pkt)
# assert frame_checksum(pkt.data) == pkt.rx_checksum
yield delay(100)
yield clk.posedge
print("test 4: checksum tests")
current_test.next = 4
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80164
test_frame.ip_dest_ip = 0xc0a80165
test_frame.udp_source_port = 1
test_frame.udp_dest_port = 2
test_frame.udp_length = None
test_frame.udp_checksum = None
test_frame.payload = bytearray((x % 256 for x in range(256)))
test_frame.set_udp_pseudo_header_checksum()
axis_frame = test_frame.build_axis()
yield from driver.interfaces[0].start_xmit(axis_frame.data, 0, 34, 6)
yield qsfp0_1_sink.wait()
pkt = qsfp0_1_sink.recv()
print(pkt)
qsfp0_1_source.send(pkt)
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.rx_checksum == frame_checksum(pkt.data)
check_frame = udp_ep.UDPFrame()
check_frame.parse_axis(pkt.data)
assert check_frame.verify_checksums()
yield delay(100)
yield clk.posedge
print("test 5: multiple small packets")
current_test.next = 5
count = 64
pkts = [
bytearray([(x + k) % 256 for x in range(64)]) for k in range(count)
]
loopback_enable.next = True
for p in pkts:
yield from driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.data == pkts[k]
assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(100)
yield clk.posedge
print("test 6: multiple large packets")
current_test.next = 6
count = 64
pkts = [
bytearray([(x + k) % 256 for x in range(1514)])
for k in range(count)
]
loopback_enable.next = True
for p in pkts:
yield from driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.data == pkts[k]
assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
clk_156mhz = Signal(bool(0))
rst_156mhz = Signal(bool(0))
clk_250mhz = Signal(bool(0))
rst_250mhz = Signal(bool(0))
user_sw = Signal(intbv(0)[2:])
m_axis_rq_tready = Signal(bool(0))
s_axis_rc_tdata = Signal(intbv(0)[256:])
s_axis_rc_tkeep = Signal(intbv(0)[8:])
s_axis_rc_tlast = Signal(bool(0))
s_axis_rc_tuser = Signal(intbv(0)[75:])
s_axis_rc_tvalid = Signal(bool(0))
s_axis_cq_tdata = Signal(intbv(0)[256:])
s_axis_cq_tkeep = Signal(intbv(0)[8:])
s_axis_cq_tlast = Signal(bool(0))
s_axis_cq_tuser = Signal(intbv(0)[88:])
s_axis_cq_tvalid = Signal(bool(0))
m_axis_cc_tready = Signal(bool(0))
pcie_tfc_nph_av = Signal(intbv(15)[4:])
pcie_tfc_npd_av = Signal(intbv(15)[4:])
cfg_max_payload = Signal(intbv(0)[2:])
cfg_max_read_req = Signal(intbv(0)[3:])
cfg_mgmt_read_data = Signal(intbv(0)[32:])
cfg_mgmt_read_write_done = Signal(bool(0))
cfg_interrupt_msi_enable = Signal(intbv(0)[4:])
cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:])
cfg_interrupt_msi_mask_update = Signal(bool(0))
cfg_interrupt_msi_data = Signal(intbv(0)[32:])
cfg_interrupt_msi_sent = Signal(bool(0))
cfg_interrupt_msi_fail = Signal(bool(0))
qsfp_0_tx_clk_0 = Signal(bool(0))
qsfp_0_tx_rst_0 = Signal(bool(0))
qsfp_0_rx_clk_0 = Signal(bool(0))
qsfp_0_rx_rst_0 = Signal(bool(0))
qsfp_0_rxd_0 = Signal(intbv(0)[64:])
qsfp_0_rxc_0 = Signal(intbv(0)[8:])
qsfp_0_tx_clk_1 = Signal(bool(0))
qsfp_0_tx_rst_1 = Signal(bool(0))
qsfp_0_rx_clk_1 = Signal(bool(0))
qsfp_0_rx_rst_1 = Signal(bool(0))
qsfp_0_rxd_1 = Signal(intbv(0)[64:])
qsfp_0_rxc_1 = Signal(intbv(0)[8:])
qsfp_0_tx_clk_2 = Signal(bool(0))
qsfp_0_tx_rst_2 = Signal(bool(0))
qsfp_0_rx_clk_2 = Signal(bool(0))
qsfp_0_rx_rst_2 = Signal(bool(0))
qsfp_0_rxd_2 = Signal(intbv(0)[64:])
qsfp_0_rxc_2 = Signal(intbv(0)[8:])
qsfp_0_tx_clk_3 = Signal(bool(0))
qsfp_0_tx_rst_3 = Signal(bool(0))
qsfp_0_rx_clk_3 = Signal(bool(0))
qsfp_0_rx_rst_3 = Signal(bool(0))
qsfp_0_rxd_3 = Signal(intbv(0)[64:])
qsfp_0_rxc_3 = Signal(intbv(0)[8:])
qsfp_0_modprs_l = Signal(bool(0))
qsfp_1_tx_clk_0 = Signal(bool(0))
qsfp_1_tx_rst_0 = Signal(bool(0))
qsfp_1_rx_clk_0 = Signal(bool(0))
qsfp_1_rx_rst_0 = Signal(bool(0))
qsfp_1_rxd_0 = Signal(intbv(0)[64:])
qsfp_1_rxc_0 = Signal(intbv(0)[8:])
qsfp_1_tx_clk_1 = Signal(bool(0))
qsfp_1_tx_rst_1 = Signal(bool(0))
qsfp_1_rx_clk_1 = Signal(bool(0))
qsfp_1_rx_rst_1 = Signal(bool(0))
qsfp_1_rxd_1 = Signal(intbv(0)[64:])
qsfp_1_rxc_1 = Signal(intbv(0)[8:])
qsfp_1_tx_clk_2 = Signal(bool(0))
qsfp_1_tx_rst_2 = Signal(bool(0))
qsfp_1_rx_clk_2 = Signal(bool(0))
qsfp_1_rx_rst_2 = Signal(bool(0))
qsfp_1_rxd_2 = Signal(intbv(0)[64:])
qsfp_1_rxc_2 = Signal(intbv(0)[8:])
qsfp_1_tx_clk_3 = Signal(bool(0))
qsfp_1_tx_rst_3 = Signal(bool(0))
qsfp_1_rx_clk_3 = Signal(bool(0))
qsfp_1_rx_rst_3 = Signal(bool(0))
qsfp_1_rxd_3 = Signal(intbv(0)[64:])
qsfp_1_rxc_3 = Signal(intbv(0)[8:])
qsfp_1_modprs_l = Signal(bool(0))
qsfp_int_l = Signal(bool(0))
qsfp_i2c_scl_i = Signal(bool(1))
qsfp_i2c_sda_i = Signal(bool(1))
eeprom_i2c_scl_i = Signal(bool(1))
eeprom_i2c_sda_i = Signal(bool(1))
# Outputs
user_led_g = Signal(intbv(0)[2:])
user_led_r = Signal(bool(0))
front_led = Signal(intbv(0)[2:])
m_axis_rq_tdata = Signal(intbv(0)[256:])
m_axis_rq_tkeep = Signal(intbv(0)[8:])
m_axis_rq_tlast = Signal(bool(0))
m_axis_rq_tuser = Signal(intbv(0)[62:])
m_axis_rq_tvalid = Signal(bool(0))
s_axis_rc_tready = Signal(bool(0))
s_axis_cq_tready = Signal(bool(0))
m_axis_cc_tdata = Signal(intbv(0)[256:])
m_axis_cc_tkeep = Signal(intbv(0)[8:])
m_axis_cc_tlast = Signal(bool(0))
m_axis_cc_tuser = Signal(intbv(0)[33:])
m_axis_cc_tvalid = Signal(bool(0))
status_error_cor = Signal(bool(0))
status_error_uncor = Signal(bool(0))
cfg_mgmt_addr = Signal(intbv(0)[10:])
cfg_mgmt_function_number = Signal(intbv(0)[8:])
cfg_mgmt_write = Signal(bool(0))
cfg_mgmt_write_data = Signal(intbv(0)[32:])
cfg_mgmt_byte_enable = Signal(intbv(0)[4:])
cfg_mgmt_read = Signal(bool(0))
cfg_interrupt_msi_int = Signal(intbv(0)[32:])
cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:])
cfg_interrupt_msi_select = Signal(intbv(0)[2:])
cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[2:])
cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0))
cfg_interrupt_msi_attr = Signal(intbv(0)[3:])
cfg_interrupt_msi_tph_present = Signal(bool(0))
cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:])
cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[8:])
cfg_interrupt_msi_function_number = Signal(intbv(0)[8:])
qsfp_0_txd_0 = Signal(intbv(0)[64:])
qsfp_0_txc_0 = Signal(intbv(0)[8:])
qsfp_0_txd_1 = Signal(intbv(0)[64:])
qsfp_0_txc_1 = Signal(intbv(0)[8:])
qsfp_0_txd_2 = Signal(intbv(0)[64:])
qsfp_0_txc_2 = Signal(intbv(0)[8:])
qsfp_0_txd_3 = Signal(intbv(0)[64:])
qsfp_0_txc_3 = Signal(intbv(0)[8:])
qsfp_0_sel_l = Signal(bool(1))
qsfp_1_txd_0 = Signal(intbv(0)[64:])
qsfp_1_txc_0 = Signal(intbv(0)[8:])
qsfp_1_txd_1 = Signal(intbv(0)[64:])
qsfp_1_txc_1 = Signal(intbv(0)[8:])
qsfp_1_txd_2 = Signal(intbv(0)[64:])
qsfp_1_txc_2 = Signal(intbv(0)[8:])
qsfp_1_txd_3 = Signal(intbv(0)[64:])
qsfp_1_txc_3 = Signal(intbv(0)[8:])
qsfp_1_sel_l = Signal(bool(1))
qsfp_reset_l = Signal(bool(1))
qsfp_i2c_scl_o = Signal(bool(1))
qsfp_i2c_scl_t = Signal(bool(1))
qsfp_i2c_sda_o = Signal(bool(1))
qsfp_i2c_sda_t = Signal(bool(1))
eeprom_i2c_scl_o = Signal(bool(1))
eeprom_i2c_scl_t = Signal(bool(1))
eeprom_i2c_sda_o = Signal(bool(1))
eeprom_i2c_sda_t = Signal(bool(1))
eeprom_wp = Signal(bool(1))
# sources and sinks
qsfp_0_0_source = xgmii_ep.XGMIISource()
qsfp_0_0_source_logic = qsfp_0_0_source.create_logic(
qsfp_0_rx_clk_0,
qsfp_0_rx_rst_0,
txd=qsfp_0_rxd_0,
txc=qsfp_0_rxc_0,
name='qsfp_0_0_source')
qsfp_0_0_sink = xgmii_ep.XGMIISink()
qsfp_0_0_sink_logic = qsfp_0_0_sink.create_logic(qsfp_0_tx_clk_0,
qsfp_0_tx_rst_0,
rxd=qsfp_0_txd_0,
rxc=qsfp_0_txc_0,
name='qsfp_0_0_sink')
qsfp_0_1_source = xgmii_ep.XGMIISource()
qsfp_0_1_source_logic = qsfp_0_1_source.create_logic(
qsfp_0_rx_clk_1,
qsfp_0_rx_rst_1,
txd=qsfp_0_rxd_1,
txc=qsfp_0_rxc_1,
name='qsfp_0_1_source')
qsfp_0_1_sink = xgmii_ep.XGMIISink()
qsfp_0_1_sink_logic = qsfp_0_1_sink.create_logic(qsfp_0_tx_clk_1,
qsfp_0_tx_rst_1,
rxd=qsfp_0_txd_1,
rxc=qsfp_0_txc_1,
name='qsfp_0_1_sink')
qsfp_0_2_source = xgmii_ep.XGMIISource()
qsfp_0_2_source_logic = qsfp_0_2_source.create_logic(
qsfp_0_rx_clk_2,
qsfp_0_rx_rst_2,
txd=qsfp_0_rxd_2,
txc=qsfp_0_rxc_2,
name='qsfp_0_2_source')
qsfp_0_2_sink = xgmii_ep.XGMIISink()
qsfp_0_2_sink_logic = qsfp_0_2_sink.create_logic(qsfp_0_tx_clk_2,
qsfp_0_tx_rst_2,
rxd=qsfp_0_txd_2,
rxc=qsfp_0_txc_2,
name='qsfp_0_2_sink')
qsfp_0_3_source = xgmii_ep.XGMIISource()
qsfp_0_3_source_logic = qsfp_0_3_source.create_logic(
qsfp_0_rx_clk_3,
qsfp_0_rx_rst_3,
txd=qsfp_0_rxd_3,
txc=qsfp_0_rxc_3,
name='qsfp_0_3_source')
qsfp_0_3_sink = xgmii_ep.XGMIISink()
qsfp_0_3_sink_logic = qsfp_0_3_sink.create_logic(qsfp_0_tx_clk_3,
qsfp_0_tx_rst_3,
rxd=qsfp_0_txd_3,
rxc=qsfp_0_txc_3,
name='qsfp_0_3_sink')
qsfp_1_0_source = xgmii_ep.XGMIISource()
qsfp_1_0_source_logic = qsfp_1_0_source.create_logic(
qsfp_1_rx_clk_0,
qsfp_1_rx_rst_0,
txd=qsfp_1_rxd_0,
txc=qsfp_1_rxc_0,
name='qsfp_1_0_source')
qsfp_1_0_sink = xgmii_ep.XGMIISink()
qsfp_1_0_sink_logic = qsfp_1_0_sink.create_logic(qsfp_1_tx_clk_0,
qsfp_1_tx_rst_0,
rxd=qsfp_1_txd_0,
rxc=qsfp_1_txc_0,
name='qsfp_1_0_sink')
qsfp_1_1_source = xgmii_ep.XGMIISource()
qsfp_1_1_source_logic = qsfp_1_1_source.create_logic(
qsfp_1_rx_clk_1,
qsfp_1_rx_rst_1,
txd=qsfp_1_rxd_1,
txc=qsfp_1_rxc_1,
name='qsfp_1_1_source')
qsfp_1_1_sink = xgmii_ep.XGMIISink()
qsfp_1_1_sink_logic = qsfp_1_1_sink.create_logic(qsfp_1_tx_clk_1,
qsfp_1_tx_rst_1,
rxd=qsfp_1_txd_1,
rxc=qsfp_1_txc_1,
name='qsfp_1_1_sink')
qsfp_1_2_source = xgmii_ep.XGMIISource()
qsfp_1_2_source_logic = qsfp_1_2_source.create_logic(
qsfp_1_rx_clk_2,
qsfp_1_rx_rst_2,
txd=qsfp_1_rxd_2,
txc=qsfp_1_rxc_2,
name='qsfp_1_2_source')
qsfp_1_2_sink = xgmii_ep.XGMIISink()
qsfp_1_2_sink_logic = qsfp_1_2_sink.create_logic(qsfp_1_tx_clk_2,
qsfp_1_tx_rst_2,
rxd=qsfp_1_txd_2,
rxc=qsfp_1_txc_2,
name='qsfp_1_2_sink')
qsfp_1_3_source = xgmii_ep.XGMIISource()
qsfp_1_3_source_logic = qsfp_1_3_source.create_logic(
qsfp_1_rx_clk_3,
qsfp_1_rx_rst_3,
txd=qsfp_1_rxd_3,
txc=qsfp_1_rxc_3,
name='qsfp_1_3_source')
qsfp_1_3_sink = xgmii_ep.XGMIISink()
qsfp_1_3_sink_logic = qsfp_1_3_sink.create_logic(qsfp_1_tx_clk_3,
qsfp_1_tx_rst_3,
rxd=qsfp_1_txd_3,
rxc=qsfp_1_txc_3,
name='qsfp_1_3_sink')
# Clock and Reset Interface
user_clk = Signal(bool(0))
user_reset = Signal(bool(0))
sys_clk = Signal(bool(0))
sys_reset = Signal(bool(0))
# PCIe devices
rc = pcie.RootComplex()
rc.max_payload_size = 0x1 # 256 bytes
rc.max_read_request_size = 0x5 # 4096 bytes
driver = mqnic.Driver(rc)
dev = pcie_usp.UltrascalePlusPCIe()
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.functions[0].msi_multiple_message_capable = 5
dev.functions[0].configure_bar(0, 16 * 1024 * 1024)
dev.functions[0].configure_bar(1, 16 * 1024 * 1024)
rc.make_port().connect(dev)
cq_pause = Signal(bool(0))
cc_pause = Signal(bool(0))
rq_pause = Signal(bool(0))
rc_pause = Signal(bool(0))
pcie_logic = dev.create_logic(
# Completer reQuest Interface
m_axis_cq_tdata=s_axis_cq_tdata,
m_axis_cq_tuser=s_axis_cq_tuser,
m_axis_cq_tlast=s_axis_cq_tlast,
m_axis_cq_tkeep=s_axis_cq_tkeep,
m_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cq_tready=s_axis_cq_tready,
#pcie_cq_np_req=pcie_cq_np_req,
pcie_cq_np_req=Signal(intbv(3)[2:]),
#pcie_cq_np_req_count=pcie_cq_np_req_count,
# Completer Completion Interface
s_axis_cc_tdata=m_axis_cc_tdata,
s_axis_cc_tuser=m_axis_cc_tuser,
s_axis_cc_tlast=m_axis_cc_tlast,
s_axis_cc_tkeep=m_axis_cc_tkeep,
s_axis_cc_tvalid=m_axis_cc_tvalid,
s_axis_cc_tready=m_axis_cc_tready,
# Requester reQuest Interface
s_axis_rq_tdata=m_axis_rq_tdata,
s_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_tlast=m_axis_rq_tlast,
s_axis_rq_tkeep=m_axis_rq_tkeep,
s_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rq_tready=m_axis_rq_tready,
#pcie_rq_seq_num0=pcie_rq_seq_num0,
#pcie_rq_seq_num_vld0=pcie_rq_seq_num_vld0,
#pcie_rq_seq_num1=pcie_rq_seq_num1,
#pcie_rq_seq_num_vld1=pcie_rq_seq_num_vld1,
#pcie_rq_tag0=pcie_rq_tag0,
#pcie_rq_tag1=pcie_rq_tag1,
#pcie_rq_tag_av=pcie_rq_tag_av,
#pcie_rq_tag_vld0=pcie_rq_tag_vld0,
#pcie_rq_tag_vld1=pcie_rq_tag_vld1,
# Requester Completion Interface
m_axis_rc_tdata=s_axis_rc_tdata,
m_axis_rc_tuser=s_axis_rc_tuser,
m_axis_rc_tlast=s_axis_rc_tlast,
m_axis_rc_tkeep=s_axis_rc_tkeep,
m_axis_rc_tvalid=s_axis_rc_tvalid,
m_axis_rc_tready=s_axis_rc_tready,
# Transmit Flow Control Interface
#pcie_tfc_nph_av=pcie_tfc_nph_av,
#pcie_tfc_npd_av=pcie_tfc_npd_av,
# Configuration Management Interface
cfg_mgmt_addr=cfg_mgmt_addr,
cfg_mgmt_function_number=cfg_mgmt_function_number,
cfg_mgmt_write=cfg_mgmt_write,
cfg_mgmt_write_data=cfg_mgmt_write_data,
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
cfg_mgmt_read=cfg_mgmt_read,
cfg_mgmt_read_data=cfg_mgmt_read_data,
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
#cfg_mgmt_debug_access=cfg_mgmt_debug_access,
# Configuration Status Interface
#cfg_phy_link_down=cfg_phy_link_down,
#cfg_phy_link_status=cfg_phy_link_status,
#cfg_negotiated_width=cfg_negotiated_width,
#cfg_current_speed=cfg_current_speed,
cfg_max_payload=cfg_max_payload,
cfg_max_read_req=cfg_max_read_req,
#cfg_function_status=cfg_function_status,
#cfg_vf_status=cfg_vf_status,
#cfg_function_power_state=cfg_function_power_state,
#cfg_vf_power_state=cfg_vf_power_state,
#cfg_link_power_state=cfg_link_power_state,
#cfg_err_cor_out=cfg_err_cor_out,
#cfg_err_nonfatal_out=cfg_err_nonfatal_out,
#cfg_err_fatal_out=cfg_err_fatal_out,
#cfg_local_err_out=cfg_local_err_out,
#cfg_local_err_valid=cfg_local_err_valid,
#cfg_rx_pm_state=cfg_rx_pm_state,
#cfg_tx_pm_state=cfg_tx_pm_state,
#cfg_ltssm_state=cfg_ltssm_state,
#cfg_rcb_status=cfg_rcb_status,
#cfg_obff_enable=cfg_obff_enable,
#cfg_pl_status_change=cfg_pl_status_change,
#cfg_tph_requester_enable=cfg_tph_requester_enable,
#cfg_tph_st_mode=cfg_tph_st_mode,
#cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable,
#cfg_vf_tph_st_mode=cfg_vf_tph_st_mode,
# Configuration Received Message Interface
#cfg_msg_received=cfg_msg_received,
#cfg_msg_received_data=cfg_msg_received_data,
#cfg_msg_received_type=cfg_msg_received_type,
# Configuration Transmit Message Interface
#cfg_msg_transmit=cfg_msg_transmit,
#cfg_msg_transmit_type=cfg_msg_transmit_type,
#cfg_msg_transmit_data=cfg_msg_transmit_data,
#cfg_msg_transmit_done=cfg_msg_transmit_done,
# Configuration Flow Control Interface
#cfg_fc_ph=cfg_fc_ph,
#cfg_fc_pd=cfg_fc_pd,
#cfg_fc_nph=cfg_fc_nph,
#cfg_fc_npd=cfg_fc_npd,
#cfg_fc_cplh=cfg_fc_cplh,
#cfg_fc_cpld=cfg_fc_cpld,
#cfg_fc_sel=cfg_fc_sel,
# Configuration Control Interface
#cfg_hot_reset_in=cfg_hot_reset_in,
#cfg_hot_reset_out=cfg_hot_reset_out,
#cfg_config_space_enable=cfg_config_space_enable,
#cfg_dsn=cfg_dsn,
#cfg_ds_port_number=cfg_ds_port_number,
#cfg_ds_bus_number=cfg_ds_bus_number,
#cfg_ds_device_number=cfg_ds_device_number,
#cfg_ds_function_number=cfg_ds_function_number,
#cfg_power_state_change_ack=cfg_power_state_change_ack,
#cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
cfg_err_cor_in=status_error_cor,
cfg_err_uncor_in=status_error_uncor,
#cfg_flr_done=cfg_flr_done,
#cfg_vf_flr_done=cfg_vf_flr_done,
#cfg_flr_in_process=cfg_flr_in_process,
#cfg_vf_flr_in_process=cfg_vf_flr_in_process,
#cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
#cfg_link_training_enable=cfg_link_training_enable,
# Configuration Interrupt Controller Interface
#cfg_interrupt_int=cfg_interrupt_int,
#cfg_interrupt_sent=cfg_interrupt_sent,
#cfg_interrupt_pending=cfg_interrupt_pending,
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_pending_status_data_enable=
cfg_interrupt_msi_pending_status_data_enable,
cfg_interrupt_msi_pending_status_function_num=
cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
#cfg_interrupt_msix_enable=cfg_interrupt_msix_enable,
#cfg_interrupt_msix_mask=cfg_interrupt_msix_mask,
#cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable,
#cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask,
#cfg_interrupt_msix_address=cfg_interrupt_msix_address,
#cfg_interrupt_msix_data=cfg_interrupt_msix_data,
#cfg_interrupt_msix_int=cfg_interrupt_msix_int,
#cfg_interrupt_msix_vec_pending=cfg_interrupt_msix_vec_pending,
#cfg_interrupt_msix_vec_pending_status=cfg_interrupt_msix_vec_pending_status,
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
# Configuration Extend Interface
#cfg_ext_read_received=cfg_ext_read_received,
#cfg_ext_write_received=cfg_ext_write_received,
#cfg_ext_register_number=cfg_ext_register_number,
#cfg_ext_function_number=cfg_ext_function_number,
#cfg_ext_write_data=cfg_ext_write_data,
#cfg_ext_write_byte_enable=cfg_ext_write_byte_enable,
#cfg_ext_read_data=cfg_ext_read_data,
#cfg_ext_read_data_valid=cfg_ext_read_data_valid,
# Clock and Reset Interface
user_clk=user_clk,
user_reset=user_reset,
sys_clk=sys_clk,
sys_clk_gt=sys_clk,
sys_reset=sys_reset,
#phy_rdy_out=phy_rdy_out,
cq_pause=cq_pause,
cc_pause=cc_pause,
rq_pause=rq_pause,
rc_pause=rc_pause)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
clk_156mhz=clk_156mhz,
rst_156mhz=rst_156mhz,
clk_250mhz=user_clk,
rst_250mhz=user_reset,
user_led_g=user_led_g,
user_led_r=user_led_r,
front_led=front_led,
user_sw=user_sw,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tlast=m_axis_rq_tlast,
m_axis_rq_tready=m_axis_rq_tready,
m_axis_rq_tuser=m_axis_rq_tuser,
m_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rc_tdata=s_axis_rc_tdata,
s_axis_rc_tkeep=s_axis_rc_tkeep,
s_axis_rc_tlast=s_axis_rc_tlast,
s_axis_rc_tready=s_axis_rc_tready,
s_axis_rc_tuser=s_axis_rc_tuser,
s_axis_rc_tvalid=s_axis_rc_tvalid,
s_axis_cq_tdata=s_axis_cq_tdata,
s_axis_cq_tkeep=s_axis_cq_tkeep,
s_axis_cq_tlast=s_axis_cq_tlast,
s_axis_cq_tready=s_axis_cq_tready,
s_axis_cq_tuser=s_axis_cq_tuser,
s_axis_cq_tvalid=s_axis_cq_tvalid,
m_axis_cc_tdata=m_axis_cc_tdata,
m_axis_cc_tkeep=m_axis_cc_tkeep,
m_axis_cc_tlast=m_axis_cc_tlast,
m_axis_cc_tready=m_axis_cc_tready,
m_axis_cc_tuser=m_axis_cc_tuser,
m_axis_cc_tvalid=m_axis_cc_tvalid,
pcie_tfc_nph_av=pcie_tfc_nph_av,
pcie_tfc_npd_av=pcie_tfc_npd_av,
cfg_max_payload=cfg_max_payload,
cfg_max_read_req=cfg_max_read_req,
cfg_mgmt_addr=cfg_mgmt_addr,
cfg_mgmt_function_number=cfg_mgmt_function_number,
cfg_mgmt_write=cfg_mgmt_write,
cfg_mgmt_write_data=cfg_mgmt_write_data,
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
cfg_mgmt_read=cfg_mgmt_read,
cfg_mgmt_read_data=cfg_mgmt_read_data,
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
cfg_interrupt_msi_pending_status_function_num=
cfg_interrupt_msi_pending_status_function_num,
cfg_interrupt_msi_pending_status_data_enable=
cfg_interrupt_msi_pending_status_data_enable,
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
status_error_cor=status_error_cor,
status_error_uncor=status_error_uncor,
qsfp_0_tx_clk_0=qsfp_0_tx_clk_0,
qsfp_0_tx_rst_0=qsfp_0_tx_rst_0,
qsfp_0_txd_0=qsfp_0_txd_0,
qsfp_0_txc_0=qsfp_0_txc_0,
qsfp_0_rx_clk_0=qsfp_0_rx_clk_0,
qsfp_0_rx_rst_0=qsfp_0_rx_rst_0,
qsfp_0_rxd_0=qsfp_0_rxd_0,
qsfp_0_rxc_0=qsfp_0_rxc_0,
qsfp_0_tx_clk_1=qsfp_0_tx_clk_1,
qsfp_0_tx_rst_1=qsfp_0_tx_rst_1,
qsfp_0_txd_1=qsfp_0_txd_1,
qsfp_0_txc_1=qsfp_0_txc_1,
qsfp_0_rx_clk_1=qsfp_0_rx_clk_1,
qsfp_0_rx_rst_1=qsfp_0_rx_rst_1,
qsfp_0_rxd_1=qsfp_0_rxd_1,
qsfp_0_rxc_1=qsfp_0_rxc_1,
qsfp_0_tx_clk_2=qsfp_0_tx_clk_2,
qsfp_0_tx_rst_2=qsfp_0_tx_rst_2,
qsfp_0_txd_2=qsfp_0_txd_2,
qsfp_0_txc_2=qsfp_0_txc_2,
qsfp_0_rx_clk_2=qsfp_0_rx_clk_2,
qsfp_0_rx_rst_2=qsfp_0_rx_rst_2,
qsfp_0_rxd_2=qsfp_0_rxd_2,
qsfp_0_rxc_2=qsfp_0_rxc_2,
qsfp_0_tx_clk_3=qsfp_0_tx_clk_3,
qsfp_0_tx_rst_3=qsfp_0_tx_rst_3,
qsfp_0_txd_3=qsfp_0_txd_3,
qsfp_0_txc_3=qsfp_0_txc_3,
qsfp_0_rx_clk_3=qsfp_0_rx_clk_3,
qsfp_0_rx_rst_3=qsfp_0_rx_rst_3,
qsfp_0_rxd_3=qsfp_0_rxd_3,
qsfp_0_rxc_3=qsfp_0_rxc_3,
qsfp_0_modprs_l=qsfp_0_modprs_l,
qsfp_0_sel_l=qsfp_0_sel_l,
qsfp_1_tx_clk_0=qsfp_1_tx_clk_0,
qsfp_1_tx_rst_0=qsfp_1_tx_rst_0,
qsfp_1_txd_0=qsfp_1_txd_0,
qsfp_1_txc_0=qsfp_1_txc_0,
qsfp_1_rx_clk_0=qsfp_1_rx_clk_0,
qsfp_1_rx_rst_0=qsfp_1_rx_rst_0,
qsfp_1_rxd_0=qsfp_1_rxd_0,
qsfp_1_rxc_0=qsfp_1_rxc_0,
qsfp_1_tx_clk_1=qsfp_1_tx_clk_1,
qsfp_1_tx_rst_1=qsfp_1_tx_rst_1,
qsfp_1_txd_1=qsfp_1_txd_1,
qsfp_1_txc_1=qsfp_1_txc_1,
qsfp_1_rx_clk_1=qsfp_1_rx_clk_1,
qsfp_1_rx_rst_1=qsfp_1_rx_rst_1,
qsfp_1_rxd_1=qsfp_1_rxd_1,
qsfp_1_rxc_1=qsfp_1_rxc_1,
qsfp_1_tx_clk_2=qsfp_1_tx_clk_2,
qsfp_1_tx_rst_2=qsfp_1_tx_rst_2,
qsfp_1_txd_2=qsfp_1_txd_2,
qsfp_1_txc_2=qsfp_1_txc_2,
qsfp_1_rx_clk_2=qsfp_1_rx_clk_2,
qsfp_1_rx_rst_2=qsfp_1_rx_rst_2,
qsfp_1_rxd_2=qsfp_1_rxd_2,
qsfp_1_rxc_2=qsfp_1_rxc_2,
qsfp_1_tx_clk_3=qsfp_1_tx_clk_3,
qsfp_1_tx_rst_3=qsfp_1_tx_rst_3,
qsfp_1_txd_3=qsfp_1_txd_3,
qsfp_1_txc_3=qsfp_1_txc_3,
qsfp_1_rx_clk_3=qsfp_1_rx_clk_3,
qsfp_1_rx_rst_3=qsfp_1_rx_rst_3,
qsfp_1_rxd_3=qsfp_1_rxd_3,
qsfp_1_rxc_3=qsfp_1_rxc_3,
qsfp_1_modprs_l=qsfp_1_modprs_l,
qsfp_1_sel_l=qsfp_1_sel_l,
qsfp_reset_l=qsfp_reset_l,
qsfp_int_l=qsfp_int_l,
qsfp_i2c_scl_i=qsfp_i2c_scl_i,
qsfp_i2c_scl_o=qsfp_i2c_scl_o,
qsfp_i2c_scl_t=qsfp_i2c_scl_t,
qsfp_i2c_sda_i=qsfp_i2c_sda_i,
qsfp_i2c_sda_o=qsfp_i2c_sda_o,
qsfp_i2c_sda_t=qsfp_i2c_sda_t,
eeprom_i2c_scl_i=eeprom_i2c_scl_i,
eeprom_i2c_scl_o=eeprom_i2c_scl_o,
eeprom_i2c_scl_t=eeprom_i2c_scl_t,
eeprom_i2c_sda_i=eeprom_i2c_sda_i,
eeprom_i2c_sda_o=eeprom_i2c_sda_o,
eeprom_i2c_sda_t=eeprom_i2c_sda_t,
eeprom_wp=eeprom_wp)
@always(delay(5))
def clkgen():
clk.next = not clk
@always(delay(3))
def qsfp_clkgen():
qsfp_0_tx_clk_0.next = not qsfp_0_tx_clk_0
qsfp_0_rx_clk_0.next = not qsfp_0_rx_clk_0
qsfp_0_tx_clk_1.next = not qsfp_0_tx_clk_1
qsfp_0_rx_clk_1.next = not qsfp_0_rx_clk_1
qsfp_0_tx_clk_2.next = not qsfp_0_tx_clk_2
qsfp_0_rx_clk_2.next = not qsfp_0_rx_clk_2
qsfp_0_tx_clk_3.next = not qsfp_0_tx_clk_3
qsfp_0_rx_clk_3.next = not qsfp_0_rx_clk_3
qsfp_1_tx_clk_0.next = not qsfp_1_tx_clk_0
qsfp_1_rx_clk_0.next = not qsfp_1_rx_clk_0
qsfp_1_tx_clk_1.next = not qsfp_1_tx_clk_1
qsfp_1_rx_clk_1.next = not qsfp_1_rx_clk_1
qsfp_1_tx_clk_2.next = not qsfp_1_tx_clk_2
qsfp_1_rx_clk_2.next = not qsfp_1_rx_clk_2
qsfp_1_tx_clk_3.next = not qsfp_1_tx_clk_3
qsfp_1_rx_clk_3.next = not qsfp_1_rx_clk_3
@always_comb
def clk_logic():
sys_clk.next = clk
sys_reset.next = not rst
loopback_enable = Signal(bool(0))
@instance
def loopback():
while True:
yield clk.posedge
if loopback_enable:
if not qsfp_0_0_sink.empty():
pkt = qsfp_0_0_sink.recv()
qsfp_0_0_source.send(pkt)
if not qsfp_0_1_sink.empty():
pkt = qsfp_0_1_sink.recv()
qsfp_0_1_source.send(pkt)
if not qsfp_0_2_sink.empty():
pkt = qsfp_0_2_sink.recv()
qsfp_0_2_source.send(pkt)
if not qsfp_0_3_sink.empty():
pkt = qsfp_0_3_sink.recv()
qsfp_0_3_source.send(pkt)
if not qsfp_1_0_sink.empty():
pkt = qsfp_1_0_sink.recv()
qsfp_1_0_source.send(pkt)
if not qsfp_1_1_sink.empty():
pkt = qsfp_1_1_sink.recv()
qsfp_1_1_source.send(pkt)
if not qsfp_1_2_sink.empty():
pkt = qsfp_1_2_sink.recv()
qsfp_1_2_source.send(pkt)
if not qsfp_1_3_sink.empty():
pkt = qsfp_1_3_sink.recv()
qsfp_1_3_source.send(pkt)
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
qsfp_0_tx_rst_0.next = 1
qsfp_0_rx_rst_0.next = 1
qsfp_0_tx_rst_1.next = 1
qsfp_0_rx_rst_1.next = 1
qsfp_0_tx_rst_2.next = 1
qsfp_0_rx_rst_2.next = 1
qsfp_0_tx_rst_3.next = 1
qsfp_0_rx_rst_3.next = 1
qsfp_1_tx_rst_0.next = 1
qsfp_1_rx_rst_0.next = 1
qsfp_1_tx_rst_1.next = 1
qsfp_1_rx_rst_1.next = 1
qsfp_1_tx_rst_2.next = 1
qsfp_1_rx_rst_2.next = 1
qsfp_1_tx_rst_3.next = 1
qsfp_1_rx_rst_3.next = 1
yield clk.posedge
yield delay(100)
rst.next = 0
qsfp_0_tx_rst_0.next = 0
qsfp_0_rx_rst_0.next = 0
qsfp_0_tx_rst_1.next = 0
qsfp_0_rx_rst_1.next = 0
qsfp_0_tx_rst_2.next = 0
qsfp_0_rx_rst_2.next = 0
qsfp_0_tx_rst_3.next = 0
qsfp_0_rx_rst_3.next = 0
qsfp_1_tx_rst_0.next = 0
qsfp_1_rx_rst_0.next = 0
qsfp_1_tx_rst_1.next = 0
qsfp_1_rx_rst_1.next = 0
qsfp_1_tx_rst_2.next = 0
qsfp_1_rx_rst_2.next = 0
qsfp_1_tx_rst_3.next = 0
qsfp_1_rx_rst_3.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
current_tag = 1
yield clk.posedge
print("test 1: enumeration")
current_test.next = 1
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()
# enable queues
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0200,
0xffffffff)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0300,
0xffffffff)
yield from rc.mem_read(driver.hw_addr,
4) # wait for all writes to complete
yield delay(100)
yield clk.posedge
print("test 3: send and receive a packet")
current_test.next = 3
# test bad packet
#qsfp_0_0_source.send(b'\x55\x55\x55\x55\x55\xd5'+bytearray(range(128)))
data = bytearray([x % 256 for x in range(1024)])
yield from driver.interfaces[0].start_xmit(data, 0)
yield qsfp_0_0_sink.wait()
pkt = qsfp_0_0_sink.recv()
print(pkt)
qsfp_0_0_source.send(pkt)
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert frame_checksum(pkt.data) == pkt.rx_checksum
# yield from driver.interfaces[1].start_xmit(data, 0)
# yield qsfp_1_0_sink.wait()
# pkt = qsfp_1_0_sink.recv()
# print(pkt)
# qsfp_1_0_source.send(pkt)
# yield driver.interfaces[1].wait()
# pkt = driver.interfaces[1].recv()
# print(pkt)
# assert frame_checksum(pkt.data) == pkt.rx_checksum
yield delay(100)
yield clk.posedge
print("test 4: multiple small packets")
current_test.next = 4
count = 64
pkts = [
bytearray([(x + k) % 256 for x in range(64)]) for k in range(count)
]
loopback_enable.next = True
for p in pkts:
yield from driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.data == pkts[k]
assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(100)
yield clk.posedge
print("test 5: multiple large packets")
current_test.next = 5
count = 64
pkts = [
bytearray([(x + k) % 256 for x in range(1514)])
for k in range(count)
]
loopback_enable.next = True
for p in pkts:
yield from driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
assert pkt.data == pkts[k]
assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(1000)
yield clk.posedge
print("test 6: TDMA")
current_test.next = 6
count = 16
pkts = [
bytearray([(x + k) % 256 for x in range(1514)])
for k in range(count)
]
loopback_enable.next = True
# configure TDMA
# configure TDMA scheduler
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00120,
0) # schedule period fns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00124,
40000) # schedule period ns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00128,
0) # schedule period sec (low)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0012c,
0) # schedule period sec (high)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00130,
0) # timeslot period fns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00134,
10000) # timeslot period ns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00138,
0) # timeslot period sec (low)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0013c,
0) # timeslot period sec (high)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00140,
0) # active period fns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00144,
5000) # active period ns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00148,
0) # active period sec (low)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0014c,
0) # active period sec (high)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00110,
0) # schedule start fns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00114,
200000) # schedule start ns
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00118,
0) # schedule start sec (low)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x0011c,
0) # schedule start sec (high)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00100,
0x00000001)
# enable queues
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00200,
0xffffffff)
# disable global enable
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x00300,
0x00000000)
# configure slots
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10000,
0x00000001)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10100,
0x00000002)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10200,
0x00000004)
yield from rc.mem_write_dword(
driver.interfaces[0].ports[0].schedulers[0].hw_addr + 0x10300,
0x00000008)
yield from rc.mem_read(driver.hw_addr,
4) # wait for all writes to complete
# send packets
for k in range(count):
yield from driver.interfaces[0].start_xmit(pkts[k], k % 4)
for k in range(count):
pkt = driver.interfaces[0].recv()
if not pkt:
yield driver.interfaces[0].wait()
pkt = driver.interfaces[0].recv()
print(pkt)
#assert pkt.data == pkts[k]
#assert frame_checksum(pkt.data) == pkt.rx_checksum
loopback_enable.next = False
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
ENABLE_PADDING = 1
MIN_FRAME_LENGTH = 64
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_tdata = Signal(intbv(0)[64:])
s_axis_tkeep = Signal(intbv(0)[8:])
s_axis_tvalid = Signal(bool(0))
s_axis_tlast = Signal(bool(0))
s_axis_tuser = Signal(bool(0))
ifg_delay = Signal(intbv(0)[8:])
# Outputs
s_axis_tready = Signal(bool(0))
xgmii_txd = Signal(intbv(0x0707070707070707)[64:])
xgmii_txc = Signal(intbv(0xff)[8:])
start_packet_0 = Signal(bool(0))
start_packet_4 = Signal(bool(0))
# sources and sinks
source_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(
clk,
rst,
tdata=s_axis_tdata,
tkeep=s_axis_tkeep,
tvalid=s_axis_tvalid,
tready=s_axis_tready,
tlast=s_axis_tlast,
tuser=s_axis_tuser,
pause=source_pause,
name='source'
)
sink = xgmii_ep.XGMIISink()
sink_logic = sink.create_logic(
clk,
rst,
rxd=xgmii_txd,
rxc=xgmii_txc,
name='sink'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axis_tdata=s_axis_tdata,
s_axis_tkeep=s_axis_tkeep,
s_axis_tvalid=s_axis_tvalid,
s_axis_tready=s_axis_tready,
s_axis_tlast=s_axis_tlast,
s_axis_tuser=s_axis_tuser,
xgmii_txd=xgmii_txd,
xgmii_txc=xgmii_txc,
ifg_delay=ifg_delay,
start_packet_0=start_packet_0,
start_packet_4=start_packet_4
)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
for payload_len in list(range(1,18))+list(range(40,58)):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(payload_len))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
source.send(axis_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
source.send(axis_frame1)
source.send(axis_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame1.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame1.eth_src_mac
assert eth_frame.eth_type == test_frame1.eth_type
assert eth_frame.payload.data.index(test_frame1.payload.data) == 0
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
assert eth_frame.eth_type == test_frame2.eth_type
assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
axis_frame1.last_cycle_user = 1
source.send(axis_frame1)
source.send(axis_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
assert rx_frame.error[-1]
# bad packet
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
assert eth_frame.eth_type == test_frame2.eth_type
assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
assert sink.empty()
yield delay(100)
for payload_len in list(range(46,54)):
yield clk.posedge
print("test 4: test stream, length %d" % payload_len)
current_test.next = 4
for i in range(10):
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(payload_len))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
source.send(axis_frame)
for i in range(10):
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
ENABLE_PADDING = 1
ENABLE_DIC = 1
MIN_FRAME_LENGTH = 64
TX_FIFO_ADDR_WIDTH = 9
RX_FIFO_ADDR_WIDTH = 9
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
rx_clk = Signal(bool(0))
rx_rst = Signal(bool(0))
tx_clk = Signal(bool(0))
tx_rst = Signal(bool(0))
logic_clk = Signal(bool(0))
logic_rst = Signal(bool(0))
tx_axis_tdata = Signal(intbv(0)[64:])
tx_axis_tkeep = Signal(intbv(0)[8:])
tx_axis_tvalid = Signal(bool(0))
tx_axis_tlast = Signal(bool(0))
tx_axis_tuser = Signal(bool(0))
rx_axis_tready = Signal(bool(0))
xgmii_rxd = Signal(intbv(0x0707070707070707)[64:])
xgmii_rxc = Signal(intbv(0xff)[8:])
ifg_delay = Signal(intbv(0)[8:])
# Outputs
tx_axis_tready = Signal(bool(0))
rx_axis_tdata = Signal(intbv(0)[64:])
rx_axis_tkeep = Signal(intbv(0)[8:])
rx_axis_tvalid = Signal(bool(0))
rx_axis_tlast = Signal(bool(0))
rx_axis_tuser = Signal(bool(0))
xgmii_txd = Signal(intbv(0x0707070707070707)[64:])
xgmii_txc = Signal(intbv(0xff)[8:])
tx_fifo_overflow = Signal(bool(0))
tx_fifo_bad_frame = Signal(bool(0))
tx_fifo_good_frame = Signal(bool(0))
rx_error_bad_frame = Signal(bool(0))
rx_error_bad_fcs = Signal(bool(0))
rx_fifo_overflow = Signal(bool(0))
rx_fifo_bad_frame = Signal(bool(0))
rx_fifo_good_frame = Signal(bool(0))
# sources and sinks
xgmii_source_queue = Queue()
xgmii_sink_queue = Queue()
axis_source_queue = Queue()
axis_source_pause = Signal(bool(0))
axis_sink_queue = Queue()
xgmii_source = xgmii_ep.XGMIISource(rx_clk,
rx_rst,
txd=xgmii_rxd,
txc=xgmii_rxc,
fifo=xgmii_source_queue,
name='xgmii_source')
xgmii_sink = xgmii_ep.XGMIISink(tx_clk,
tx_rst,
rxd=xgmii_txd,
rxc=xgmii_txc,
fifo=xgmii_sink_queue,
name='xgmii_sink')
axis_source = axis_ep.AXIStreamSource(tx_clk,
tx_rst,
tdata=tx_axis_tdata,
tkeep=tx_axis_tkeep,
tvalid=tx_axis_tvalid,
tready=tx_axis_tready,
tlast=tx_axis_tlast,
tuser=tx_axis_tuser,
fifo=axis_source_queue,
pause=axis_source_pause,
name='axis_source')
axis_sink = axis_ep.AXIStreamSink(rx_clk,
rx_rst,
tdata=rx_axis_tdata,
tkeep=rx_axis_tkeep,
tvalid=rx_axis_tvalid,
tready=rx_axis_tready,
tlast=rx_axis_tlast,
tuser=rx_axis_tuser,
fifo=axis_sink_queue,
name='axis_sink')
# DUT
dut = dut_eth_mac_1g(clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
logic_clk,
logic_rst,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tready,
tx_axis_tlast,
tx_axis_tuser,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tready,
rx_axis_tlast,
rx_axis_tuser,
xgmii_rxd,
xgmii_rxc,
xgmii_txd,
xgmii_txc,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame,
ifg_delay)
@always(delay(4))
def clkgen():
clk.next = not clk
tx_clk.next = not tx_clk
rx_clk.next = not rx_clk
logic_clk.next = not logic_clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
tx_rst.next = 1
rx_rst.next = 1
logic_rst.next = 1
yield clk.posedge
rst.next = 0
tx_rst.next = 0
rx_rst.next = 0
logic_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
yield clk.posedge
print("test 1: test rx packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
xgmii_source_queue.put(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame))
yield clk.posedge
yield clk.posedge
while xgmii_rxc != 0xff:
yield clk.posedge
yield delay(100)
while rx_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not axis_sink_queue.empty():
rx_frame = axis_sink_queue.get()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: test tx packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
axis_source_queue.put(axis_frame)
yield clk.posedge
yield clk.posedge
while tx_axis_tvalid:
yield clk.posedge
yield delay(100)
while xgmii_txc != 0xff:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not xgmii_sink_queue.empty():
rx_frame = xgmii_sink_queue.get()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == 46
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
yield delay(100)
raise StopSimulation
return dut, axis_source, axis_sink, xgmii_source, xgmii_sink, clkgen, check
