def do_ROUND(op, stack, state):
prev_type = state.esil["type"]
state.esil["type"] = FLOAT
val, = pop_values(stack, state)
stack.append(z3.fpRoundToIntegral(FPM, val))
state.esil["type"] = prev_type
else:
cmp = smt._icmp_ops[term.op]
# only the signed ones can be FP, so this is safe
return cmp(smt.eval(term.x), smt.eval(term.y))
def _must(op):
return lambda t,s: s._must_analysis(t, op)
eval.register(CannotBeNegativeZeroPred, BaseSMTTranslator,
_must(lambda x: z3.Not(x == z3.fpMinusZero(x.sort()))))
eval.register(FPIdenticalPred, BaseSMTTranslator, _handler(operator.eq))
eval.register(FPIntegerPred, BaseSMTTranslator,
_handler(lambda x: x == z3.fpRoundToIntegral(z3.RTZ(), x)))
def _has_attr(attr):
return lambda t,s: s._has_attr(attr, t._args[0])
eval.register(HasNInfPred, BaseSMTTranslator, _has_attr('ninf'))
eval.register(HasNNaNPred, BaseSMTTranslator, _has_attr('nnan'))
eval.register(HasNSWPred, BaseSMTTranslator, _has_attr('nsw'))
eval.register(HasNSZPred, BaseSMTTranslator, _has_attr('nsz'))
eval.register(HasNUWPred, BaseSMTTranslator, _has_attr('nuw'))
eval.register(IsExactPred, BaseSMTTranslator, _has_attr('exact'))
@eval.register(IsConstantPred, BaseSMTTranslator)
def _(term, smt):
arg = term._args[0]
def do_ROUND(op, stack, state):
val, = pop_values(stack, state)
stack.append(z3.fpRoundToIntegral(FPM, val))
# only the signed ones can be FP, so this is safe
return cmp(smt.eval(term.x), smt.eval(term.y))
def _must(op):
return lambda t, s: s._must_analysis(t, op)
eval.register(CannotBeNegativeZeroPred, BaseSMTTranslator,
_must(lambda x: z3.Not(x == z3.fpMinusZero(x.sort()))))
eval.register(FPIdenticalPred, BaseSMTTranslator, _handler(operator.eq))
eval.register(FPIntegerPred, BaseSMTTranslator,
_handler(lambda x: x == z3.fpRoundToIntegral(z3.RTZ(), x)))
def _has_attr(attr):
return lambda t, s: s._has_attr(attr, t._args[0])
eval.register(HasNInfPred, BaseSMTTranslator, _has_attr('ninf'))
eval.register(HasNNaNPred, BaseSMTTranslator, _has_attr('nnan'))
eval.register(HasNSWPred, BaseSMTTranslator, _has_attr('nsw'))
eval.register(HasNSZPred, BaseSMTTranslator, _has_attr('nsz'))
eval.register(HasNUWPred, BaseSMTTranslator, _has_attr('nuw'))
eval.register(IsExactPred, BaseSMTTranslator, _has_attr('exact'))
@eval.register(IsConstantPred, BaseSMTTranslator)
def do_CEIL(op, stack, state):
val, = pop_values(stack, state)
stack.append(z3.fpRoundToIntegral(FPM, val) + 1) # idk