def insertModule():
if len(connectEntry.get()) > 0:
connectValue = connectEntry.get()
ser = serial.Serial(connectValue, 19200)
time.sleep(2)
unit = ControlUnit(ser, protocol)
s = 1
number = str(len(elementen) + 1)
name = '#%s' % number
element = Element(rootframe, name, unit, s)
elementen.append(element)
def connect(self, address='localhost', port=9898, serverError=None):
s = cu.client_connect(address, port)
if s is not None:
self.send = ds.Send(s)
self.recv = ds.Recv(s)
self.recv.function = self.handleMessage
self.recv.get()
self.functionList = {}
self.userName = None
else:
if serverError is not None:
serverError(address, port)
def __init__(self):
self.Login = False
self.s = cu.client_connect('localhost', 4445)
self.count = 1
self.send = ds.Send()
self.recv = ds.Recv()
#threading.Thread(target=self.recvData).start()
#threading.Thread(target=self.checking).start()
#self.recvData()
#threading.Thread(target=self.shower).start()
print("client is connected")
def __init__(self, addr='localhost', port=4445):
self.Login = False
self.s = cu.client_connect(addr, port)
self.count = 1
self.send = ds.Send()
self.recv = ds.Recv()
self.dcond = {}
self.data = {}
threading.Thread(target=self.recvData).start()
threading.Thread(target=self.checking).start()
threading.Thread(target=self.shower).start()
threading.Thread(target=self.sh).start()
print("client is connected")
def __init__(self,addr='localhost',port=9085):
self.Login=False
self.s=cu.client_connect(addr,port)
self.count=1
self.send=ds.Send()
self.recv=ds.Recv()
self.showers=True
self.dcond={}
self.data={}
self.curMessage='NONE'
self.stmessage={}
threading.Thread(target=self.recvData).start()
threading.Thread(target=self.shower).start()
print("client is connected")
def __init__(self,addr='localhost',port=8787):
self.Login=False
self.s=cu.client_connect(addr,port)
self.count=1
self.send=ds.Send(self.s)
self.recv=ds.Recv(self.s)
self.functionList={}
self.function1Type=None
self.function2Type=None
self.function3Type=None
#self.argument1Type=None
#self.argument2Type=None
#self.argument3Type=None
threading.Thread(target=self.recvData).start()
print("client is connected")
def executeInstruction(splitedInstruction, program_counter): name_instruction = splitedInstruction[0] if name_instruction == 'add' or name_instruction == 'mul' or name_instruction == 'sub' or name_instruction == 'div': first_argument = splitedInstruction[1] second_argument = splitedInstruction[2] third_argument = splitedInstruction[3] first_value = getValue(name_instruction, 'Second', second_argument) second_value = getValue(name_instruction, 'Third', third_argument) result = Ula.executeUla(name_instruction, int(first_value), int(second_value)) setValue(name_instruction, first_argument, result) return False elif name_instruction == 'equal' or name_instruction == 'diff' or name_instruction == 'smaller' or name_instruction == 'greater': first_argument = splitedInstruction[1] second_argument = splitedInstruction[2] third_argument = splitedInstruction[3] first_value = getValue(name_instruction, 'First', first_argument) second_value = getValue(name_instruction, 'Second', second_argument) if Ula.executeUla(name_instruction, int(first_value), int(second_value)) == True: ControlUnit.setProgramCounter(third_argument+':') return False elif name_instruction == 'jmp': first_argument = splitedInstruction[1] ControlUnit.setProgramCounter(first_argument+':') return False elif name_instruction[-1] == ':': ControlUnit.setGoToMap(name_instruction, program_counter) return False else: return True
import ControlUnit as cu
import threading
import random
import AssembleData as ad
import DataShare as ds
import XprtLoginControl as xlc
import cv2
import time
import numpy as np
xc=xlc.Controller()
ass=ad.Assemble()
dAssemble=ad.Dassemble()
s=cu.client_connect('localhost',4445)
send=ds.Send()
def dataCvt(data):
userName='******'
type='Camera'
data=np.array(data)
shape=str(data.shape)
types=str(data.dtype)
actData=bytes(data)
actData=ds.encb(actData)
actData=actData.decode()
import ControlUnit
ControlUnit.initControlUnit('../data_handler/instruction.txt')
def testControlUnit():
#Entradas
OPcode = Signal(modbv(0)[7:0])
funct7 = Signal(modbv(0)[7:0])
funct3 = Signal(modbv(0)[3:0])
branch = Signal(modbv(0)[1:0])
x = Signal(modbv(0)[1:0])
#Salidas
RegWrite = Signal(modbv(0)[1:])
RegDest = Signal(modbv(0)[3:])
ALUsrc = Signal(modbv(0)[1:])
ALUop = Signal(modbv(0)[4:])
DWidth = Signal(modbv(0)[3:])
PCsrc = Signal(modbv(0)[1:])
Sel_Mux = Signal(modbv(0)[1:])
dut = ControlUnit(OPcode, funct7, funct3, branch, RegWrite, RegDest,
ALUsrc, ALUop, DWidth, PCsrc, Sel_Mux)
cont = Signal(modbv(0)[4:])
interv = delay(1)
@always(interv)
def stim():
x.next = 0
if cont == 0:
OPcode.next = 0b0110011 #TIPO R
for i in range(10):
if i == 0:
funct7.next = 0b0000000
funct3.next = 0b000 #ADD
elif i == 1:
funct7.next = 0b0000000
funct3.next = 0b010 #SLT
elif i == 2:
funct7.next = 0b0000000
funct3.next = 0b011 #SLTU
elif i == 3:
funct7.next = 0b0000000
funct3.next = 0b111 #AND
elif i == 4:
funct7.next = 0b0000000
funct3.next = 0b110 #OR
elif i == 5:
funct7.next = 0b0000000
funct3.next = 0b100 #XOR
elif i == 6:
funct7.next = 0b0000000
funct3.next = 0b001 #SLL
elif i == 7:
funct7.next = 0b0000000
funct3.next = 0b101 #SRL
elif i == 8:
funct7.next = 0b0100000
funct3.next = 0b000 #SUB
elif i == 9:
funct7.next = 0b0100000
funct3.next = 0b101 #SRA
elif cont == 1:
OPcode.next = 0b0010011 #TIPO I
for i in range(9):
funct7.next = 0b0000000
if i == 0:
funct3.next = 0b000 #ADDI
elif i == 1:
funct3.next = 0b010 #SLTI
elif i == 2:
funct3.next = 0b011 #SLTUI
elif i == 3:
funct3.next = 0b111 #ANDI
elif i == 4:
funct3.next = 0b110 #ORI
elif i == 5:
funct3.next = 0b100 #XORI
elif i == 6:
funct3.next = 0b001 #SLLI
elif i == 7:
funct3.next = 0b101 #SRLI
elif i == 8:
funct3.next = 0b101 #SRA1
elif cont == 2:
OPcode.next = 0b1100111 #TIPO I JAR
funct3.next == 0b000
elif cont == 3:
OPcode.next = 0b0000011 #TIPO I para load
for i in range(5):
if i == 0:
funct3.next = 0b000 #LB
elif i == 1:
funct3.next = 0b001 #LH
elif i == 2:
funct3.next = 0b010 #LW
elif i == 3:
funct3.next = 0b100 #LBU
elif i == 4:
funct3.next = 0b101 #LHU
else:
funct3.next = 0b111
elif cont == 4:
OPcode.next = 0b0100011 #TIPO S
for i in range(3):
if i == 0:
funct3.next = 0b000 #SB
elif i == 1:
funct3.next = 0b001 #SH
elif i == 2:
funct3.next = 0b010 #SW
else:
funct3.next = 0b111
elif cont == 5:
OPcode.next = 0b1100011 #TIPO SB
for i in range(6):
if i == 0:
funct3.next = 0b000 #BEQ
elif i == 1:
funct3.next = 0b001 #BNE
elif i == 2:
funct3.next = 0b100 #BLT
elif i == 3:
funct3.next = 0b101 #BGE
elif i == 4:
funct3.next = 0b110 #BLTU
elif i == 5:
funct3.next = 0b111 #BGEU
else:
funct3.next = 0b111
if x == 0:
branch.next = 0b1 #Sel.mux=1
x.next = 1
else:
branch.next = 0b0 #Sel.mux=0
x.next = 0
elif cont == 6:
OPcode.next = 0b0110111
elif cont == 7:
OPcode.next = 0b0010111
elif cont == 8:
OPcode.next = 0b1101111
cont.next = cont.next + 1
return dut, stim
def isRunning():
global running
return running
#CPU_GUI = threading.Thread(target=GUI.GUI).start()
# Global configurations from .env file and extract global values
global CONFIG
CONFIG = dotenv.dotenv_values(".env")
# Extract values from config file
FREQ = int(CONFIG["CLOCK_FREQ"])
# Initialize clock
clk = Clock.Clock(FREQ)
cu1 = ControlUnit.ControlUnit(clk, FREQ, 0)
cu2 = ControlUnit.ControlUnit(clk, FREQ, 1)
cu3 = ControlUnit.ControlUnit(clk, FREQ, 2)
cu4 = ControlUnit.ControlUnit(clk, FREQ, 3)
threading.Thread(target=cu1.run).start()
threading.Thread(target=cu2.run).start()
threading.Thread(target=cu3.run).start()
threading.Thread(target=cu4.run).start()
clk.changeMode()
threading.Thread(target=clk.run).start()
threading.Thread(target=clk.printClock).start()
def tope(clk, reset, DataOutRAM, Done, Address, DataInRAM, WR, WE, RE):
#Señales
datainstruccion = Signal(
modbv(0)[32:]) #Out:CPR, In:Register,ControlUnit,Inm.
datainmediato = Signal(modbv(0)[32:]) #Out:Inm, In:Mux3,Mux1,Add1
mux3_add2 = Signal(modbv(0)[32:]) #Out:Mux3, In: Add2
Sel_Mux = Signal(modbv(0)[1:]) #Out:Control Unit, In:Mux3
add2_mux4 = Signal(modbv(0)[32:]) #Out:Add2, In:Mux4
PCsrc = Signal(modbv(0)[1:]) #Out: Control Unit, In: Mux4
RegWrite = Signal(modbv(0)[1:]) #Out: Control Unit, In: And
mux4_PC = Signal(modbv(0)[32:]) #Out: Mux4, In:PC
dirdatos = Signal(modbv(0)[32:]) #Out:PC, In:Add2,Add1,Add4,CPR
mux1_000 = Signal(modbv(0)[32:]) #Out:Add4, In:Mux1
mux1_001 = Signal(modbv(0)[32:]) #Out: Add1, In: Mux1
mux1_010 = Signal(modbv(0)[32:]) #Out: Inm, In: Mux1
mux1_011 = Signal(modbv(0)[32:]) #Out:BHW, In:Mux1
RegDest = Signal(modbv(0)[3:]) #Out:Control Unit, In:Mux1
rdd = Signal(modbv(0)[32:]) #Out: Mux1, In:Register File
rd = Signal(modbv(0)[5:]) #Out:Datainstruccion, In:RegisterFile
rs2 = Signal(modbv(0)[5:]) #Out:DataInstruccion, In:Register File
rs1 = Signal(modbv(0)[5:]) #Out:DataInstruccion, In:Register File
r1d = Signal(modbv(0)[32:]) #Out: Register File, In: ALU
#r2d = Signal(modbv(0)[32:]) #Out: Register File, In: Mux2, BRAM
RegEnable = Signal(modbv(0)[1:]) #Out:and, In:Register File
ALUinA = Signal(modbv(0)[32:]) #Out: Mux2, In: ALU
ALUsrc = Signal(modbv(0)[1:]) #Out: Control Unit, In:Mux2
ALUout = Signal(modbv(0)[32:]) #Out: Alu, In:Mux1, Mux4, BRAM Data, CPR
ALUflag = Signal(modbv(0)[1:]) #Out: ALU, In: Control Unit
ALUop = Signal(modbv(0)[4:]) #Out: Control Unit, In:BHW, Store Enable
Dwidth = Signal(modbv(0)[3:]) #Out: Control Unit, In:BHW,Store Enable
PCEN_BHW = Signal(modbv(0)[32:]) #Out:CPR, In:BHW
Reg_OK = Signal(modbv(0)[1:]) #Out:CPR , In:And
#Ignorar por el momento, aqui estaba la bram
#Address = Signal(modbv(0)[5:]) #Out:PC ENABLE, In:BRAM,
#DataInRAM = Signal(modbv(0)[32:]) #Out:r2d , In: BRAM
#WR = Signal(modbv(0)[4:]) #Out: , #In:BRAM, Out:Store Enable
#WE = Signal(False) #Out: , In:BRAM, Out:PC_Enable
#RE = Signal(False) #Out: , In:BRAM, Out:PC_Enable
#Done = Signal(False) #Out:BRAM, In:PCEnable
#DataOutRAM = Signal(modbv(0)[32:]) #Out:Bram, In: Datoinstruccion, In:PC_Enable
Ok_PC = Signal(modbv(0)[1:]) #In:PC, Out:PC_Enable
Opcode = Signal(modbv(0)[7:])
funct7 = Signal(modbv(0)[7:])
funct3 = Signal(modbv(0)[3:])
BHWDIR = Signal(modbv(0)[2:])
#r2d = DataInRAM
@always_comb
def assign():
rd.next = datainstruccion[12:7]
rs2.next = datainstruccion[25:20]
rs1.next = datainstruccion[20:15]
mux1_010.next = datainmediato
Opcode.next = datainstruccion[7:0]
funct7.next = datainstruccion[32:25]
funct3.next = datainstruccion[15:12]
BHWDIR.next = ALUout[2:0]
#Instances
Inm = ConvInst(datainstruccion,
datainmediato) #Conversor instruccion-inmediato
Mux3inst = Mux3(Sel_Mux, 4, datainmediato, mux3_add2) #Multiplexor
Add2inst = ADD(mux3_add2, dirdatos, add2_mux4) #Adder
Mux4inst = Mux4(PCsrc, ALUout, add2_mux4, mux4_PC) #Multiplexor
PCinst = PC(mux4_PC, clk, reset, Ok_PC, dirdatos) #Program Counter
Add4inst = ADD_4(dirdatos, mux1_000) #Add4
Add1inst = ADD(dirdatos, datainmediato, mux1_001) #Adder
Mux1inst = Mux1(RegDest, mux1_000, mux1_001, mux1_010, mux1_011, ALUout,
rdd) #Multiplexor
Mux2inst = Mux2(ALUsrc, DataInRAM, datainmediato, ALUinA) #Multiplexor
ALUinst = ALU(ALUinA, r1d, ALUop, ALUout, ALUflag) #ALU
ControlUnitInst = ControlUnit(Opcode, funct7, funct3, ALUflag, RegWrite,
RegDest, ALUsrc, ALUop, Dwidth, PCsrc,
Sel_Mux) #Control Unit
BHWinst = BHW(Dwidth, BHWDIR, PCEN_BHW, mux1_011) #BHW
StoreEnableinst = StoreEnable(Dwidth, BHWDIR, WR) #Store Enable
#Block Ram
Andinst = AND(RegWrite, Reg_OK, RegEnable) #AND
RegisterFileinst = RegisterFile(clk, reset, RegEnable, rd, rs1, rs2, rdd,
r1d, DataInRAM) #Register File
CPRinst = CPR(clk, reset, DataOutRAM, dirdatos, ALUout, Done,
datainstruccion, Opcode, PCEN_BHW, Reg_OK, Address, WE, RE,
Ok_PC) #Control PC
return instances()