def store_data_cache_block_on_main_mem(self, memory_address,
cache_block_new_state):
block_to_store = DataBlock(0)
block_to_store.copy_data_block(
self.data_cache.get_block_mem_address(memory_address))
self.__cpu_instance.get_main_memory().set_data_block(
memory_address, block_to_store)
self.change_cache_block_state(memory_address, cache_block_new_state)
return block_to_store
def solve_cache_miss(self, m_address):
clock_cycles = 0
# LOCK OTHER CORE CACHE AND DATA BUS
if self.__core_instance.acquire_other_and_data_bus_locks():
# LOCKS ACQUIRED + 2 Other cache +32 Data bus
clock_cycles += CONSULT_OTHER_CACHE_CLOCK_CYCLES + DATA_BUS_OPERATION_CLOCK_CYCLES
if self.__core_instance.get_if_memory_address_on_other_cache(
m_address):
# Memory address is on the other core cache
if self.__core_instance.get_memory_address_state_on_other_cache(
m_address) == StatesEnum.MODIFIED:
# Other core cache block is modified
# Store the other core block and get the new block
data_block_to_insert = DataBlock(0)
data_block_to_insert.copy_data_block(
self.__core_instance.
store_other_core_data_cache_block_on_main_memory(
m_address, StatesEnum.SHARED))
clock_cycles += self.__core_instance.store_block_on_self_cache(
StatesEnum.SHARED, m_address, data_block_to_insert)
return clock_cycles
# Memory address isn't in the other core or isn't modified
# LOCK RELEASED OTHER CORE CACHE
self.__core_instance.release_other_core_cache()
# Only need to load to self cache + 32
main_memory_data_block = self.__core_instance.get_data_block(
m_address)
data_to_insert = DataBlock(0)
data_to_insert.copy_data_block(main_memory_data_block)
clock_cycles += self.__core_instance.store_block_on_self_cache(
StatesEnum.SHARED, m_address, data_to_insert)
return clock_cycles
else:
# Cant get the other core cache
return LOCK_ERROR
def __init__(self, cache_type: int, cpu_instance):
self.__core_id = cache_type
self.__cpu_instance = cpu_instance
# Core execution finished
self.__finished = False
# Thread constructor
Thread.__init__(self)
# Create the data block for initialize the data cache
data_block = DataBlock(0)
# Initialize the cache of the core
if cache_type == 0:
self.data_cache = Data2WACache(data_block)
elif cache_type == 1:
self.data_cache = DataFACache(data_block)
else:
raise TypeError("Unknown Value for cache type.")
# Initialize the instruction cache
instruction = Instruction()
instruction.set_instruction_values([0, 0, 0, 0])
self.instructionCache = InstructionsCache(instruction)
self.hilillo_id = -1
self.register = []
self.PC = 0
self.RL = 0
self.quantum = 0
self.__hilillo_finished = True
self.__cycles = 0
# Initialize the instructions
self.__add = ADD.ADD(self)
self.__addi = ADDI.ADDI(self)
self.__div = DIV.DIV(self)
self.__mul = MUL.MUL(self)
self.__sub = SUB.SUB(self)
self.__jal = JAL.JAL(self)
self.__jalr = JALR.JALR(self)
self.__bne = BNE.BNE(self)
self.__beq = BEQ.BEQ(self)
self.__lw = LW.LW(self)
self.__sw = SW.SW(self)
self.__lr = LR.LR(self)
self.__sc = SC.SC(self)
def initialize_memory(self):
for i in range(0, 24):
self.__data_memory.append(DataBlock(1))