def __init__( s ): # Interface s.req = InValRdyBundle ( GcdUnitReqMsg() ) s.resp = OutValRdyBundle ( Bits(16) ) # Adapters s.req_q = InValRdyQueueAdapter ( s.req ) s.resp_q = OutValRdyQueueAdapter ( s.resp ) # Concurrent block @s.tick_fl def block(): #------------------------------------------------------------------- # TASK 3.2: Comment out the Exception below. # Implement GcdUnitFL code shown on the slides. #------------------------------------------------------------------- raise NotImplementedError( 'GcdUnitMsg has not been implemented yet!\n ' 'Put your implementation code here!' )
def __init__( s ): # Interface s.req = InValRdyBundle ( GcdUnitReqMsg() ) s.resp = OutValRdyBundle ( Bits(16) ) # Adapters s.req_q = InValRdyQueueAdapter ( s.req ) s.resp_q = OutValRdyQueueAdapter ( s.resp ) # Concurrent block @s.tick_fl def block(): # Use adapter to pop value from request queue req_msg = s.req_q.popleft() # Use gcd function from Python's standard library result = gcd( req_msg.a, req_msg.b ) # Use adapter to append result to response queue s.resp_q.append( result )
def __init__(s, GcdUnit, src_msgs, sink_msgs, src_delay, sink_delay, dump_vcd=False, test_verilog=False): # Instantiate models s.src = TestSource(GcdUnitReqMsg(), src_msgs, src_delay) s.gcd = GcdUnit() s.sink = TestSink(Bits(16), sink_msgs, sink_delay) # Dump VCD if dump_vcd: s.gcd.vcd_file = dump_vcd # Translation if test_verilog: s.gcd = TranslationTool(s.gcd, verilator_xinit=test_verilog) # Connect s.connect(s.src.out, s.gcd.req) s.connect(s.gcd.resp, s.sink.in_)
def __init__(s): # Interface s.req = InValRdyBundle(GcdUnitReqMsg()) s.resp = OutValRdyBundle(Bits(16)) # Instantiate datapath and control s.dpath = GcdUnitDpathRTL() s.ctrl = GcdUnitCtrlRTL() # Connect input interface to dpath/ctrl s.connect(s.req.msg.a, s.dpath.req_msg_a) s.connect(s.req.msg.b, s.dpath.req_msg_b) s.connect(s.req.val, s.ctrl.req_val) s.connect(s.req.rdy, s.ctrl.req_rdy) # Connect dpath/ctrl to output interface s.connect(s.dpath.resp_msg, s.resp.msg) s.connect(s.ctrl.resp_val, s.resp.val) s.connect(s.ctrl.resp_rdy, s.resp.rdy) # Connect status/control signals s.connect_auto(s.dpath, s.ctrl)
def __init__(s, GcdUnit, src_msgs, sink_msgs, src_delay, sink_delay, dump_vcd=False, test_verilog=False): # Instantiate models s.src = TestSource(GcdUnitReqMsg(), src_msgs, src_delay) s.gcd = GcdUnit s.sink = TestSink(Bits(16), sink_msgs, sink_delay) # Dump VCD if dump_vcd: s.gcd.vcd_file = dump_vcd # Translation if test_verilog: cls_name = s.gcd.__class__.__name__ if (cls_name != 'SwShim') and (not hasattr(s.gcd, 'dut')): s.gcd = TranslationTool(s.gcd, verilator_xinit=test_verilog) # Connect s.connect(s.src.out, s.gcd.req) s.connect(s.gcd.resp, s.sink.in_)
def __init__( s, src_msgs, sink_msgs ): s.src = TestSource (GcdUnitReqMsg(), src_msgs) s.gcd = GcdUnitFL () s.sink = TestSink (Bits(16), sink_msgs) s.connect( s.src.out, s.gcd.req ) s.connect( s.gcd.resp, s.sink.in_ )
def test_mk_msg(): # Create msg msg = GcdUnitReqMsg().mk_msg(1, 2) # Verify msg assert msg.a == 1 assert msg.b == 2
def test_str(): # Create msg msg = GcdUnitReqMsg() msg.a = 0xdead msg.b = 0xbeef # Verify string assert str(msg) == "dead:beef"
def test_str(): # Create msg msg = GcdUnitReqMsg() msg.a = 0xd msg.b = 0xd # Verify string assert str(msg) == "000d:000d"
def test_fields(): # Create msg msg = GcdUnitReqMsg() msg.a = 1 msg.b = 2 # Verify msg assert msg.a == 1 assert msg.b == 2
def test_fields(): # Create msg print msg = GcdUnitReqMsg() print msg msg.a = 1 print msg msg.b = 2 print msg # Verify msg assert msg.a == 1 assert msg.b == 2
def __init__(s): # Interface s.req = InValRdyBundle(GcdUnitReqMsg()) s.resp = OutValRdyBundle(Bits(16)) # Adapters s.req_q = InValRdyQueueAdapter(s.req) s.resp_q = OutValRdyQueueAdapter(s.resp) # Concurrent block @s.tick_fl def block(): req_msg = s.req_q.popleft() result = gcd(req_msg.a, req_msg.b) s.resp_q.append(result)
def __init__(s): # Interface s.req = InValRdyBundle(GcdUnitReqMsg()) s.resp = OutValRdyBundle(Bits(16)) # Verilog ports s.set_ports({ 'clk': s.clk, 'reset': s.reset, 'req_val': s.req.val, 'req_rdy': s.req.rdy, 'req_msg': s.req.msg, 'resp_val': s.resp.val, 'resp_rdy': s.resp.rdy, 'resp_msg': s.resp.msg, })
def __init__(s): # Interface s.req = InValRdyBundle(GcdUnitReqMsg()) s.resp = OutValRdyBundle(Bits(16)) # Adapters s.req_q = InValRdyQueueAdapter(s.req) s.resp_q = OutValRdyQueueAdapter(s.resp) # Member variables s.result = 0 s.counter = 0 # Concurrent block @s.tick_cl def block(): # Tick the queue adapters s.req_q.xtick() s.resp_q.xtick() # Handle delay to model the gcd unit latency if s.counter > 0: s.counter -= 1 if s.counter == 0: s.resp_q.enq(s.result) # If we have a new message and the output queue is not full elif not s.req_q.empty() and not s.resp_q.full(): req_msg = s.req_q.deq() s.result, s.counter = gcd(req_msg.a, req_msg.b)
def mk_req_msg( a, b ): msg = GcdUnitReqMsg() msg.a = a msg.b = b return msg