def moduleParameterParser(self):
moduleParameterList = []
lineNumber = len(self.VerilogLines)
for index in range(lineNumber):
match = re.search(
r"(?i)parameter\s+([a-zA-Z0-9_$]*)\s*=\s*([^,\n;/)]*)",
self.VerilogLines[index])
if match:
parameter = Parameter(match.group(1))
parameter.setValue(match.group(2))
parameter.setLineIndex(index)
matchComment = re.search(r'\s*//\s*(.*)',
self.VerilogLines[index])
if matchComment:
parameter.setComment(matchComment.group(1))
else:
parameter.setComment("")
moduleParameterList.append(parameter)
self.module.setParametersList(moduleParameterList)
def TBParameterParser(self):
listOfInstances = []
intance = re.findall(
r"((`ifdef|`ifndef)[a-zA-Z0-9_$.,\/\"'`)(\s]*`endif|[a-zA-Z0-9_$]+)\s*#\s*[(]([a-zA-Z0-9_$.,\/\"'`)(\s]*)[)]\s*([a-zA-Z0-9_$]+)",
self.verilogText)
if intance:
for i in range(len(intance)):
if re.search(r"(`ifdef|`ifndef)", intance[i][0]):
moduleName = self.instanceNameCorrection(intance[i][0])
Instance = ModuleInstance(intance[i][3], moduleName)
Instance.setFalseName(intance[i][0])
else:
Instance = ModuleInstance(intance[i][3], intance[i][0])
intanceParameterList = []
# add space at the begin of parameters inside hash to conpensate error for the first parameter
# which need to have a space
textInsideHash = " " + intance[i][2]
#to find all parameter inside the "#"
parametersInsideHash = re.findall(
r"\s*[^\/][.]\s*([a-zA-Z0-9_$]+)\s*[(]\s*([`a-zA-Z0-9_$'\".]+)\s*[)]\s*[,]?[ \/]*([a-zA-Z0-9_$'`\"\/, ]*)",
textInsideHash)
#parsing every parameter line
for parameterLine in parametersInsideHash:
valueFound = False
commentFound = False
#condition to check if the parameter name has ` so we search for define
if re.search(r"[`]", parameterLine[1]):
parameter = re.search(r"[`][ ]*([a-zA-Z0-9_$]*)",
parameterLine[1])
for i in range(len(self.VerilogLines)):
defineMatch = re.search(
r"[`](?i)define[ ]+" + parameter.group(1) +
"[ ]+([a-zA-Z0-9_']+)", self.VerilogLines[i])
if defineMatch:
valueFound = True
param = Parameter(parameterLine[0])
param.setValue(defineMatch.group(1))
param.setLineIndex(i)
matchComment = re.search(
r'\s*//\s*(.*)', self.VerilogLines[i])
if matchComment:
commentFound = True
param.setComment(matchComment.group(1))
break
elif re.search(
r"[.][ ]*" + parameterLine[0] + "[ (]*" +
parameterLine[1], self.VerilogLines[i]):
index = i
else:
for i in range(len(self.VerilogLines)):
parameter = re.search(
r"(?i)parameter\s+" + parameterLine[1] +
"\s*=\s*([^,\n;/)]*)", self.VerilogLines[i])
if parameter:
valueFound = True
param = Parameter(parameterLine[0])
param.setValue(parameter.group(1))
param.setLineIndex(i)
matchComment = re.search(
r'\s*//\s*(.*)', self.VerilogLines[i])
if matchComment:
commentFound = True
param.setComment(matchComment.group(1))
break
elif re.search(
r"[.][ ]*" + parameterLine[0] + "[ (]*" +
parameterLine[1], self.VerilogLines[i]):
index = i
if not valueFound:
if self.includeFile:
valueFound, listOfValues = self.parseIncludeFile(
parameterLine[1])
if not valueFound:
param = Parameter(parameterLine[0])
param.setValue(parameterLine[1])
param.setLineIndex(index)
param.setComment(parameterLine[2])
else:
param = Parameter(parameterLine[0])
param.setValue(listOfValues[0])
param.setLineIndex(listOfValues[1])
param.setComment(listOfValues[2])
param.setInInclude(True)
intanceParameterList.append(param)
Instance.setParametersList(intanceParameterList)
listOfInstances.append(Instance)
self.testBench.setInstanceList(listOfInstances)
