def test_basic( dump_vcd ):
# Elaborate the model
model = RegIncr()
model.vcd_file = dump_vcd
model.elaborate()
# Create and reset simulator
sim = SimulationTool( model )
sim.reset()
print ""
# Helper function
def t( in_, out ):
# Write input value to input port
model.in_.value = in_
# Ensure that all combinational concurrent blocks are called
sim.eval_combinational()
# Display a line trace
sim.print_line_trace()
# If reference output is not '?', verify value read from output port
if ( out != '?' ):
assert model.out == out
# Tick simulator one cycle
sim.cycle()
# ''' TUTORIAL TASK '''''''''''''''''''''''''''''''''''''''''''''''''''''
# This test script is incomplete. As part of the tutorial you will add
# a sequence of test cases to set the input and verify the output of
# the registered incrementer.
# '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
# Cylce-by-cycle tests
t(0x00, '?')
t(0x13, 0x01)
t(0x27, 0x14)
t(0x00, 0x28)
t(0x00, 0x01)
t(0x00, 0x01)
def __init__(self):
self.in_ = InPort(Bits(8))
self.out = OutPort(Bits(8))
self.reg_incr_0 = RegIncr()
self.connect(self.in_, self.reg_incr_0.in_)
self.reg_incr_1 = RegIncr()
self.connect(self.reg_incr_0.out, self.reg_incr_1.in_)
self.connect(self.reg_incr_1.out, self.out)
def test_basic( dump_vcd ):
# Elaborate the model
model = RegIncr()
model.vcd_file = dump_vcd
model.elaborate()
# Create and reset simulator
sim = SimulationTool( model )
sim.reset()
print ""
# Helper function
def t( in_, out ):
# Write input value to input port
model.in_.value = in_
# Ensure that all combinational concurrent blocks are called
sim.eval_combinational()
# Display a line trace
sim.print_line_trace()
# If reference output is not '?', verify value read from output port
if ( out != '?' ):
assert model.out == out
# Tick simulator one cycle
sim.cycle()
# Cycle-by-cycle tests
t( 0x00, '?' )
t( 0x13, 0x01 )
t( 0x27, 0x14 )
t( 0x00, 0x28 )
t( 0x00, 0x01 )
t( 0x00, 0x01 )
def test_large(dump_vcd):
run_test_vector_sim(RegIncr(), [
('in_ out*'),
[0xa0, '?'],
[0xb3, 0xa1],
[0xc6, 0xb4],
[0x00, 0xc7],
], dump_vcd)
def test_small(dump_vcd):
run_test_vector_sim(RegIncr(), [
('in_ out*'),
[0x00, '?'],
[0x03, 0x01],
[0x06, 0x04],
[0x00, 0x07],
], dump_vcd)
def test_peter(dump_vcd):
run_test_vector_sim(RegIncr(), [
('in_ out*'),
[0x00, '?'],
[0x01, 0x01],
[0x02, 0x02],
[0x03, 0x03],
], dump_vcd)
def test_random( dump_vcd ):
test_vector_table = [( 'in_', 'out*' )]
last_result = '?'
for i in xrange(20):
rand_value = Bits( 8, random.randint(0,0xff) )
test_vector_table.append( [ rand_value, last_result ] )
last_result = Bits( 8, rand_value + 1 )
run_test_vector_sim( RegIncr(), test_vector_table, dump_vcd
def test_overflow( dump_vcd ):
run_test_vector_sim( RegIncr(), [
('in_ out*'),
[ 0x00, '?' ],
[ 0xfe, 0x01 ],
[ 0xff, 0xff ],
[ 0x00, 0x00 ],
], dump_vcd )
def __init__(s):
# Port-based interface
s.in_ = InPort(8)
s.out = OutPort(8)
# First stage
s.reg_incr_0 = RegIncr()
# Second stage
s.reg_incr_1 = RegIncr()
s.connect(s.reg_incr_0.out, s.reg_incr_1.in_)
s.connect(s.reg_incr_1.out, s.out)
s.connect(s.in_, s.reg_incr_0.in_)
def test_overflow(dump_vcd):
run_test_vector_sim(RegIncr(), [
('in_ out*'),
[0x00, '?'],
[0x0, 0x0],
[0xFF, 0xFF],
[0xFE, 0x1],
], dump_vcd)
def test_basic(dump_vcd):
# Elaborate the model
model = RegIncr()
model.vcd_file = dump_vcd
model.elaborate()
# Create and reset simulator
sim = SimulationTool(model)
sim.reset()
print ""
# Helper function
def t(in_, out):
# Write input value to input port
model.in_.value = in_
# Ensure that all combinational concurrent blocks are called
sim.eval_combinational()
# Display a line trace
sim.print_line_trace()
# If reference output is not '?', verify value read from output port
if (out != '?'):
assert model.out == out
# Tick simulator one cycle
sim.cycle()
t(0x00, '?')
t(0x13, 0x01)
t(0x27, 0x14)
t(0x00, 0x28)
t(0x00, 0x01)
t(0x00, 0x01)
class RegIncr2stage(Model):
def __init__(self):
self.in_ = InPort(Bits(8))
self.out = OutPort(Bits(8))
self.reg_incr_0 = RegIncr()
self.connect(self.in_, self.reg_incr_0.in_)
self.reg_incr_1 = RegIncr()
self.connect(self.reg_incr_0.out, self.reg_incr_1.in_)
self.connect(self.reg_incr_1.out, self.out)
def line_trace(self):
return "{} ({}) {}".format(
self.in_,
self.reg_incr_0.line_trace(),
self.reg_incr_1.line_trace(),
self.out
)
def test_random(dump_vcd):
input_list = []
for i in range(15):
input_list.append(int(i * 16))
vec_table = []
vec_table.append(('in_', 'out*'))
vec_table.append([input_list[0], '?'])
for i in range(1, 15):
vec_table.append([input_list[i], input_list[i - 1] + 1])
print(vec_table)
run_test_vector_sim(RegIncr(), vec_table, dump_vcd)
def test_basic(dump_vcd):
model = RegIncr()
model.vcd_file = dump_vcd
model.elaborate()
sim = SimulationTool(model)
sim.reset()
def t(in_, out):
model.in_.value = in_
sim.eval_combinational()
sim.print_line_trace()
if out != '?':
assert model.out == out
sim.cycle()
t(0x00, '?')
t(0x13, 0x01)
t(0x27, 0x14)
t(0x00, 0x28)
t(0x00, 0x01)
t(0x00, 0x01)
def __init__(s):
# Port-based interface
s.in_ = InPort(8)
s.out = OutPort(8)
# First stage
s.reg_incr_0 = RegIncr()
s.connect(s.in_, s.reg_incr_0.in_)
# ''' TUTORIAL TASK ''''''''''''''''''''''''''''''''''''''''''''''''''
# This model is incomplete. As part of the tutorial you will insert
# code here to instantiate and then connect the second stage of this
# two-stage registered incrementer.
# ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
s.reg_incr_1 = RegIncr()
s.connect(s.reg_incr_0.out, s.reg_incr_1.in_)
s.connect(s.reg_incr_1.out, s.out)
def __init__(s, nstages=2):
# Port-based interface
s.in_ = InPort(8)
s.out = OutPort(8)
# Instantiate the registered incrementers
s.reg_incrs = [RegIncr() for x in xrange(nstages)]
# Connect input port to first reg_incr in chain
s.connect(s.in_, s.reg_incrs[0].in_)
# Connect reg_incr in chain
for i in xrange(nstages - 1):
s.connect(s.reg_incrs[i].out, s.reg_incrs[i + 1].in_)
# Connect last reg_incr in chain to output port
s.connect(s.reg_incrs[-1].out, s.out)
def __init__( s, nstages=2 ):
# Port-based interface
s.in_ = InPort (8)
s.out = OutPort (8)
# Instantiate the registered incrementers
s.reg_incrs = [ RegIncr() for x in xrange(nstages) ]
# Connect input port to first reg_incr in chain
s.connect( s.in_, s.reg_incrs[0].in_ )
# ''' TUTORIAL TASK ''''''''''''''''''''''''''''''''''''''''''''''''''
# This model is incomplete. As part of the tutorial you will add code
# to connect the stages together.
# ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
# Connect last reg_incr in chain to output port
s.connect( s.reg_incrs[-1].out, s.out )
#!/usr/bin/python
# -*- coding:utf-8 -*-
from pymtl import *
from sys import argv
from RegIncr import RegIncr
input_values = [int(x, 0) for x in argv[1:]]
input_values.extend([0] * 3)
model = RegIncr()
model.vcd_file = "regincr-sim.vcd"
model.elaborate()
sim = SimulationTool(model)
sim.reset()
for input_value in input_values:
# Write input value to input port
model.in_.value = input_value
# Display input and output ports
sim.print_line_trace()
# Tick simulator one cycle
sim.cycle()
def test_random(n, dump_vcd):
run_test_vector_sim(RegIncr(bitwidth=n),
mk_test_vector_table(n, sample(range(2**n),2) ), dump_vcd)
from pymtl import * from sys import argv from RegIncr import RegIncr # Get list of input values from command line input_values = [ int(x,0) for x in argv[1:] ] # Add three zero values to end of list of input values input_values.extend( [0]*3 ) # Elaborate the model model = RegIncr() model.elaborate() # Create and reset simulator sim = SimulationTool( model ) sim.reset() # Apply input values and display output values for input_value in input_values: # Write input value to input port model.in_.value = input_value
from pymtl import * from sys import argv from RegIncr import RegIncr # Get list of input values from command line input_values = [int(x, 0) for x in argv[1:]] # Add three zero values to end of list of input values input_values.extend([0] * 3) # Elaborate the model model = RegIncr() model.vcd_file = "regincr-sim.vcd" model.elaborate() # Create a simulator using simulation tool sim = SimulationTool(model) # Reset simulator sim.reset() # Apply input values and display output values for input_value in input_values:
