def test_simple( dtype, test_verilog ):
# instantiate the model and elaborate it
model = RegIncr( dtype )
#---------------------------------------------------------------------
# TASK 5: Add verilog translation to the test harness here
#---------------------------------------------------------------------
model.elaborate()
# create the simulator
sim = SimulationTool( model )
# verify the model
print
for input_vector, expected_out in simple_test_vectors:
model.in_.value = input_vector
sim.print_line_trace()
sim.cycle()
assert model.out == expected_out
sim.print_line_trace()
def test_simple(dtype, test_verilog):
# instantiate the model and elaborate it
model = RegIncr(dtype)
#---------------------------------------------------------------------
# TASK 2.5: Add verilog translation to the test harness here
#---------------------------------------------------------------------
model.elaborate()
# create the simulator
sim = SimulationTool(model)
# verify the model
print
for input_vector, expected_out in simple_test_vectors:
model.in_.value = input_vector
sim.print_line_trace()
sim.cycle()
assert model.out == expected_out
sim.print_line_trace()
def test_simple(dtype, test_verilog):
# instantiate the model and elaborate it
model = RegIncr(dtype)
if test_verilog: # add these two lines to
model = TranslationTool(model) # enable testing translation
model.elaborate()
# create the simulator
sim = SimulationTool(model)
# verify the model
print
for input_vector, expected_out in simple_test_vectors:
model.in_.value = input_vector
sim.print_line_trace()
sim.cycle()
assert model.out == expected_out
sim.print_line_trace()
def test_simple(dtype, test_verilog):
# instantiate the model and elaborate it
model = RegIncr(dtype)
if test_verilog: # add these two lines to
model = TranslationTool(model) # enable testing translation
model.elaborate()
# create the simulator
sim = SimulationTool(model)
# verify the model
print
for input_vector, expected_out in simple_test_vectors:
model.in_.value = input_vector
sim.print_line_trace()
sim.cycle()
assert model.out == expected_out
sim.print_line_trace()
