env.BoardConfig().get('build.type', 'hx'),
env.BoardConfig().get('build.size', '1k'),
env.BoardConfig().get('build.pack', 'tq144'), CHIPDB_PATH),
suffix='.rpt',
src_suffix='.asc')
env.Append(BUILDERS={
'Synth': synth,
'PnR': pnr,
'Bin': bitstream,
'Time': time_rpt
})
blif = env.Synth(TARGET, [src_synth])
asc = env.PnR(TARGET, [blif, PCF])
binf = env.Bin(TARGET, asc)
#
# Target: Time analysis (.rpt)
#
rpt = env.Time(asc)
target_time = env.Alias('time', rpt)
AlwaysBuild(target_time)
#
# Target: Upload bitstream
#
target_upload = env.Alias('upload', binf, '$UPLOADBINCMD')
AlwaysBuild(target_upload)
src_suffix='.json')
#
# Builder: ecppack (.config --> .bit)
#
bitstream = Builder(action='ecppack --db {0} {1} $SOURCE $TARGET'.format(
DATABASE_PATH, '--idcode ' + env.BoardConfig().get('build.idcode', '')
if env.BoardConfig().get('build.idcode', '') else ''),
suffix='.bit',
src_suffix='.config')
env.Append(BUILDERS={'Synth': synth, 'PnR': pnr, 'Bin': bitstream})
blif = env.Synth(TARGET, [src_synth])
config = env.PnR(TARGET, [blif, LPF])
bit = env.Bin(TARGET, config)
#
# Target: Upload bitstream
#
target_upload = env.Alias('upload', bit, '$UPLOADBINCMD')
AlwaysBuild(target_upload)
#
# Builders: Icarus Verilog
#
iverilog = Builder(
action='iverilog {0} -o $TARGET -D VCD_OUTPUT={1} {2} $SOURCES'.format(
IVER_PATH, TARGET_SIM + '.vcd' if TARGET_SIM else '', VLIB_FILES),
suffix='.out',
src_suffix='.v')
