class VExpress_EMM(RealView):
mem_start_addr = '2GB'
max_mem_size = '2GB'
pci_cfg_base = 0x30000000
uart = Pl011(pio_addr=0x1c090000, int_num=37)
realview_io = RealViewCtrl(proc_id0=0x14000000,
proc_id1=0x14000000,
pio_addr=0x1C010000)
gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
local_cpu_timer = CpuLocalTimer(int_num_timer=29,
int_num_watchdog=30,
pio_addr=0x2C080000)
timer0 = Sp804(int_num0=34,
int_num1=34,
pio_addr=0x1C110000,
clock0='1MHz',
clock1='1MHz')
timer1 = Sp804(int_num0=35,
int_num1=35,
pio_addr=0x1C120000,
clock0='1MHz',
clock1='1MHz')
clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117)
kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
cf_ctrl = IdeController(disks=[],
pci_func=0,
pci_dev=0,
pci_bus=2,
io_shift=2,
ctrl_offset=2,
Command=0x1,
BAR0=0x1C1A0000,
BAR0Size='256B',
BAR1=0x1C1A0100,
BAR1Size='4096B',
BAR0LegacyIO=True,
BAR1LegacyIO=True)
pciconfig = PciConfigAll(size='256MB')
ethernet = IGbE_e1000(pci_bus=0,
pci_dev=0,
pci_func=0,
InterruptLine=1,
InterruptPin=1)
ide = IdeController(disks=[],
pci_bus=0,
pci_dev=1,
pci_func=0,
InterruptLine=2,
InterruptPin=2)
vram = SimpleMemory(range=AddrRange(0x18000000, size='32MB'), zero=True)
rtc = PL031(pio_addr=0x1C170000, int_num=36)
l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
aaci_fake = AmbaFake(pio_addr=0x1C040000)
lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
mmc_fake = AmbaFake(pio_addr=0x1c050000)
def setupBootLoader(self, mem_bus, cur_sys, loc):
self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), zero=True)
self.nvmem.port = mem_bus.master
cur_sys.boot_loader = loc('boot_emm.arm')
cur_sys.atags_addr = 0x80000100
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.master
self.local_cpu_timer.pio = bus.master
self.hdlcd.dma = bus.slave
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, a9scu)
bridge.ranges = [
AddrRange(0x2F000000, size='16MB'),
AddrRange(0x2B000000, size='4MB'),
AddrRange(0x30000000, size='256MB'),
AddrRange(0x40000000, size='512MB'),
AddrRange(0x18000000, size='64MB'),
AddrRange(0x1C000000, size='64MB')
]
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.uart.pio = bus.master
self.realview_io.pio = bus.master
self.timer0.pio = bus.master
self.timer1.pio = bus.master
self.clcd.pio = bus.master
self.clcd.dma = bus.slave
self.hdlcd.pio = bus.master
self.kmi0.pio = bus.master
self.kmi1.pio = bus.master
self.cf_ctrl.pio = bus.master
self.cf_ctrl.dma = bus.slave
self.cf_ctrl.config = bus.master
self.rtc.pio = bus.master
bus.use_default_range = True
self.vram.port = bus.master
self.ide.pio = bus.master
self.ide.config = bus.master
self.ide.dma = bus.slave
self.ethernet.pio = bus.master
self.ethernet.config = bus.master
self.ethernet.dma = bus.slave
self.pciconfig.pio = bus.default
self.l2x0_fake.pio = bus.master
self.uart1_fake.pio = bus.master
self.uart2_fake.pio = bus.master
self.uart3_fake.pio = bus.master
self.sp810_fake.pio = bus.master
self.watchdog_fake.pio = bus.master
self.aaci_fake.pio = bus.master
self.lan_fake.pio = bus.master
self.usb_fake.pio = bus.master
self.mmc_fake.pio = bus.master
def setupBootLoader(self, mem_bus, cur_sys, loc):
self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), zero=True)
self.nvmem.port = mem_bus.master
cur_sys.boot_loader = loc('boot_emm.arm')
cur_sys.atags_addr = 0x80000100
def setupBootLoader(self, mem_bus, cur_sys, loc):
self.nvmem = SimpleMemory(range=AddrRange(Addr('2GB'), size='64MB'),
zero=True)
self.nvmem.port = mem_bus.master
cur_sys.boot_loader = loc('boot.arm')
class VExpress_EMM(RealView):
_mem_regions = [(Addr('2GB'), Addr('2GB'))]
pci_cfg_base = 0x30000000
uart = Pl011(pio_addr=0x1c090000, int_num=37)
realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \
idreg=0x02250000, pio_addr=0x1C010000)
gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
local_cpu_timer = CpuLocalTimer(int_num_timer=29,
int_num_watchdog=30,
pio_addr=0x2C080000)
generic_timer = GenericTimer(int_num=29)
timer0 = Sp804(int_num0=34,
int_num1=34,
pio_addr=0x1C110000,
clock0='1MHz',
clock1='1MHz')
timer1 = Sp804(int_num0=35,
int_num1=35,
pio_addr=0x1C120000,
clock0='1MHz',
clock1='1MHz')
clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117)
kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
cf_ctrl = IdeController(disks=[],
pci_func=0,
pci_dev=0,
pci_bus=2,
io_shift=2,
ctrl_offset=2,
Command=0x1,
BAR0=0x1C1A0000,
BAR0Size='256B',
BAR1=0x1C1A0100,
BAR1Size='4096B',
BAR0LegacyIO=True,
BAR1LegacyIO=True)
pciconfig = PciConfigAll(size='256MB')
vram = SimpleMemory(range=AddrRange(0x18000000, size='32MB'),
conf_table_reported=False)
rtc = PL031(pio_addr=0x1C170000, int_num=36)
l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
aaci_fake = AmbaFake(pio_addr=0x1C040000)
lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
mmc_fake = AmbaFake(pio_addr=0x1c050000)
energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
# Attach any PCI devices that are supported
def attachPciDevices(self):
self.ethernet = IGbE_e1000(pci_bus=0,
pci_dev=0,
pci_func=0,
InterruptLine=1,
InterruptPin=1)
self.ide = IdeController(disks=[],
pci_bus=0,
pci_dev=1,
pci_func=0,
InterruptLine=2,
InterruptPin=2)
def enableMSIX(self):
self.gic = Pl390(dist_addr=0x2C001000,
cpu_addr=0x2C002000,
it_lines=512)
self.gicv2m = Gicv2m()
self.gicv2m.frames = [
Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)
]
def setupBootLoader(self, mem_bus, cur_sys, loc):
self.nvmem = SimpleMemory(range=AddrRange('64MB'),
conf_table_reported=False)
self.nvmem.port = mem_bus.master
cur_sys.boot_loader = loc('boot_emm.arm')
cur_sys.atags_addr = 0x8000000
cur_sys.load_addr_mask = 0xfffffff
cur_sys.load_offset = 0x80000000
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.master
self.local_cpu_timer.pio = bus.master
if hasattr(self, "gicv2m"):
self.gicv2m.pio = bus.master
self.hdlcd.dma = bus.slave
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, a9scu)
bridge.ranges = [
AddrRange(0x2F000000, size='16MB'),
AddrRange(0x2B000000, size='4MB'),
AddrRange(0x30000000, size='256MB'),
AddrRange(0x40000000, size='512MB'),
AddrRange(0x18000000, size='64MB'),
AddrRange(0x1C000000, size='64MB')
]
self.vgic.pio = bus.master
# Set the clock domain for IO objects that are considered
# to be "close" to the cores.
def onChipIOClkDomain(self, clkdomain):
self.gic.clk_domain = clkdomain
if hasattr(self, "gicv2m"):
self.gicv2m.clk_domain = clkdomain
self.hdlcd.clk_domain = clkdomain
self.vgic.clk_domain = clkdomain
# Attach I/O devices to specified bus object. Done here
# as the specified bus to connect to may not always be fixed.
def attachIO(self, bus):
self.uart.pio = bus.master
self.realview_io.pio = bus.master
self.timer0.pio = bus.master
self.timer1.pio = bus.master
self.clcd.pio = bus.master
self.clcd.dma = bus.slave
self.hdlcd.pio = bus.master
self.kmi0.pio = bus.master
self.kmi1.pio = bus.master
self.cf_ctrl.pio = bus.master
self.cf_ctrl.dma = bus.slave
self.cf_ctrl.config = bus.master
self.rtc.pio = bus.master
bus.use_default_range = True
self.vram.port = bus.master
self.pciconfig.pio = bus.default
self.l2x0_fake.pio = bus.master
self.uart1_fake.pio = bus.master
self.uart2_fake.pio = bus.master
self.uart3_fake.pio = bus.master
self.sp810_fake.pio = bus.master
self.watchdog_fake.pio = bus.master
self.aaci_fake.pio = bus.master
self.lan_fake.pio = bus.master
self.usb_fake.pio = bus.master
self.mmc_fake.pio = bus.master
self.energy_ctrl.pio = bus.master
# Try to attach the I/O if it exists
try:
self.ide.pio = bus.master
self.ide.config = bus.master
self.ide.dma = bus.slave
self.ethernet.pio = bus.master
self.ethernet.config = bus.master
self.ethernet.dma = bus.slave
except:
pass
# Set the clock domain for IO objects that are considered
# to be "far" away from the cores.
def offChipIOClkDomain(self, clkdomain):
self.uart.clk_domain = clkdomain
self.realview_io.clk_domain = clkdomain
self.timer0.clk_domain = clkdomain
self.timer1.clk_domain = clkdomain
self.clcd.clk_domain = clkdomain
self.kmi0.clk_domain = clkdomain
self.kmi1.clk_domain = clkdomain
self.cf_ctrl.clk_domain = clkdomain
self.rtc.clk_domain = clkdomain
self.vram.clk_domain = clkdomain
self.pciconfig.clk_domain = clkdomain
self.l2x0_fake.clk_domain = clkdomain
self.uart1_fake.clk_domain = clkdomain
self.uart2_fake.clk_domain = clkdomain
self.uart3_fake.clk_domain = clkdomain
self.sp810_fake.clk_domain = clkdomain
self.watchdog_fake.clk_domain = clkdomain
self.aaci_fake.clk_domain = clkdomain
self.lan_fake.clk_domain = clkdomain
self.usb_fake.clk_domain = clkdomain
self.mmc_fake.clk_domain = clkdomain
self.energy_ctrl.clk_domain = clkdomain
class VExpress_EMM(RealView):
_mem_regions = [(Addr('2GB'), Addr('2GB'))]
# Ranges based on excluding what is part of on-chip I/O (gic,
# a9scu)
_off_chip_ranges = [AddrRange(0x2F000000, size='16MB'),
AddrRange(0x30000000, size='256MB'),
AddrRange(0x40000000, size='512MB'),
AddrRange(0x18000000, size='64MB'),
AddrRange(0x1C000000, size='64MB')]
# Platform control device (off-chip)
realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
idreg=0x02250000, pio_addr=0x1C010000)
mcc = VExpressMCC()
dcc = CoreTile2A15DCC()
### On-chip devices ###
gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
pio_addr=0x2C080000)
hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
pio_addr=0x2b000000, int_num=117,
workaround_swap_rb=True)
def _on_chip_devices(self):
devices = [
self.gic, self.vgic,
self.local_cpu_timer
]
if hasattr(self, "gicv2m"):
devices.append(self.gicv2m)
devices.append(self.hdlcd)
return devices
### Off-chip devices ###
uart = Pl011(pio_addr=0x1c090000, int_num=37)
pci_host = GenericPciHost(
conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
pci_pio_base=0)
generic_timer = GenericTimer(int_phys=29, int_virt=27)
timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard())
kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit())
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
io_shift = 2, ctrl_offset = 2, Command = 0x1,
BAR0 = 0x1C1A0000, BAR0Size = '256B',
BAR1 = 0x1C1A0100, BAR1Size = '4096B',
BAR0LegacyIO = True, BAR1LegacyIO = True)
vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
conf_table_reported = False)
rtc = PL031(pio_addr=0x1C170000, int_num=36)
l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
aaci_fake = AmbaFake(pio_addr=0x1C040000)
lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
mmc_fake = AmbaFake(pio_addr=0x1c050000)
energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
def _off_chip_devices(self):
devices = [
self.uart,
self.realview_io,
self.pci_host,
self.timer0,
self.timer1,
self.clcd,
self.kmi0,
self.kmi1,
self.cf_ctrl,
self.rtc,
self.vram,
self.l2x0_fake,
self.uart1_fake,
self.uart2_fake,
self.uart3_fake,
self.sp810_fake,
self.watchdog_fake,
self.aaci_fake,
self.lan_fake,
self.usb_fake,
self.mmc_fake,
self.energy_ctrl,
]
# Try to attach the I/O if it exists
if hasattr(self, "ide"):
devices.append(self.ide)
if hasattr(self, "ethernet"):
devices.append(self.ethernet)
return devices
# Attach any PCI devices that are supported
def attachPciDevices(self):
self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
InterruptLine=1, InterruptPin=1)
self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
InterruptLine=2, InterruptPin=2)
def enableMSIX(self):
self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
self.gicv2m = Gicv2m()
self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
def setupBootLoader(self, mem_bus, cur_sys, loc):
cur_sys.bootmem = SimpleMemory(range = AddrRange('64MB'),
conf_table_reported = False)
if mem_bus is not None:
cur_sys.bootmem.port = mem_bus.master
if not cur_sys.boot_loader:
cur_sys.boot_loader = loc('boot_emm.arm')
cur_sys.atags_addr = 0x8000000
cur_sys.load_offset = 0x80000000
def setupBootLoader(self, mem_bus, cur_sys, loc):
self.nvmem = SimpleMemory(range = AddrRange('64MB'),
conf_table_reported = False)
self.nvmem.port = mem_bus.master
cur_sys.boot_loader = loc('boot_emm.arm')
cur_sys.atags_addr = 0x80000100
def setupBootLoader(self, mem_bus, cur_sys, loc):
self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
conf_table_reported = False)
self.nvmem.port = mem_bus.master
cur_sys.boot_loader = loc('boot.arm')