def _testbench(): rb = RamBus(memory_size=MEM_SIZE >> 2) dut = Memory(clka_i=rb.clka, rsta_i=False, imem=rb.imem_intercon, clkb_i=rb.clkb, rstb_i=False, dmem=rb.dmem_intercon, SIZE=MEM_SIZE, HEX=MEM_TEST_FILE, BYTES_X_LINE=BYTES_X_LINE) tb_clk = rb.gen_clocks() with open(MEM_TEST_FILE) as f: words_x_line = BYTES_X_LINE >> 2 lines_f = [line.strip() for line in f] lines = [ line[8 * i:8 * (i + 1)] for line in lines_f for i in range(words_x_line - 1, -1, -1) ] @instance def timeout(): yield delay(1000000) raise Error("Test failed: Timeout") @instance def stimulus(): # Testing the file loading for addr in range(rb.depth): # Address in words yield rb.read(addr << 2) # Address in bytes data = int(lines[addr], 16) assert rb.dmem.dat_i == data, "Data loading: Data mismatch! Addr = {0:#x}: {1} != {2:#x}".format( addr << 2, hex(rb.dmem.dat_i), data) # Testing R/W for addr in range(rb.depth): data = random.randint(0, 2**32) yield rb.write(addr << 2, data) for addr in range(rb.depth): # Address in words yield rb.read(addr << 2) # Address in bytes assert rb.dmem.dat_i == rb.mirror_mem[ addr], "R/W: Data mismatch! Addr = {0:#x}".format(addr << 2) raise StopSimulation return dut, tb_clk, stimulus, timeout
def _testbench(): rb = RamBus(memory_size=MEM_SIZE >> 2) dut = Memory(clka_i=rb.clka, rsta_i=False, imem=rb.imem_intercon, clkb_i=rb.clkb, rstb_i=False, dmem=rb.dmem_intercon, SIZE=MEM_SIZE, HEX=MEM_TEST_FILE, BYTES_X_LINE=BYTES_X_LINE) tb_clk = rb.gen_clocks() with open(MEM_TEST_FILE) as f: words_x_line = BYTES_X_LINE >> 2 lines_f = [line.strip() for line in f] lines = [line[8 * i:8 * (i + 1)] for line in lines_f for i in range(words_x_line - 1, -1, -1)] @instance def timeout(): yield delay(1000000) raise Error("Test failed: Timeout") @instance def stimulus(): # Testing the file loading for addr in range(rb.depth): # Address in words yield rb.read(addr << 2) # Address in bytes data = int(lines[addr], 16) assert rb.dmem.dat_i == data, "Data loading: Data mismatch! Addr = {0:#x}: {1} != {2:#x}".format(addr << 2, hex(rb.dmem.dat_i), data) # Testing R/W for addr in range(rb.depth): data = random.randint(0, 2**32) yield rb.write(addr << 2, data) for addr in range(rb.depth): # Address in words yield rb.read(addr << 2) # Address in bytes assert rb.dmem.dat_i == rb.mirror_mem[addr], "R/W: Data mismatch! Addr = {0:#x}".format(addr << 2) raise StopSimulation return dut, tb_clk, stimulus, timeout
def _testbench(): rb = RamBus(memory_size=MEM_SIZE >> 2) cpu = WishboneIntercon() dmem = WishboneIntercon() invalidate = Signal(False) dut = ICache( clk_i=rb.clkb, # noqa rst_i=False, cpu=rb.dmem_intercon, mem=dmem, invalidate=invalidate, D_WIDTH=32, BLOCK_WIDTH=3, SET_WIDTH=5, WAYS=4, LIMIT_WIDTH=32) mem = Memory( clka_i=rb.clka, # noqa rsta_i=False, imem=rb.imem_intercon, clkb_i=rb.clkb, rstb_i=False, dmem=dmem, SIZE=MEM_SIZE, HEX=MEM_TEST_FILE, BYTES_X_LINE=BYTES_X_LINE) tb_clk = rb.gen_clocks() # noqa # Load the test file. Used as reference. with open(MEM_TEST_FILE) as f: words_x_line = BYTES_X_LINE >> 2 lines_f = [line.strip() for line in f] lines = [ line[8 * i:8 * (i + 1)] for line in lines_f for i in range(words_x_line - 1, -1, -1) ] @instance def timeout(): # Avoid waiting until armageddon yield delay(100000) raise Error("Test failed: Timeout") @always_comb def port_assign(): # This assignments are for the purpose of being able to watch this # signal GTKWave. cpu.addr.next = rb.dmem_intercon.addr cpu.dat_o.next = rb.dmem_intercon.dat_o cpu.dat_i.next = rb.dmem_intercon.dat_i cpu.sel.next = rb.dmem_intercon.sel cpu.cyc.next = rb.dmem_intercon.cyc cpu.we.next = rb.dmem_intercon.we cpu.stb.next = rb.dmem_intercon.stb cpu.ack.next = rb.dmem_intercon.ack cpu.err.next = rb.dmem_intercon.err @instance def stimulus(): # rb.rst.next = True # yield delay(10) # rb.rst.next = False # Read data from memory: first round for addr in range(rb.depth >> 5): # Address in words yield rb.read(addr << 2) # Address in bytes data = int(lines[addr], 16) assert rb.dmem.dat_i == data, "Data loading (1): Data mismatch! Addr = {0:#x}: {1} != {2:#x}".format( addr << 2, hex(rb.dmem.dat_i), data) invalidate.next = True yield delay(10) invalidate.next = False # Read data from memory: second round. # This time, depending in the cache configuration, should # make each access a hit (big cache) for addr in range(rb.depth >> 5): # Address in words yield rb.read(addr << 2) # Address in bytes data = int(lines[addr], 16) assert rb.dmem.dat_i == data, "Data loading (2): Data mismatch! Addr = {0:#x}: {1} != {2:#x}".format( addr << 2, hex(rb.dmem.dat_i), data) raise StopSimulation return instances()
def _testbench(): rb = RamBus(memory_size=MEM_SIZE >> 2) cpu = WishboneIntercon() dmem = WishboneIntercon() invalidate = Signal(False) dut = ICache(clk_i=rb.clkb, # noqa rst_i=False, cpu=rb.dmem_intercon, mem=dmem, invalidate=invalidate, D_WIDTH=32, BLOCK_WIDTH=3, SET_WIDTH=5, WAYS=4, LIMIT_WIDTH=32) mem = Memory(clka_i=rb.clka, # noqa rsta_i=False, imem=rb.imem_intercon, clkb_i=rb.clkb, rstb_i=False, dmem=dmem, SIZE=MEM_SIZE, HEX=MEM_TEST_FILE, BYTES_X_LINE=BYTES_X_LINE) tb_clk = rb.gen_clocks() # noqa # Load the test file. Used as reference. with open(MEM_TEST_FILE) as f: words_x_line = BYTES_X_LINE >> 2 lines_f = [line.strip() for line in f] lines = [line[8 * i:8 * (i + 1)] for line in lines_f for i in range(words_x_line - 1, -1, -1)] @instance def timeout(): # Avoid waiting until armageddon yield delay(100000) raise Error("Test failed: Timeout") @always_comb def port_assign(): # This assignments are for the purpose of being able to watch this # signal GTKWave. cpu.addr.next = rb.dmem_intercon.addr cpu.dat_o.next = rb.dmem_intercon.dat_o cpu.dat_i.next = rb.dmem_intercon.dat_i cpu.sel.next = rb.dmem_intercon.sel cpu.cyc.next = rb.dmem_intercon.cyc cpu.we.next = rb.dmem_intercon.we cpu.stb.next = rb.dmem_intercon.stb cpu.ack.next = rb.dmem_intercon.ack cpu.err.next = rb.dmem_intercon.err @instance def stimulus(): # rb.rst.next = True # yield delay(10) # rb.rst.next = False # Read data from memory: first round for addr in range(rb.depth >> 5): # Address in words yield rb.read(addr << 2) # Address in bytes data = int(lines[addr], 16) assert rb.dmem.dat_i == data, "Data loading (1): Data mismatch! Addr = {0:#x}: {1} != {2:#x}".format(addr << 2, hex(rb.dmem.dat_i), data) invalidate.next = True yield delay(10) invalidate.next = False # Read data from memory: second round. # This time, depending in the cache configuration, should # make each access a hit (big cache) for addr in range(rb.depth >> 5): # Address in words yield rb.read(addr << 2) # Address in bytes data = int(lines[addr], 16) assert rb.dmem.dat_i == data, "Data loading (2): Data mismatch! Addr = {0:#x}: {1} != {2:#x}".format(addr << 2, hex(rb.dmem.dat_i), data) raise StopSimulation return instances()