示例#1
0
def writeClock(freq_mult, divisor):
	i2c = busio.I2C(board.SCL, board.SDA)
 
	# Initialize SI5351.
	si5351 = adafruit_si5351.SI5351(i2c)

	si5351.pll_a.configure_integer(freq_mult) 
	print('PLL A frequency: {0}mhz'.format(si5351.pll_a.frequency/1000000))
	 
	
	# si5351.pll_b.configure_fractional(24, 2, 3)  # Multiply 25mhz by 24.667 (24 2/3)
	# print('PLL B frequency: {0}mhz'.format(si5351.pll_b.frequency/1000000))
	 
	
	si5351.clock_0.configure_integer(si5351.pll_a, divisor)
	print('Clock 0: {0}mhz'.format(si5351.clock_0.frequency/1000000))
	 

	# si5351.clock_1.configure_fractional(si5351.pll_b, 45, 1, 2) # Divide by 45.5 (45 1/2)
	# print('Clock 1: {0}mhz'.format(si5351.clock_1.frequency/1000000))
	 
	
	# si5351.clock_2.configure_integer(si5351.pll_b, 900)

	# si5351.clock_2.r_divider = adafruit_si5351.R_DIV_64
	# print('Clock 2: {0}khz'.format(si5351.clock_2.frequency/1000))
	 
	# After configuring PLLs and clocks, enable the outputs.
	si5351.outputs_enabled = True
#  - PLL B at 616.66667mhz
#  - Clock 0 at 112.5mhz, using PLL A as a source divided by 8
#  - Clock 1 at 13.553115mhz, using PLL B as a source divided by 45.5
#  - Clock 2 at 10.76khz, using PLL B as a source divided by 900 and further
#    divided with an R divider of 64.
import board
import busio

import adafruit_si5351


# Initialize I2C bus.
i2c = busio.I2C(board.SCL, board.SDA)

# Initialize SI5351.
si5351 = adafruit_si5351.SI5351(i2c)
# Alternatively you can specify the I2C address if it has been changed:
# si5351 = adafruit_si5351.SI5351(i2c, address=0x61)

# Now configue the PLLs and clock outputs.
# The PLLs can be configured with a multiplier and division of the on-board
# 25mhz reference crystal.  For example configure PLL A to 900mhz by multiplying
# by 36.  This uses an integer multiplier which is more accurate over time
# but allows less of a range of frequencies compared to a fractional
# multiplier shown next.
si5351.pll_a.configure_integer(36)  # Multiply 25mhz by 36
print("PLL A frequency: {0}mhz".format(si5351.pll_a.frequency / 1000000))

# And next configure PLL B to 616.6667mhz by multiplying 25mhz by 24.667 using
# the fractional multiplier configuration.  Notice you specify the integer
# multiplier and then a numerator and denominator as separate values, i.e.