def calibrate_adc(self):
"""
Calibrate the ADC associated with this engine, using the adc5g.calibrate_mmcm_phase method.
"""
# The phase switches must be off for calibration
self.phase_switch_enable(0)
self._logger.info('Calibrating ADC link')
adc.calibrate_all_delays(self.roachhost,self.adc,snaps=[self.expand_name('snapshot_adc')])
# Set back to user-defined defaults
self.phase_switch_enable(self.phase_switch)
def calibrate_adc(self):
"""
Calibrate the ADC associated with this engine, using the adc5g.calibrate_mmcm_phase method.
"""
# The phase switches must be off for calibration
self.phase_switch_enable(0)
self._logger.info('Calibrating ADC link')
adc.calibrate_all_delays(self.roachhost,
self.adc,
snaps=[self.expand_name('snapshot_adc')])
# Set back to user-defined defaults
self.phase_switch_enable(self.phase_switch)
def setUpClass(cls):
TestBase.setUpClass()
adc5g.set_test_mode(cls._roach, 0)
adc5g.set_test_mode(cls._roach, 1)
#adc5g.set_test_mode(cls._roach,1)
print "\nSETTING SYN"
#adc5g.sync_adc(self._roach)
# cls._optimal_phase, cls._glitches = adc5g.calibrate_mmcm_phase(
#cls._roach, cls._zdok_n, ['scope_raw_%d_snap_bram' % cls._zdok_n])
# cls._roach, cls._zdok_n, ['snap'])
#BOFFILE = 'adc5g_test.bof'
BOFFILE = 'adcethvfullv64zdk1_2015_Oct_09_1201.bof' #'adcethvfullv64_2015_Sep_09_0946.bof' #'adcethvfullv61_2015_Sep_02_1653.bof' #'adc5g_test_2014_Jul_21_2138.bof'#1649.bof' #'adc5g_test_rev2.bof'
ROACH = '192.168.100.182' #182 or 2
#ROACH = '10.0.1.213'
SNAPNAME = 'snap' #'scope_raw_0_snap'
def br(x):
return np.binary_repr(x, width=8)
r = corr.katcp_wrapper.FpgaClient(ROACH)
time.sleep(0.1)
#r.progdev(BOFFILE)
adc5g.set_test_mode(r, 0, counter=False)
adc5g.sync_adc(r)
adc5g.calibrate_all_delays(r, 0, snaps=[SNAPNAME], verbosity=5)
# adc5g.calibrate_mmcm_phase(r, 0, [SNAPNAME])
#adc5g.calibrate_mmcm_phase(r, 0, ['snap'])
adc5g.unset_test_mode(r, 0)
#a, b, c, d = adc5g.get_test_vector(r, ['snap'])
a, b, c, d = adc5g.get_test_vector(r, [SNAPNAME])
#x = adc5g.get_snapshot(r, 'scope_raw_0_snap')
#a = x[0::4]
#b = x[1::4]
#c = x[2::4]
#d = x[3::4]
for i in range(32):
print br(a[i]), br(b[i]), br(c[i]), br(d[i])
# for cn, core in enumerate([a,b,c,d]):
# pylab.plot(np.array(core) & 0xf, label='%d'%cn)
# pylab.legend()
#pylab.show()
# adc5g.unset_test_mode(roach, 0)
# adc5g.unset_test_mode(roach, 1)
# time.sleep(4)
print "\ntest finished"
time.sleep(0.5)
print 'Estimating clock speed...'
clk_est = r.est_brd_clk()
print 'Clock speed is %d MHz' % clk_est
if opts.clockrate is None:
clkrate = clk_est * 16
else:
clkrate = opts.clockrate
freq_axis = gen_freq_scale(clkrate, 2048)
if opts.prog_fpga:
print 'Calibrating ADCs'
adc.calibrate_all_delays(r,
0,
snaps=['snapshot_adc0'],
verbosity=opts.verbosity)
adc.calibrate_all_delays(r,
1,
snaps=['snapshot_adc1'],
verbosity=opts.verbosity)
#adc.sync_adc(r)
print 'Setting accumulation length to %d' % opts.acc_len
r.write_int('acc_len', opts.acc_len)
#print 'Setting fft-shift to %s'%opts.fft_shift
#r.write_int('fft_shift0',int(opts.fft_shift,2))
#r.write_int('fft_shift1',int(opts.fft_shift,2))
fft_shift = -1
print 'Setting fft-shift to %s' % fft_shift
time.sleep(0.5)
print 'Estimating clock speed...'
fpga_clk_est = r.est_brd_clk()
print 'Clock speed is %d MHz'%fpga_clk_est
if opts.clockrate is None:
clkrate = fpga_clk_est*16 #This is the ADC rate
else:
clkrate = opts.clockrate
print 'ADC sample rate is %d MHz'%clkrate
freq_axis = gen_freq_scale(clkrate,N_CHANS)
if opts.prog_fpga:
print 'Calibrating ADCs'
adc.calibrate_all_delays(r,0,snaps=['snapshot_adc0'],verbosity=opts.verbosity)
#adc.sync_adc(r)
print 'Setting accumulation length to %d'%opts.acc_len,
print '(%.2f seconds)'%((2*N_CHANS*opts.acc_len)/(clkrate*1e6))
# There is an inherent accumulation of 8 parallel samples. The register 'acc_len'
# controls serial accumulation, so write opts.acc_len/8 to it
r.write_int('acc_len',opts.acc_len//8)
fft_shift_int = int(opts.fft_shift,2)
print 'Setting fft-shift to %s'%opts.fft_shift
r.write_int('fft_shift0',fft_shift_int)
print 'Using test vector generator?:', opts.tvg
r.write_int('ct_tvg_en',int(opts.tvg))
import numpy as np import corr import adc5g as adc import time import struct ROACH = '192.168.0.111' r = corr.katcp_wrapper.FpgaClient(ROACH) time.sleep(0.1) print adc.calibrate_all_delays(r,0,verbosity=2) print adc.get_core_offsets(r) exit()
BOFFILE = 'adc5g_test_rev2.bof'
ROACH = '10.0.1.213'
SNAPNAME = 'scope_raw_0_snap'
def br(x):
return np.binary_repr(x, width=8)
r = corr.katcp_wrapper.FpgaClient(ROACH)
time.sleep(0.1)
r.progdev(BOFFILE)
adc5g.set_test_mode(r, 0, counter=False)
adc5g.sync_adc(r)
adc5g.calibrate_all_delays(r, 0, snaps=['snap'], verbosity=5)
#adc5g.calibrate_mmcm_phase(r, 0, ['snap'])
#adc5g.unset_test_mode(r, 0)
#a, b, c, d = adc5g.get_test_vector(r, ['snap'])
a, b, c, d = adc5g.get_test_vector(r, [SNAPNAME])
#x = adc5g.get_snapshot(r, 'scope_raw_0_snap')
#a = x[0::4]
#b = x[1::4]
#c = x[2::4]
#d = x[3::4]
for i in range(32):
print br(a[i]), br(b[i]), br(c[i]), br(d[i])
for cn, core in enumerate([a,b,c,d]):
pylab.plot(np.array(core) & 0xf, label='%d'%cn)
import numpy as np import corr import adc5g as adc import time import struct ROACH = '192.168.0.111' r = corr.katcp_wrapper.FpgaClient(ROACH) time.sleep(0.1) print adc.calibrate_all_delays(r, 0, verbosity=2) print adc.get_core_offsets(r) exit()
