def main(filename):
model = aiglib.aiger_init()
aiglib.aiger_open_and_read_from_file(model, filename)
for i in range(model.num_latches):
latch = aiglib.get_ith_latch(model, i)
m = match(regex, latch.name)
if m:
ltype = m.groups()[1][0]
if ltype == "b":
aiglib.aiger_add_bad(model, latch.next, latch.name)
if ltype == "c":
aiglib.aiger_add_constraint(model, latch.next, latch.name)
if ltype == "j":
aiglib.aiger_add_justice(model, 1, [latch.next], latch.name)
if ltype == "f":
aiglib.aiger_add_fairness(model, latch.next, latch.name)
res, string = aiglib.aiger_write_to_string(model,
aiglib.aiger_ascii_mode,
2147483648)
assert res != 0, 'writing failure'
print(string)
def main(spec_filename, k):
assert k > 0, str(k)
global spec
#: :type: aiglib.aiger
spec = aiglib.aiger_init()
aiglib.aiger_open_and_read_from_file(spec, spec_filename)
assert spec.num_fairness <= 1, 'more than one fairness property is not supported yet'
if spec.num_justice == 0:
write_and_die()
assert spec.num_justice == 1, 'more than one justice property is not supported yet: ' + str(spec.num_justice)
assert spec.justice.size == 1, 'the justice section should contain exactly one literal: ' + str(spec.justice.size)
add_counter_to_spec(k)
write_and_die()
def __init__(self, aiger_file_name, intro_error_latch=False):
self.spec = aiger_init()
err = aiger_open_and_read_from_file(self.spec, aiger_file_name)
assert not err, err
# introduce a fake latch for the error and call the given hook
self.error_fake_latch = None
if intro_error_latch:
self.introduce_error_latch()
# initialize caches
self._1l_land_cache = dict()
self._deps_cache = dict()
# dump some info about the spec
if not log.debug:
return
latches = [x.lit for x in self.iterate_latches()]
log.DBG_MSG(str(len(latches)) + " Latches: " + str(latches))
uinputs = [x.lit for x in self.iterate_uncontrollable_inputs()]
log.DBG_MSG(str(len(uinputs)) + " U. Inputs: " + str(uinputs))
cinputs = [x.lit for x in self.iterate_controllable_inputs()]
log.DBG_MSG(str(len(cinputs)) + " C. Inputs: " + str(cinputs))
def __init__(self, aiger_file_name, intro_error_latch=False):
self.spec = aiger_init()
err = aiger_open_and_read_from_file(self.spec, aiger_file_name)
assert not err, err
# introduce a fake latch for the error and call the given hook
self.error_fake_latch = None
if intro_error_latch:
self.introduce_error_latch()
# initialize caches
self._1l_land_cache = dict()
self._deps_cache = dict()
# dump some info about the spec
if not log.debug:
return
latches = [x.lit for x in self.iterate_latches()]
log.DBG_MSG(str(len(latches)) + " Latches: " + str(latches))
uinputs = [x.lit for x in self.iterate_uncontrollable_inputs()]
log.DBG_MSG(str(len(uinputs)) + " U. Inputs: " + str(uinputs))
cinputs = [x.lit for x in self.iterate_controllable_inputs()]
log.DBG_MSG(str(len(cinputs)) + " C. Inputs: " + str(cinputs))
def main(spec_filename, k):
assert k > 0, str(k)
global spec
#: :type: aiglib.aiger
spec = aiglib.aiger_init()
aiglib.aiger_open_and_read_from_file(spec, spec_filename)
assert spec.num_fairness <= 1, 'more than one fairness property is not supported yet'
if spec.num_justice == 0:
write_and_die()
assert spec.num_justice == 1, 'more than one justice property is not supported yet: ' + str(
spec.num_justice)
assert spec.justice.size == 1, 'the justice section should contain exactly one literal: ' + str(
spec.justice.size)
add_counter_to_spec(k)
write_and_die()
def main(filename):
model = aiglib.aiger_init()
aiglib.aiger_open_and_read_from_file(model, filename)
for i in range(model.num_latches):
latch = aiglib.get_ith_latch(model, i)
m = match(regex, latch.name)
if m:
ltype = m.groups()[1][0]
if ltype == "b":
aiglib.aiger_add_bad(model, latch.next, latch.name)
if ltype == "c":
aiglib.aiger_add_constraint(model, latch.next, latch.name)
if ltype == "j":
aiglib.aiger_add_justice(model, 1, [latch.next], latch.name)
if ltype == "f":
aiglib.aiger_add_fairness(model, latch.next, latch.name)
res, string = aiglib.aiger_write_to_string(model, aiglib.aiger_ascii_mode,
2147483648)
assert res != 0, 'writing failure'
print(string)
def main(filename):
#: :type: aiglib.aiger
model = aiglib.aiger_init()
aiglib.aiger_open_and_read_from_file(model, filename)
if model.num_justice == 0:
_write_result(model)
return
assert model.num_justice == 1
assert model.justice.size == 1
next_lit = (model.maxvar + 1) * 2
# first, add all elements
aiglib.aiger_add_input(model, next_lit, 'SYNT_2_HWMCC_aux')
#: :type: aiglib.aiger_symbol
aux = aiglib.aiger_is_input(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and1 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and2 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and3 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and4 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L1')
#: :type: aiglib.aiger_and
L1 = aiglib.aiger_is_latch(model, next_lit)
next_lit += 2
aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L2')
#: :type: aiglib.aiger_and
L2 = aiglib.aiger_is_latch(model, next_lit)
next_lit += 2
#: :type: aiglib.aiger_symbol
old_just_lit = aiglib.get_justice_lit(model, 0, 0)
# second, define all connections
and1.rhs0, and1.rhs1 = aux.lit + 1, L1.lit + 1
and2.rhs0, and2.rhs1 = L1.lit, old_just_lit
and3.rhs0, and3.rhs1 = and2.lhs + 1, L2.lit + 1
and4.rhs0, and4.rhs1 = L2.lit + 1, L1.lit
L1.next = and1.lhs + 1
L2.next = and3.lhs + 1
aiglib.set_justice_lit(model, 0, 0, and4.lhs)
#
_write_result(model)
def main(filename):
#: :type: aiglib.aiger
model = aiglib.aiger_init()
aiglib.aiger_open_and_read_from_file(model, filename)
if model.num_justice == 0:
_write_result(model)
return
assert model.num_justice == 1
assert model.justice.size == 1
next_lit = (model.maxvar + 1) * 2
# first, add all elements
aiglib.aiger_add_input(model, next_lit, 'SYNT_2_HWMCC_aux')
#: :type: aiglib.aiger_symbol
aux = aiglib.aiger_is_input(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and1 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and2 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and3 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and4 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L1')
#: :type: aiglib.aiger_and
L1 = aiglib.aiger_is_latch(model, next_lit)
next_lit += 2
aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L2')
#: :type: aiglib.aiger_and
L2 = aiglib.aiger_is_latch(model, next_lit)
next_lit += 2
#: :type: aiglib.aiger_symbol
old_just_lit = aiglib.get_justice_lit(model, 0, 0)
# second, define all connections
and1.rhs0, and1.rhs1 = aux.lit + 1, L1.lit + 1
and2.rhs0, and2.rhs1 = L1.lit, old_just_lit
and3.rhs0, and3.rhs1 = and2.lhs + 1, L2.lit + 1
and4.rhs0, and4.rhs1 = L2.lit + 1, L1.lit
L1.next = and1.lhs + 1
L2.next = and3.lhs + 1
aiglib.set_justice_lit(model, 0, 0, and4.lhs)
#
_write_result(model)
