def __init__(self, n):
self._n = n
self.enable = Signal()
self.offset = Signal(signed(9))
self.operands = Endpoint(
Layout([('inputs', Shape(8 * n)), ('filters', Shape(8 * n))]))
self.result = Endpoint(signed(32))
def test_layout_10_wo(self):
elem = Element(10, "w")
self.assertEqual(elem.width, 10)
self.assertEqual(elem.access, Element.Access.W)
self.assertEqual(elem.layout, Layout.cast([
("w_data", 10),
("w_stb", 1),
]))
def test_layout_1_ro(self):
elem = Element(1, "r")
self.assertEqual(elem.width, 1)
self.assertEqual(elem.access, Element.Access.R)
self.assertEqual(elem.layout, Layout.cast([
("r_data", 1),
("r_stb", 1),
]))
def test_layout_0_rw(self): # degenerate but legal case
elem = Element(0, access=Element.Access.RW)
self.assertEqual(elem.width, 0)
self.assertEqual(elem.access, Element.Access.RW)
self.assertEqual(elem.layout, Layout.cast([
("r_data", 0),
("r_stb", 1),
("w_data", 0),
("w_stb", 1),
]))
def test_layout_8_rw(self):
elem = Element(8, access="rw")
self.assertEqual(elem.width, 8)
self.assertEqual(elem.access, Element.Access.RW)
self.assertEqual(elem.layout, Layout.cast([
("r_data", 8),
("r_stb", 1),
("w_data", 8),
("w_stb", 1),
]))
def test_layout(self):
iface = Interface(addr_width=12, data_width=8)
self.assertEqual(iface.addr_width, 12)
self.assertEqual(iface.data_width, 8)
self.assertEqual(iface.layout, Layout.cast([
("addr", 12),
("r_data", 8),
("r_stb", 1),
("w_data", 8),
("w_stb", 1),
]))
def uart_gen_serial_record(platform: Platform, m: Module):
if platform:
serial = platform.request("uart")
debug = platform.request("debug")
m.d.comb += [
debug.eq(Cat(
serial.tx,
Const(0, 1), # GND
))
]
else:
serial = Record(Layout([("tx", 1)]), name="UART_SERIAL")
self.serial = serial # TODO this is obfuscated, but we need those signals for simulation testbench
return serial
def jtagify_dr(layout):
# assert all(len(x) == 2 for x in layout) or all(len(x) == 3 for x in layout)
def f(x):
if len(x) == 2:
return tuple([*x, DIR_FANOUT])
else:
return x
res = [
("r", list(map(f, layout))),
("w", list(map(f, layout))),
("update", 1, DIR_FANOUT),
("capture", 1, DIR_FANOUT),
]
return Layout(res)
def reg_make_rw(layout):
from amaranth.hdl.rec import DIR_FANIN, DIR_FANOUT, Record, Layout
# assert all(len(x) == 2 for x in layout) or all(len(x) == 3 for x in layout)
def f(x):
if len(x) == 2:
return tuple([*x, DIR_FANOUT])
else:
return x
res = [
("r", list(map(f, layout))),
("w", list(map(f, layout))),
("update", 1, DIR_FANOUT),
]
return Layout(res)
def __init__(self, input_streams):
self.field_names = list(name for name, shape in input_streams)
self.field_shapes = {name: shape for name, shape in input_streams}
self.inputs = {name: Endpoint(shape) for name, shape in input_streams}
self.output = Endpoint(Layout(input_streams))
self.reset = Signal()
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
from amaranth import Signal, Shape
from amaranth.hdl.dsl import Module
from amaranth.hdl.rec import Layout, Record
from amaranth.sim.core import Delay
from .stream import Endpoint, connect
from amaranth_cfu.util import SimpleElaboratable, TestBase
TEST_PAYLOAD_LAYOUT = Layout([
("one", Shape(32)),
("two", Shape(32)),
])
class DataProducer(SimpleElaboratable):
"""Producer for test purposes."""
def __init__(self):
self.next = Signal()
self.test_data = Record(TEST_PAYLOAD_LAYOUT)
self.output = Endpoint(TEST_PAYLOAD_LAYOUT)
def elab(self, m):
# Assert valid if new test_data available
# Deassert on transfer
data_waiting_to_send = Signal()
m.d.comb += self.output.payload.eq(self.test_data)
def write_stream_payload_type(self) -> Layout:
"""Gets the payload type for a write stream"""
return Layout([
("addr", self.addr_shape(), DIR_FANOUT),
("data", self.data_shape(), DIR_FANOUT),
])