def led_one(self,led_num,value): led_current = bf(self.read(self.map['LED'])) led_current_binary = "{0:b}".format(led_current[31:0]) # string containing current LED configuration in binary led_current_binary = "0000" + led_current_binary print "integer value of led_current_binary: " + str(int(led_current_binary,base=2)) print led_num print value print "current LED values in binary: " + led_current_binary # this string misses the first four zeros! print len(led_current_binary) print led_current_binary[0] print led_current_binary[15], led_current_binary[16] print led_current_binary[27] print "the type of led_current_binary is: %s" % (type(led_current_binary)) # check it's a string! print " " led_current_VALUE = led_current_binary[20:32] # take last part of string to get just VALUES led_VALUE_list = list(led_current_VALUE) # turn string into list so we can easily toggle its values print "The length of the array is %d" % (len(led_VALUE_list)) led_VALUE_list[led_num] = value # change the LED value that user wants to change led_VALUE_string = self.list_to_string(led_VALUE_list) # turn list of LED values back into string led_KEY_string = self.list_to_string(self.led_KEY_list) # turn list of LED key values to string led_full_string = self.led_unusedbits + led_KEY_string + self.led_unusedbits + led_VALUE_string # put the different strings together to get full LED configuration print "updated LED values in binary: " + led_full_string self.write(self.map['LED'],int(led_full_string,base=2)) # write in this new configuration to see the change take place print "integer value of led_full_string: " + str(int(led_full_string,base=2)) u= bf(self.read(self.map['LED'])) y= "{0:b}".format(u[31:0]) print "after we change everyting: "+"0000" + y print led_num print value
def clock(self, source): clocksel = bf(self.read(self.map['CLKSEL'])) pllctrl = bf(self.read(self.map['PLLCTRL'])) if source == self.internalClock: # Enable LAB clock. clocksel[1] = 1 # Use FPGA input. clocksel[0] = 0 # Enable local clock. clocksel[2] = 0 if pllctrl[1]: # Switch PLL to internal clock. Need to reset it. pllctrl[1] = 0 pllctrl[0] = 1 self.write(self.map['PLLCTRL'], int(pllctrl)) pllctrl[0] = 0 self.write(self.map['PLLCTRL'], int(pllctrl)) self.write(self.map['CLKSEL'], int(clocksel)) elif source == self.externalClock: # Enable LAB clock. clocksel[1] = 1 # Use TURF input. clocksel[0] = 1 # Disable local clock clocksel[2] = 1 if not pllctrl[1]: # Switch PLL to external clock. Need to reset it. pllctrl[1] = 1 pllctrl[0] = 1 self.write(self.map['PLLCTRL'], int(pllctrl)) pllctrl[0] = 0 self.write(self.map['PLLCTRL'], int(pllctrl)) self.write(self.map['CLKSEL'], int(clocksel))
def dma_event(self, lab, samples=1024): if not self.dma_enabled(): print "DMA is not enabled" return None board_data = [] for i in xrange(12): labdata=np.zeros(samples, dtype=np.int) board_data.append(labdata) ioaddr = self.dma_base() # SUPER MEGA SPEED # we split up the DMA buffer into two buffers of 8192 bytes (this is the max theoretical to read out from a LAB, # even if you can't do it) # then we DMA into one half while unpacking the other half. for i in xrange(12): self.write(self.map['DMA_BASE'], self.map['LAB4_ROM_BASE']+(i<<11)) # ping-pong between first 4096 bytes and second 4096 bytes # cache line size is 64 bytes, so no cache issues I think self.write(self.map['DMA_BASE']+0x4, ioaddr+(8192*(i&1))) self.write(self.map['DMA_BASE']+0x8, (samples>>1)-1) self.write(self.map['DMA_BASE']+0xC, 1) # If we're not loop #0, unpack the previous data if i: labdata = board_data[i-1] # obviously this is a mod 2 operation so can add instead of subtract offset = 8192*((i+1)&1) for i in range(0, int(samples), 2): labdata[i+1], labdata[i] = struct.unpack("<HH", self.dma_read(4, offset)) offset = offset+4 val = bf(self.read(self.map['DMA_BASE']+0xC)) ntries = 0 while not val[2]: if val[3]: print 'DMA error occurred: ', hex(int(val)) # issue abort self.write(self.map['DMA_BASE']+0xC, 0x10) return None if ntries > 10000: print 'DMA timeout? : ', hex(int(val)) # issue abort self.write(self.map['DMA_BASE']+0xC, 0x10) return None ntries = ntries + 1 val = bf(self.read(self.map['DMA_BASE']+0xC)) # OK, so now we've DMA'd all of the event data, but we need to unpack the last one labdata = board_data[11] offset = 8192 for i in range(0, int(samples), 2): labdata[i+1], labdata[i] = struct.unpack("<HH", self.dma_read(4, offset)) offset = offset + 4 return board_data
def reset_fifo(self, force=False, reset_readout=True): ctrl = bf(self.read(self.map['CONTROL'])) if ctrl[1] and not force: print 'cannot reset FIFO: LAB4 in run mode' return 1 else: if reset_readout: self.run_mode(0) rdout = bf(self.read(self.map['READOUT'])) rdout[1] = 1 rdout[2] = reset_readout self.write(self.map['READOUT'], rdout) return 0
def readout_testpattern_mode(self, enable=True): ctrl = bf(self.read(self.map['CONTROL'])) if enable: ctrl[15] = 1 else: ctrl[15] = 0 self.write(self.map['CONTROL'], ctrl)
def testpattern_mode(self, enable=True): #when enabled, SELany bit is 0 rdout = bf(self.read(self.map['READOUT'])) if enable: rdout[4] = 0 self.write(self.map['READOUT'], rdout) else: rdout[4] = 1 self.write(self.map['READOUT'], rdout)
def run_mode(self, enable=True): ctrl = bf(self.read(self.map['CONTROL'])) if enable: ctrl[1] = 1 self.write(self.map['CONTROL'], ctrl) else: ctrl[1] = 0 self.write(self.map['CONTROL'], ctrl)
def l4reg(self, lab, addr, value, verbose=False): ctrl = bf(self.read(self.map['CONTROL'])) if ctrl[1]: #should be checking ctrl[2], which indicates run-mode. but not working 6/9 print 'LAB4_Controller is running, cannot update registers.' return user = bf(self.read(self.map['L4REG'])) if user[31]: print 'LAB4_Controller is still processing a register?' return user[11:0] = value user[23:12] = addr user[27:24] = lab user[31] = 1 if verbose: print 'Going to write 0x%X' % user self.write(self.map['L4REG'], int(user)) while not user[31]: user = bf(self.read(self.map['L4REG']))
def reg_clr(self): ctrl = bf(self.read(self.map['CONTROL'])) if ctrl[1]: print 'cannot issue REG_CLR: LAB4 in run mode' return 1 else: self.write(0, 0xFFF0000) self.write(0, 0) return 0
def check_fifo(self, check_fifos=False): rdout = bf(self.read(self.map['READOUT'])) ''' check_mode = 0, check if data available on any fifo (not empty) check_mode = 1, check individual readout fifo empties, return 12 bits ''' if check_fifos: return rdout[27:16] else: return rdout[3]
def set_vped(self, value, eeprom=False): val = bf(value) if eeprom: dac_bytes = [0x5E, (0x8 << 4) | (val[11:8]), val[7:0]] else: dac_bytes = [0x46, (0x8 << 4) | (val[11:8]), val[7:0]] self.dac.write_seq(dac_bytes) if eeprom: self.wait() self.wait(0.1)
def set_rfp_vped(self, value=[0x9C4, 0x578, 0x578], eeprom=False): val0 = bf(value[0]) val1 = bf(value[1]) val2 = bf(value[2]) dac_bytes = [] if eeprom: dac_bytes.append([0x58, (0x8 << 4) | (val0[11:8]), val0[7:0]]) dac_bytes.append([0x5A, (0x8 << 4) | (val1[11:8]), val1[7:0]]) dac_bytes.append([0x5C, (0x8 << 4) | (val2[11:8]), val2[7:0]]) else: dac_bytes.append([0x40, (0x8 << 4) | (val0[11:8]), val0[7:0]]) dac_bytes.append([0x42, (0x8 << 4) | (val1[11:8]), val1[7:0]]) dac_bytes.append([0x44, (0x8 << 4) | (val2[11:8]), val2[7:0]]) for i in range(0, len(dac_bytes)): self.dac.write_seq(dac_bytes[i]) if eeprom: self.wait( ) #time delay required to write to eeprom! (can be better handled, surely) self.wait(0.1)
def scan_edge(self,lab, pos=0, start=0): val = bf(0) val[15:0] = start val[24] = pos val[19:16] = lab self.write(self.map['PHASEARG'], int(val)) self.write(self.map['PHASECMD'], 0x04) ret=self.read(self.map['PHASECMD']) while ret != 0x00: ret = self.read(self.map['PHASECMD']) return self.read(self.map['PHASERES'])
def dma_lab(self, lab, samples=1024): # need something here to determine if the backend has DMA enabled and also to check the DMA address, I guess if not self.dma_enabled(): print "DMA is not enabled." return None labdata=np.zeros(samples, dtype=np.int) # this is the board's I/O address in the IOMMU ioaddr = 0 # write source address self.write(self.map['DMA_BASE'], self.map['LAB4_ROM_BASE']+(lab<<11)) # write destination address self.write(self.map['DMA_BASE']+0x4, self.dma_base()) # write number of samples minus 1 self.write(self.map['DMA_BASE']+0x8, (samples>>1)-1) # initiate DMA self.write(self.map['DMA_BASE']+0xC, 1) val = bf(self.read(self.map['DMA_BASE']+0xC)) ntries = 0 while not val[2]: ntries = ntries + 1 if val[3]: print 'DMA error occurred: ', hex(int(val)) # issue abort self.write(self.map['DMA_BASE']+0xC, 0x10) return None if ntries > 10000: print 'DMA timeout? : ', hex(int(val)) # issue abort self.write(self.map['DMA_BASE']+0xC, 0x10) return None val = bf(self.read(self.map['DMA_BASE']+0xC)) # Note: unpacking means sample0 gets stuck in [31:16], and sample1 gets stuck in [15:0] (first write in most significant bits) offset = 0 for i in range(0, int(samples), 2): labdata[i+1], labdata[i] = struct.unpack("<HH", self.dma_read(4, offset)) offset = offset + 4 return labdata
def scan_value(self,lab,position): if position > 4479: print "Position must be 0-4479." return None val = bf(0) val[15:0] = position val[19:16] = lab self.write(self.map['PHASEARG'], int(val)) self.write(self.map['PHASECMD'], 0x03) res = self.read(self.map['PHASECMD']) while res != 0x00: res = self.read(self.map['PHASECMD']) return self.read(self.map['PHASERES'])
def config_rfp(self, continuous_mode=True, data_rate=2, input_mux=3, pga_gain=2, thresh_lo=0x8000, thresh_hi=0x7FFF): if not self.has_rfp: return rfp_config_register = 0x1 rfp_lothresh_register = 0x2 rfp_hithresh_register = 0x3 config_hi = (input_mux & 0x7) << 4 | (pga_gain & 0x7) << 1 | ( not continuous_mode) | 0x00 config_lo = (data_rate & 0x7) << 5 | 0x00 #set threshold register values to enable continuous mode: #hi-thresh MSB = '1', lo-thresh MSB = '0' if continuous_mode: thresh_lo = thresh_lo & (0 << 16) thresh_hi = thresh_hi | 0x8000 #configure all rfp channels similarly: for i in range(0, 12): self.rfp[i].write_seq([rfp_config_register, config_hi, config_lo]) self.wait(0.01) #verify write (NOTE: top bit different for read/write in config reguster, so not compared!) ######## ( the top bit 15: indicates a `conversion in process' if [0] or not if [1] ) if self.read_rfp( rfp_config_register, i)[14:0] != bf((config_hi << 8) | config_lo)[14:0]: print 'rfp %i error: write/read mismatch to config register' % i self.rfp[i].write_seq([ rfp_lothresh_register, bf(thresh_lo)[15:8], bf(thresh_lo)[7:0] ]) self.wait(0.01) if self.read_rfp(rfp_lothresh_register, i)[15:0] != bf(thresh_lo)[15:0]: print 'rfp %i error: write/read mismatch to low-thresh register' % i self.rfp[i].write_seq([ rfp_hithresh_register, bf(thresh_hi)[15:8], bf(thresh_hi)[7:0] ]) self.wait(0.01) if self.read_rfp(rfp_hithresh_register, i)[15:0] != bf(thresh_hi)[15:0]: print 'rfp %i error: write/read mismatch to hi-thresh register' % i
def run_rfp(self, lab, run_time=5.0, plot=False): if not self.has_rfp: return None my_rfp = [] my_rfp.append(RFPdata(lab)) self.ioexpander.read_seq( 2) #do an initial read to clear any interrupts start = time.time() while ((time.time() - start) < run_time): self.ioexpander.write_seq( [0x4D]) #address the interupt status register, port 1 interrupt = self.ioexpander.read_seq( 2) #read 2 bytes (upper and lower ports) interrupt_time = time.time() - start interrupt_status_register = bf(((interrupt[0] & 0x0F) << 8) | (interrupt[1] & 0xFF)) if interrupt_status_register[11 - lab] == 1: my_rfp[0].data.append(self.read_rfp(0x0, lab)[15:0]) my_rfp[0].time.append(interrupt_time) self.ioexpander.write_seq([0x01]) self.ioexpander.read_seq( 2) #reading input register clears the interrupt self.ioexpander.read_seq(2) #convert from 2's complement: for j in range(0, len(my_rfp[0].data)): if my_rfp[0].data[j] > 0x7FFF: my_rfp[0].data[j] = my_rfp[0].data[j] - (1 << 16) if plot: import matplotlib.pyplot as plt plt.ion() plt.plot(my_rfp[0].time, my_rfp[0].data, 'o-') return my_rfp
def status(self): clocksel = bf(self.read(self.map['CLKSEL'])) pllctrl = bf(self.read(self.map['PLLCTRL'])) int_status = bf(self.read(self.map['INTCSR'])) int_mask = bf(self.read(self.map['INTMASK'])) led = bf(self.read(self.map['LED'])) labcontrol = bf(self.labc.read(self.labc.map['CONTROL'])) labreadout = bf(self.labc.read(self.labc.map['READOUT'])) print "Clock Status: LAB4 Clock is %s (CLKSEL[1] = %d)" % ("enabled" if clocksel[1] else "not enabled", clocksel[1]) print " : LAB4 Driving Clock is %s (CLKSEL[0] = %d)" % ("TURF Clock" if clocksel[0] else "FPGA Clock", clocksel[0]) print " : Local Clock is %s (CLKSEL[2] = %d)" % ("enabled" if not clocksel[2] else "not enabled", clocksel[2]) print " : FPGA System Clock PLL is %s (PLLCTRL[0] = %d/PLLCTRL[2] = %d)" % ("powered down" if pllctrl[2] else ("running" if not pllctrl[0] else "in reset"), pllctrl[0], pllctrl[2]) print " : FPGA System Clock is %s (PLLCTRL[1] = %d)" % ("TURF Clock" if pllctrl[1] else "Local Clock", pllctrl[1]) print " Int Status : %8.8x" % (self.read(self.map['INTCSR']) & 0xFFFFFFFF) print " LED : Internal value %3.3x, Key value %3.3x" % (led[11:0], led[27:16]) print " Full LED : %8.8x" % (self.read(self.map['LED']) & 0xFFFFFFFF) print " Int Mask : %8.8x" % (self.read(self.map['INTMASK']) & 0xFFFFFFFF) print "**********************" self.i2c.read_dac() print "**********************" print "LAB4 runmode: %s" % ("enabled" if labcontrol[1] else "not enabled") print "LAB4 testpat: %s" % ("enabled" if not labreadout[4] else "not enabled") print "LAB4 readout testpat: %s" % ("enabled" if labcontrol[15] else "not enabled")
def spi_cs(self, device, state): # We only have 1 SPI device. val = bf(self.read(self.map['SPICS'])) val[device] = state self.write(self.map['SPICS'], int(val))
def start(self): ctrl = bf(self.read(self.map['CONTROL'])) while not ctrl[2]: ctrl[1] = 1 self.write(self.map['CONTROL'], int(ctrl)) ctrl = bf(self.read(self.map['CONTROL']))
def read_rfp(self, pointer_reg, lab): if not self.has_rfp: return None self.rfp[lab].write_seq([pointer_reg]) rfp_register = self.rfp[lab].read_seq(2) return bf((rfp_register[0] << 8) | rfp_register[1])
def identify(self): ident = bf(self.read(self.map['IDENT'])) ver = bf(self.read(self.map['VERSION'])) print "Identification Register: %x (%c%c%c%c)" % (int(ident),ident[31:24],ident[23:16],ident[15:8],ident[7:0]) print "Version Register: %d.%d.%d compiled %d/%d" % (ver[15:12], ver[11:8], ver[7:0], ver[28:24], ver[23:16]) print "Device DNA: %x" % self.dna()
def stop(self): ctrl = bf(self.read(self.map['CONTROL'])) while ctrl[2]: ctrl[1] = 0 self.write(self.map['CONTROL'], int(ctrl)) ctrl = bf(self.read(self.map['CONTROL']))
def reset_ramp(self): ctrl = bf(self.read(self.map['CONTROL'])) ctrl[8] = 1 self.write(self.map['CONTROL'], ctrl)
def read_fifo(self, lab, address=0): val = bf(self.read(self.map['LAB4_ROM_BASE']+(lab<<11)+address)) sample0 = val[15:0] sample1 = val[31:16] return int(sample0), int(sample1)