def test_top_simple_write_read(mode, num_slaves):
Top = TopGenerator(mode=mode)
tester = fault.Tester(Top, clock=Top.apb.PCLK)
tester.circuit.apb.PRESETn = 1
addr_width = len(Top.apb.PADDR)
data_width = len(Top.apb.PWDATA)
bus = APBBus(addr_width, data_width, num_slaves)
for i in range(2):
for addr, field in enumerate(dma_fields):
if mode == "pack":
addr += i * len(dma_fields)
slave_id = 0
else:
slave_id = i
data = fault.random.random_bv(data_width)
io, request = make_request(addr, data, addr_width, data_width,
num_slaves, slave_id)
write(bus, io, request, tester, addr, data)
getattr(getattr(tester.circuit, f"dma{i}"),
f"{field}").expect(data)
read(bus, io, request, tester, addr, data)
tester.compile_and_run(target="verilator", magma_output="coreir-verilog",
magma_opts={"verilator_debug": True},
flags=["--trace"])
def test_write_then_reads():
data_width = 32
regs = [Register(f"reg_{i}", init=i, has_ce=True) for i in range(4)]
RegFile = DefineRegFile(regs, data_width)
tester = fault.Tester(RegFile, clock=RegFile.apb.PCLK)
tester.circuit.apb.PRESETn = 1
addr_width = m.bitutils.clog2(len(regs))
data_width = 32
bus = APBBus(addr_width, data_width)
values = [0xDE, 0xAD, 0xBE, 0xEF]
for addr, data in enumerate(values):
io, request = make_request(addr, data, addr_width, data_width)
write(bus, io, request, tester, addr, data)
getattr(tester.circuit, f"reg_{addr}_q").expect(data)
for addr, data in enumerate(values):
io, request = make_request(addr, data, addr_width, data_width)
read(bus, io, request, tester, addr, data)
tester.compile_and_run(target="verilator", magma_output="coreir-verilog",
magma_opts={"verilator_debug": True},
flags=["--trace"])
def test_simple_write_read():
data_width = 32
regs = [Register(f"reg_{i}", init=i, has_ce=True) for i in range(4)]
RegFile = DefineRegFile(regs, data_width)
tester = fault.Tester(RegFile, clock=RegFile.apb.PCLK)
tester.circuit.apb.PRESETn = 1
addr_width = m.bitutils.clog2(len(regs))
data_width = 32
bus = APBBus(addr_width, data_width)
addr = 1
data = 45
io, request = make_request(addr, data, addr_width, data_width)
write(bus, io, request, tester, addr, data)
read(bus, io, request, tester, addr, data)
tester.compile_and_run(target="verilator", magma_output="coreir-verilog",
magma_opts={"verilator_debug": True},
flags=["--trace"])
def test_simple_write():
data_width = 32
regs = tuple(Register(f"reg_{i}", init=i, has_ce=True) for i in range(4))
RegFile = RegisterFileGenerator(regs, data_width)
tester = fault.Tester(RegFile, clock=RegFile.apb.PCLK)
tester.circuit.apb.PRESETn = 1
addr_width = m.bitutils.clog2(len(regs))
data_width = 32
addr = 1
data = 45
bus = APBBus(addr_width, data_width)
io, request = make_request(addr, data, addr_width, data_width)
write(bus, io, request, tester, addr, data)
getattr(tester.circuit, f"reg_{addr}_q").expect(data)
tester.compile_and_run(target="verilator",
magma_output="coreir-verilog",
magma_opts={"verilator_debug": True},
flags=["--trace"])