def getVal(self, proc, inst):
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
rmVal = getattr(proc, rm)
shift_imm = utils.getBits(inst, 7, 5)
if shift_imm == 0:
if utils.getBits(rmVal, 31) == 0:
shifter_operand = 0
shifter_carry_out = utils.getBits(rmVal, 31)
else:
shifter_operand = 0xFFFFFFFF
shifter_carry_out = utils.getBits(rmVal, 31)
else:
shifter_operand = utils.asr(rmVal, shift_imm)
shifter_carry_out = utils.getBits(rmVal, shift_imm - 1)
return (shifter_operand, shifter_carry_out)
def getVal(self, proc, inst):
u = utils.getBits(inst, 23)
rn = utils.getBits(inst, 16, 4)
rn = 'r' + str(rn)
rnVal = getattr(proc, rn)
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
rmVal = getattr(proc, rm)
shift = utils.getBits(inst, 5, 2)
shift_imm = utils.getBits(inst, 7, 5)
if shift == 0: #LSL
index = rmVal << shift_imm
index &= 0xFFFFFFFF
elif shift == 1: #LSR
if shift_imm == 0:
index = 0
else:
index = rmVal >> shift_imm
elif shift == 2: #ASR
if shift_imm == 0:
if utils.getBits(rmVal, 31) == 1:
index = 0xFFFFFFFF
else:
index = 0
else:
index = utils.asr(rmVal, shift_imm)
elif shift == 3: #ROR or RRX
if shift_imm == 0:
index = (proc.statusFlag('C') << 31) | (rmVal >> 1)
else:
index = utils.ror(rmVal, 32, shift_imm)
if u == 1:
address = rnVal + index
else:
address = rnVal - index
if utils.checkCondition(proc, inst):
setattr(proc, rn, address)
return address
def getVal(self, proc, inst):
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
rs = utils.getBits(inst, 8, 4)
rs = 'r' + str(rs)
rs_val = utils.getBits(getattr(proc, rs), 0, 8)
if rs_val == 0:
shifter_operand = getattr(proc, rm)
shifter_carry_out = proc.statusFlag('C')
elif rs_val < 32:
shifter_operand = utils.asr(getattr(proc, rm), rs_val)
shifter_carry_out = utils.getBits(getattr(proc, rm), rs_val - 1)
else:
if utils.getBits(getattr(proc, rm), 31) == 0:
shifter_operand = 0
shifter_carry_out = utils.getBits(getattr(proc, rm), 31)
else:
shifter_operand = 0xFFFFFFFF
shifter_carry_out = utils.getBits(getattr(proc, rm), 31)
return (shifter_operand, shifter_carry_out)
