def execute(self, proc, inst):
shifter_operand = 0
shifter_carry_out = 0
if not checkCondition(proc, inst):
return
rn = utils.getBits(inst, 16, 4)
rn = 'r' + str(rn)
rnVal = getattr(proc, rn)
modes = component.getAllUtilitiesRegisteredFor(IARMDPAddressingMode)
for mode in modes:
if testInstruction(mode, inst):
shifter_operand, shifter_carry_out = mode.getVal(proc, inst)
break
rnBitset = Bitset(rnVal, 32)
shifterBitset = Bitset(shifter_operand, 32)
alu_out, carry = rnBitset + shifter_operand
if utils.getBits(rnVal, 31) == 0 and utils.getBits(int(result), 31) == 1:
v = 1
else:
v = 0
proc.setStatusFlag('N', utils.getBits(int(alu_out), 31))
proc.setStatusFlag('Z', int(int(alu_out) == 0))
proc.setStatusFlag('C', carry)
proc.setStatusFlag('V', v)
def execute(self, proc, inst):
shifter_operand = 0
shifter_carry_out = 0
if not checkCondition(proc, inst):
return
S = utils.getBits(inst, 20)
I = utils.getBits(inst, 25)
rd = utils.getBits(inst, 12, 4)
rd = 'r' + str(rd)
rn = utils.getBits(inst, 16, 4)
rn = 'r' + str(rn)
rdVal = getattr(proc, rd)
rnVal = getattr(proc, rn)
modes = component.getAllUtilitiesRegisteredFor(IARMDPAddressingMode)
for mode in modes:
if testInstruction(mode, inst):
shifter_operand, shifter_carry_out = mode.getVal(proc, inst)
break
setattr(proc, rd, rnVal ^ shifter_operand)
if S == 1 and rd == 'r15':
try:
proc.cpsr = proc.spsr
except:
print "UNPREDICTABLE"
elif S == 1:
proc.setStatusFlag('N', utils.getBits(getattr(proc, rd), 31))
proc.setStatusFlag('Z', int(getattr(proc, rd) == 0))
proc.setStatusFlag('C', shifter_carry_out)
def execute(self, proc, inst):
if not utils.checkCondition(proc, inst):
return
target = utils.getBits(inst, 0, 4)
t = utils.getBits(target, 0)
if t:
raise Exception("Thumb instruction set not implemented")
proc.pc = target & 0xFFFFFFFE
def getVal(self, proc, inst):
rotate_imm = utils.getBits(inst, 8, 4)
immed_8 = utils.getBits(inst, 0, 8)
shifter_operand = utils.ror(immed_8, 32, rotate_imm * 2)
if rotate_imm == 0:
shifter_carry_out = proc.statusFlag('C')
else:
shifter_carry_out = utils.getBits(shifter_operand, 31)
return (shifter_operand, shifter_carry_out)
def saveAddr(self, address, value, num_bytes=4, endianess='L'):
nextAddr = address
if(endianess == 'L'):
for i in range(num_bytes):
self.memory.write(nextAddr + i, utils.getBits(value, i * 8, 8))
else:
for i in range(num_bytes):
j = num_bytes - 1 - i
self.memory.write(nextAddr + i, utils.getBits(value, j * 8, 8))
def getVal(self, proc, inst):
u = utils.getBits(inst, 23)
rn = utils.getBits(inst, 16, 4)
rn = 'r' + str(rn)
rnVal = getattr(proc, rn)
offset_12 = utils.getBits(inst, 0, 12)
if u == 1:
address = rnVal + offset_12
else:
address = rnVal - offset_12
return address
def getVal(self, proc, inst):
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
shift_imm = utils.getBits(inst, 7, 5)
if shift_imm == 0:
shifter_operand = getattr(proc, rm)
shifter_carry_out = utils.getBits(getattr(proc, rm), 31)
else:
shifter_operand = getattr(proc, rm) >> shift_imm
shifter_carry_out = utils.getBits(getattr(proc, rm), shift_imm - 1)
return (shifter_operand, shifter_carry_out)
def getVal(self, proc, inst):
rn = utils.getBits(inst, 16, 4)
rn = 'r' + str(rn)
register_list = utils.getBits(inst, 0, 16)
rnVal = getattr(proc, rn)
start_address = rnVal
end_address = rnVal + (utils.countSetBits(register_list) * 4) - 4
if utils.checkCondition(proc, inst):
setattr(proc, rn, end_address + 4)
return (start_address, end_address)
def getVal(self, proc, inst):
u = utils.getBits(inst, 23)
rn = utils.getBits(inst, 16, 4)
rn = 'r' + str(rn)
rnVal = getattr(proc, rn)
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
rmVal = getattr(proc, rm)
if u == 1:
address = rnVal + rmVal
else:
address = rnVal - rmVal
return address
def getVal(self, proc, inst):
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
shift_imm = utils.getBits(inst, 7, 5)
if shift_imm == 0:
shifter_operand = getattr(proc, rm)
shifter_carry_out = proc.statusFlag('C')
else:
shifter_operand = getattr(proc, rm) << shift_imm
shifter_operand = shifter_operand & 0xFFFFFFFF
shifter_carry_out = utils.getBits(getattr(proc, rm), 32 - shift_imm)
return (shifter_operand, shifter_carry_out)
def execute(self, proc, inst):
if not utils.checkCondition(proc, inst):
return
l = utils.getBits(inst, 24)
signed_immed_24 = utils.getBits(inst, 0, 24)
if l == 1:
proc.lr = proc.pc
branch_addr = utils.signExtend(signed_immed_24, 24, 30)
branch_addr = branch_addr << 2
branch_addr = utils.signValue(branch_addr)
proc.pc += 4 + branch_addr
def getVal(self, proc, inst):
rn = utils.getBits(inst, 16, 4)
rn = 'r' + str(rn)
register_list = utils.getBits(inst, 0, 16)
rnVal = getattr(proc, rn)
w = utils.getBits(inst, 21)
start_address = rnVal - (utils.countSetBits(register_list) * 4) + 4
end_address = rnVal
if utils.checkCondition(proc, inst) and w == 1:
setattr(proc, rn, start_address - 4)
return (start_address, end_address)
def execute(self, proc, inst):
if not utils.checkCondition(proc, inst):
return
modes = component.getAllUtilitiesRegisteredFor(IARMLSAddressingMode)
for mode in modes:
if utils.testInstruction(mode, inst):
address = mode.getVal(proc, inst)
break
rd = utils.getBits(inst, 12, 4)
rd = 'r' + str(rd)
value = getattr(proc, rd)
value = utils.getBits(value, 0, 16)
proc.saveAddr(address, value, 2)
def execute(self, proc, inst):
if not utils.checkCondition(proc, inst):
return
modes = component.getAllUtilitiesRegisteredFor(IARMLSMAddressingMode)
for mode in modes:
if utils.testInstruction(mode, inst):
start_address, end_address = mode.getVal(proc, inst)
break
register_list = Bitset(utils.getBits(inst, 0, 16), 32)
address = start_address
for i in range(15):
if register_list[i]:
setattr(proc, 'r' + str(i), proc.readAddr(address, 4))
address += 4
if register_list[15]:
value = proc.readAddr(address, 4)
proc.pc = value & 0xFFFFFFFE
address += 4
if end_address != address - 4:
raise exceptions.DataAbort()
def getVal(self, proc, inst):
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
rmVal = getattr(proc, rm)
shift_imm = utils.getBits(inst, 7, 5)
if shift_imm == 0:
operand1 = proc.statusFlag('C') << 31
operand1 = operand1 & 0xFFFFFFFF
operand2 = rmVal >> 1
shifter_operand = operand1 | operand2
shifter_carry_out = utils.getBits(rmVal, 0)
else:
shifter_operand = utils.ror(rmVal, 32, shift_imm)
shifter_carry_out = utils.getBits(rmVal, shift_imm - 1)
return (shifter_operand, shifter_carry_out)
def execute(self, proc, inst):
if not utils.checkCondition(proc, inst):
return
modes = component.getAllUtilitiesRegisteredFor(IARMLSMAddressingMode)
for mode in modes:
if utils.testInstruction(mode, inst):
start_address, end_address = mode.getVal(proc, inst)
break
register_list = Bitset(utils.getBits(inst, 0, 16), 32)
address = start_address
print "Entra"
for i in range(16):
if register_list[i]:
print i, getattr(proc, 'r' + str(i))
proc.saveAddr(address, getattr(proc, 'r' + str(i)))
address += 4
print "Sale"
if end_address != address - 4:
raise exceptions.DataAbort()
def execute(self, proc, inst):
if not utils.checkCondition(proc, inst):
return
modes = component.getAllUtilitiesRegisteredFor(IARMLSAddressingMode)
for mode in modes:
if utils.testInstruction(mode, inst):
address = mode.getVal(proc, inst)
break
rd = utils.getBits(inst, 12, 4)
rd = 'r' + str(rd)
rn = utils.getBits(inst, 16, 4)
rn = 'r' + str(rn)
data = proc.readAddr(address, 1)
setattr(proc, rd, data)
setattr(proc, rn, address)
def getVal(self, proc, inst):
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
rs = utils.getBits(inst, 8, 4)
rs = 'r' + str(rs)
rs_val = utils.getBits(getattr(proc, rs), 0, 8)
if rs_val == 0:
shifter_operand = getattr(proc, rm)
shifter_carry_out = proc.statusFlag('C')
elif rs_val < 32:
shifter_operand = getattr(proc, rm) >> rs_val
shifter_carry_out = utils.getBits(getattr(proc, rm), rs_val - 1)
elif rs_val == 32:
shifter_operand = 0
shifter_carry_out = utils.getBits(getattr(proc, rm), 1)
else:
shifter_operand = 0
shifter_carry_out = 0
return (shifter_operand, shifter_carry_out)
def execute(self, proc, inst):
shifter_operand = 0
shifter_carry_out = 0
if not checkCondition(proc, inst):
return
rn = utils.getBits(inst, 16, 4)
rn = 'r' + str(rn)
rnVal = getattr(proc, rn)
modes = component.getAllUtilitiesRegisteredFor(IARMDPAddressingMode)
for mode in modes:
if testInstruction(mode, inst):
shifter_operand, shifter_carry_out = mode.getVal(proc, inst)
break
alu_out = rnVal ^ shifter_operand
proc.setStatusFlag('N', utils.getBits(alu_out, 31))
proc.setStatusFlag('Z', int(alu_out == 0))
proc.setStatusFlag('C', shifter_carry_out)
def execute(self, proc, inst):
shifter_operand = 0
shifter_carry_out = 0
if not checkCondition(proc, inst):
return
S = utils.getBits(inst, 20)
I = utils.getBits(inst, 25)
rd = utils.getBits(inst, 12, 4)
rd = 'r' + str(rd)
rn = utils.getBits(inst, 16, 4)
rn = 'r' + str(rn)
rdVal = getattr(proc, rd)
rnVal = getattr(proc, rn)
rnBitset = Bitset(rnVal, 32)
carryBitset = Bitset(proc.statusFlag('C'), 32)
modes = component.getAllUtilitiesRegisteredFor(IARMDPAddressingMode)
for mode in modes:
if testInstruction(mode, inst):
shifter_operand, shifter_carry_out = mode.getVal(proc, inst)
break
shifter_bitset = Bitset(shifter_operand, 32)
result, carry = shifter_bitset - rnBitset
resultBitset = Bitset(result, 32)
carryBitset[0] = not carryBitset[0]
result, carry = resultBitset - carryBitset
setattr(proc, rd, int(result))
if S == 1 and rd == 'r15':
try:
proc.cpsr = proc.spsr
except:
print "UNPREDICTABLE"
elif S == 1:
if utils.getBits(rdVal, 31) == 0 and utils.getBits(int(result), 31) == 1:
v = 1
else:
v = 0
proc.setStatusFlag('N', utils.getBits(getattr(proc, rd), 31))
proc.setStatusFlag('Z', int(getattr(proc, rd) == 0))
proc.setStatusFlag('C', int(carry == 0))
proc.setStatusFlag('V', v)
print "Ejecutaste un rsc"
def getVal(self, proc, inst):
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
rmVal = getattr(proc, rm)
shift_imm = utils.getBits(inst, 7, 5)
if shift_imm == 0:
if utils.getBits(rmVal, 31) == 0:
shifter_operand = 0
shifter_carry_out = utils.getBits(rmVal, 31)
else:
shifter_operand = 0xFFFFFFFF
shifter_carry_out = utils.getBits(rmVal, 31)
else:
shifter_operand = utils.asr(rmVal, shift_imm)
shifter_carry_out = utils.getBits(rmVal, shift_imm - 1)
return (shifter_operand, shifter_carry_out)
def getVal(self, proc, inst):
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
rs = utils.getBits(inst, 8, 4)
rs = 'r' + str(rs)
rs_val = utils.getBits(getattr(proc, rs), 0, 8)
rs_val2 = utils.getBits(getattr(proc, rs), 0, 5)
if rs_val == 0:
shifter_operand = getattr(proc, rm)
shifter_carry_out = proc.statusFlag('C')
elif rs_val2 == 0:
shifter_operand = getattr(proc, rm)
shifter_carry_out = utils.getBits(getattr(proc, rm), 31)
else:
shifter_operand = utils.ror(getattr(proc, rm), 32, rs_val2)
shifter_carry_out = utils.getBits(getattr(proc, rm), rs_val2 - 1)
return (shifter_operand, shifter_carry_out)
def getVal(self, proc, inst):
u = utils.getBits(inst, 23)
rn = utils.getBits(inst, 16, 4)
rn = 'r' + str(rn)
rnVal = getattr(proc, rn)
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
rmVal = getattr(proc, rm)
shift = utils.getBits(inst, 5, 2)
shift_imm = utils.getBits(inst, 7, 5)
if shift == 0: #LSL
index = rmVal << shift_imm
index &= 0xFFFFFFFF
elif shift == 1: #LSR
if shift_imm == 0:
index = 0
else:
index = rmVal >> shift_imm
elif shift == 2: #ASR
if shift_imm == 0:
if utils.getBits(rmVal, 31) == 1:
index = 0xFFFFFFFF
else:
index = 0
else:
index = utils.asr(rmVal, shift_imm)
elif shift == 3: #ROR or RRX
if shift_imm == 0:
index = (proc.statusFlag('C') << 31) | (rmVal >> 1)
else:
index = utils.ror(rmVal, 32, shift_imm)
if u == 1:
address = rnVal + index
else:
address = rnVal - index
if utils.checkCondition(proc, inst):
setattr(proc, rn, address)
return address
def getVal(self, proc, inst):
rm = utils.getBits(inst, 0, 4)
rm = 'r' + str(rm)
shifter_operand = getattr(proc, rm)
shifter_carry_out = proc.statusFlag('C')
return (shifter_operand, shifter_carry_out)
