def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(15)
except EndOfInstruction:
pass
else:
base = align(processor.registers.get_pc(), 4)
address = bits_add(base, self.imm32,
32) if self.add else bits_sub(
base, self.imm32, 32)
data = processor.mem_u_get(address, 4)
if self.t == 15:
if lower_chunk(address, 2) == 0b00:
processor.load_write_pc(data)
else:
print('unpredictable')
elif processor.unaligned_support() or lower_chunk(address,
2) == 0b00:
processor.registers.set(self.t, data)
else:
if processor.registers.current_instr_set() == InstrSet.ARM:
processor.registers.set(
self.t, ror(data, 32, 8 * lower_chunk(address, 2)))
else:
processor.registers.set(self.t, 0x00000000) # unknown
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset_addr = bits_add(processor.registers.get(
self.n), self.imm32, 32) if self.add else bits_sub(
processor.registers.get(self.n), self.imm32, 32)
address = offset_addr if self.index else processor.registers.get(
self.n)
data = processor.mem_u_get(address, 4)
if self.wback:
processor.registers.set(self.n, offset_addr)
if self.t == 15:
if lower_chunk(address, 2) == 0b00:
processor.load_write_pc(data)
else:
print('unpredictable')
elif processor.unaligned_support() or lower_chunk(address,
2) == 0b00:
processor.registers.set(self.t, data)
else:
processor.registers.set(self.t, 0x00000000) # unknown
def it_advance(self):
if bits_ops.lower_chunk(self.cpsr.it, 3) == 0b000:
self.cpsr.it = 0
else:
itstate = self.cpsr.it
mask, carry = shift.lsl_c(bits_ops.lower_chunk(itstate, 4), 4, 1)
condition_state = chain(carry, mask, 4)
self.cpsr.it = set_substring(itstate, 4, 0, condition_state)
def execute(self, processor):
if processor.condition_passed():
n = processor.registers.get(self.n)
m = processor.registers.get(self.m)
sum_ = substring(n, 15, 0) + substring(m, 31, 16)
diff = substring(n, 31, 16) - substring(m, 15, 0)
d = set_substring(0, 15, 0, lower_chunk(sum_, 16))
d = set_substring(d, 31, 16, lower_chunk(diff, 16))
processor.registers.set(self.d, d)
ge = 0b11 if sum_ >= 0x10000 else 00
ge = set_substring(ge, 3, 2, 0b11 if diff >= 0 else 00)
processor.registers.cpsr.ge = ge
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), 32,
self.shift_t, self.shift_n,
processor.registers.cpsr.c)
offset_addr = bits_add(processor.registers.get(
self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = offset_addr if self.index else processor.registers.get(
self.n)
if self.t == 15:
data = processor.registers.pc_store_value()
else:
data = processor.registers.get(self.t)
if (processor.unaligned_support()
or lower_chunk(address, 2) == 0b00
or processor.registers.current_instr_set()
== InstrSet.ARM):
processor.mem_u_set(address, 4, data)
else:
processor.mem_u_set(address, 4, 0x00000000) # unknown
if self.wback:
processor.registers.set(self.n, offset_addr)
def execute(self, processor):
if processor.condition_passed():
rotated = ror(processor.registers.get(self.m), 32, self.rotation)
processor.registers.set(
self.d,
add(processor.registers.get(self.n), sign_extend(lower_chunk(rotated, 8), 8, 32), 32)
)
def thumb_expand_imm_c(imm12: int, carry_in: int):
if substring(imm12, 11, 10) == 0b00:
imm_9_8 = substring(imm12, 9, 8)
lower_byte = lower_chunk(imm12, 8)
if imm_9_8 == 0b00:
imm32 = lower_byte
elif imm_9_8 == 0b01:
if lower_byte == 0b00000000:
print('unpredictable')
imm32 = chain(lower_byte, lower_byte, 16)
elif imm_9_8 == 0b10:
if lower_byte == 0b00000000:
print('unpredictable')
imm32 = chain(lower_byte, lower_byte << 8, 24)
elif imm_9_8 == 0b11:
if lower_byte == 0b00000000:
print('unpredictable')
imm32 = chain(
lower_byte,
chain(lower_byte, chain(lower_byte, lower_byte, 8), 16), 24)
carry_out = carry_in
else:
unrotated_value = chain(1, substring(imm12, 6, 0), 7)
imm32, carry_out = ror_c(unrotated_value, 8, substring(imm12, 11, 7))
return imm32, carry_out
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset_addr = bits_add(processor.registers.get(
self.n), self.imm32, 32) if self.add else bits_sub(
processor.registers.get(self.n), self.imm32, 32)
address = offset_addr if self.index else processor.registers.get(
self.n)
if have_lpae() and lower_chunk(address, 3) == 0b000:
if processor.big_endian():
data = chain(processor.registers.get(self.t),
processor.registers.get(self.t2), 32)
else:
data = chain(processor.registers.get(self.t2),
processor.registers.get(self.t), 32)
processor.mem_a_set(address, 8, data)
else:
processor.mem_a_set(address, 4,
processor.registers.get(self.t))
processor.mem_a_set(bits_add(address, 4, 32), 4,
processor.registers.get(self.t2))
if self.wback:
processor.registers.set(self.n, offset_addr)
def execute(self, processor):
if processor.condition_passed():
n = processor.registers.get(self.n)
m = processor.registers.get(self.m)
diff1 = substring(n, 7, 0) - substring(m, 7, 0)
diff2 = substring(n, 15, 8) - substring(m, 15, 8)
diff3 = substring(n, 23, 16) - substring(m, 23, 16)
diff4 = substring(n, 31, 24) - substring(m, 31, 24)
d = set_substring(0, 7, 0, lower_chunk(diff1, 8))
d = set_substring(d, 15, 8, lower_chunk(diff2, 8))
d = set_substring(d, 23, 16, lower_chunk(diff3, 8))
d = set_substring(d, 31, 24, lower_chunk(diff4, 8))
processor.registers.set(self.d, d)
ge = set_bit_at(0, 0, 0b1 if diff1 >= 0 else 0b0)
ge = set_bit_at(ge, 1, 0b1 if diff2 >= 0 else 0b0)
ge = set_bit_at(ge, 2, 0b1 if diff3 >= 0 else 0b0)
ge = set_bit_at(ge, 3, 0b1 if diff4 >= 0 else 0b0)
processor.registers.cpsr.ge = ge
def execute(self, processor):
shift_n = lower_chunk(processor.registers.get(self.s), 8)
shifted, carry = shift_c(processor.registers.get(self.m), 32, self.shift_t, shift_n, processor.registers.cpsr.c)
result = processor.registers.get(self.n) | shifted
processor.registers.set(self.d, result)
if self.setflags:
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = carry
def execute(self, processor):
if processor.condition_passed():
n = processor.registers.get(self.n)
m = processor.registers.get(self.m)
sum1 = substring(n, 7, 0) + substring(m, 7, 0)
sum2 = substring(n, 15, 8) + substring(m, 15, 8)
sum3 = substring(n, 23, 16) + substring(m, 23, 16)
sum4 = substring(n, 31, 24) + substring(m, 31, 24)
d = set_substring(0, 7, 0, lower_chunk(sum1, 8))
d = set_substring(d, 15, 8, lower_chunk(sum2, 8))
d = set_substring(d, 23, 16, lower_chunk(sum3, 8))
d = set_substring(d, 31, 24, lower_chunk(sum4, 8))
processor.registers.set(self.d, d)
ge = set_bit_at(0, 0, 0b1 if sum1 >= 0x100 else 0b0)
ge = set_bit_at(ge, 1, 0b1 if sum2 >= 0x100 else 0b0)
ge = set_bit_at(ge, 2, 0b1 if sum3 >= 0x100 else 0b0)
ge = set_bit_at(ge, 3, 0b1 if sum4 >= 0x100 else 0b0)
processor.registers.cpsr.ge = ge
def execute(self, processor):
shift_n = lower_chunk(processor.registers.get(self.s), 8)
shifted = shift(processor.registers.get(self.m), 32, self.shift_t,
shift_n, processor.registers.cpsr.c)
result, carry, overflow = add_with_carry(
processor.registers.get(self.n), bit_not(shifted, 32), 1)
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = carry
processor.registers.cpsr.v = overflow
def set_rmode(self, n, mode, value):
assert 0 <= n <= 14
if not self.is_secure() and mode == 0b10110:
print('unpredictable')
if not self.is_secure() and mode == 0b10001 and self.nsacr.rfr:
print('unpredictable')
if n == 13 and bits_ops.lower_chunk(
value, 2) != 0b00 and self.current_instr_set() != InstrSet.ARM:
print('unpredictable')
self._R[self.look_up_rname(n, mode)] = value
def execute(self, processor):
if processor.condition_passed():
offset_addr = bits_add(processor.registers.get(
self.n), self.imm32, 32) if self.add else bits_sub(
processor.registers.get(self.n), self.imm32, 32)
address = offset_addr if self.index else processor.registers.get(
self.n)
processor.mem_u_set(
address, 1, lower_chunk(processor.registers.get(self.t), 8))
if self.wback:
processor.registers.set(self.n, offset_addr)
def execute(self, processor):
if processor.condition_passed():
if processor.registers.get(self.m) == 0:
if processor.integer_zero_divide_trapping_enabled():
processor.generate_integer_zero_divide()
else:
result = 0
else:
result = int(
processor.registers.get(self.n) /
processor.registers.get(self.m))
processor.registers.set(self.d, lower_chunk(result, 32))
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset_addr = bits_add(processor.registers.get(
self.n), self.imm32, 32) if self.add else bits_sub(
processor.registers.get(self.n), self.imm32, 32)
address = offset_addr if self.index else processor.registers.get(
self.n)
if processor.unaligned_support() or lower_chunk(address,
1) == 0b0:
processor.mem_u_set(
address, 2,
lower_chunk(processor.registers.get(self.t), 16))
else:
processor.mem_u_set(address, 2, 0x0000) # unknown
if self.wback:
processor.registers.set(self.n, offset_addr)
def execute(self, processor):
if processor.condition_passed():
offset_addr = bits_add(processor.registers.get(
self.n), self.imm32, 32) if self.add else bits_sub(
processor.registers.get(self.n), self.imm32, 32)
address = offset_addr if self.index else processor.registers.get(
self.n)
data = processor.mem_u_get(address, 4)
if self.wback:
processor.registers.set(self.n, offset_addr)
if self.t == 15:
if lower_chunk(address, 2) == 0b00:
processor.load_write_pc(data)
else:
print('unpredictable')
elif processor.unaligned_support() or lower_chunk(address,
2) == 0b00:
processor.registers.set(self.t, data)
else:
processor.registers.set(
self.t, ror(data, 32, 8 * lower_chunk(address, 2)))
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), 32,
self.shift_t, self.shift_n,
processor.registers.cpsr.c)
address = add(processor.registers.get(self.n), offset, 32)
data = processor.mem_u_get(address, 4)
if self.t == 15:
if lower_chunk(address, 2) == 0b00:
processor.load_write_pc(address)
else:
print('unpredictable')
elif processor.unaligned_support() or lower_chunk(address,
2) == 0b00:
processor.registers.set(self.t, data)
else:
processor.registers.set(self.t, 0x00000000) # unknown
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
address = processor.registers.get(self.n)
if processor.exclusive_monitors_pass(address, 1):
processor.mem_a_set(address, 1, lower_chunk(processor.registers.get(self.t), 8))
processor.registers.set(self.d, 0b00000000000000000000000000000000)
else:
processor.registers.set(self.d, 0b00000000000000000000000000000001)
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(self.m), 32, self.shift_t, self.shift_n,
processor.registers.cpsr.c)
offset_addr = bits_add(processor.registers.get(self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = offset_addr if self.index else processor.registers.get(self.n)
processor.mem_u_set(address, 1, lower_chunk(processor.registers.get(self.t), 8))
if self.wback:
processor.registers.set(self.n, offset_addr)
def execute(self, processor):
if processor.condition_passed():
if processor.registers.current_mode_is_hyp():
print('unpredictable')
else:
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = processor.registers.get(self.m) if self.register_form else self.imm32
offset_addr = bits_add(processor.registers.get(self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = processor.registers.get(self.n) if self.post_index else offset_addr
if processor.unaligned_support() or not bit_at(address, 0):
processor.mem_u_unpriv_set(address, 2, lower_chunk(processor.registers.get(self.t), 16))
else:
processor.mem_u_unpriv_set(address, 2, 0x0000) # unknown
if self.post_index:
processor.registers.set(self.n, offset_addr)
def execute(self, processor):
if processor.condition_passed():
if processor.registers.current_mode_is_hyp():
print('unpredictable')
else:
try:
processor.null_check_if_thumbee(self.n)
except EndOfInstruction:
pass
else:
offset = shift(processor.registers.get(
self.m), 32, self.shift_t, self.shift_n,
processor.registers.cpsr.c
) if self.register_form else self.imm32
offset_addr = bits_add(processor.registers.get(
self.n), offset, 32) if self.add else bits_sub(
processor.registers.get(self.n), offset, 32)
address = processor.registers.get(
self.n) if self.post_index else offset_addr
processor.mem_u_unpriv_set(
address, 1,
lower_chunk(processor.registers.get(self.t), 8))
if self.post_index:
processor.registers.set(self.n, offset_addr)
def execute(self, processor):
if processor.condition_passed():
processor.call_supervisor(lower_chunk(self.imm32, 16))
def execute(self, processor):
if processor.condition_passed():
rotated = ror(processor.registers.get(self.m), 32, self.rotation)
processor.registers.set(self.d, lower_chunk(rotated, 16))
def execute(self, processor):
if processor.condition_passed():
m = processor.registers.get(self.m)
result = set_substring(0, 31, 8, sign_extend(lower_chunk(m, 8), 8, 24))
result = set_substring(result, 7, 0, substring(m, 15, 8))
processor.registers.set(self.d, result)
def from_bitarray(instr, processor):
imm32 = lower_chunk(instr, 24)
return SvcA1(instr, imm32=imm32)
def lsl_c(x, x_len, shift):
assert shift > 0
extended_x = x << shift
return bits_ops.lower_chunk(extended_x, x_len), (extended_x >> x_len) & 1
