def __init__(self, chanif, channels, rx_synchronizer=None, fine_ts_width=3, full_ts_width=63): if rx_synchronizer is None: rx_synchronizer = GenericRXSynchronizer() self.submodules += rx_synchronizer self.submodules.link_layer = link_layer.LinkLayer( chanif.encoder, chanif.decoders) self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready) link_layer_sync = SimpleNamespace( tx_aux_frame=self.link_layer.tx_aux_frame, tx_aux_data=self.link_layer.tx_aux_data, tx_aux_ack=self.link_layer.tx_aux_ack, tx_rt_frame=self.link_layer.tx_rt_frame, tx_rt_data=self.link_layer.tx_rt_data, rx_aux_stb=rx_synchronizer.resync(self.link_layer.rx_aux_stb), rx_aux_frame=rx_synchronizer.resync(self.link_layer.rx_aux_frame), rx_aux_frame_perm=rx_synchronizer.resync( self.link_layer.rx_aux_frame_perm), rx_aux_data=rx_synchronizer.resync(self.link_layer.rx_aux_data), rx_rt_frame=rx_synchronizer.resync(self.link_layer.rx_rt_frame), rx_rt_frame_perm=rx_synchronizer.resync( self.link_layer.rx_rt_frame_perm), rx_rt_data=rx_synchronizer.resync(self.link_layer.rx_rt_data)) self.submodules.link_stats = link_layer.LinkLayerStats( link_layer_sync, "rtio") self.submodules.rt_packet = ClockDomainsRenamer("rtio")( rt_packet_satellite.RTPacketSatellite(link_layer_sync)) self.submodules.ios = rt_ios_satellite.IOS(self.rt_packet, channels, fine_ts_width, full_ts_width) self.submodules.rt_errors = rt_errors_satellite.RTErrorsSatellite( self.rt_packet, self.ios) self.clock_domains.cd_rio = ClockDomain() self.clock_domains.cd_rio_phy = ClockDomain() self.comb += [ self.cd_rio.clk.eq(ClockSignal("rtio")), self.cd_rio.rst.eq(self.rt_packet.reset), self.cd_rio_phy.clk.eq(ClockSignal("rtio")), self.cd_rio_phy.rst.eq(self.rt_packet.reset_phy), ] self.submodules.aux_controller = aux_controller.AuxController( self.link_layer)
def __init__(self, chanif, channels, rx_synchronizer=None, fine_ts_width=3, lane_count=8, fifo_depth=128): self.reset = CSRStorage(reset=1) self.reset_phy = CSRStorage(reset=1) self.clock_domains.cd_rio = ClockDomain() self.clock_domains.cd_rio_phy = ClockDomain() self.comb += [ self.cd_rio.clk.eq(ClockSignal("rtio")), self.cd_rio_phy.clk.eq(ClockSignal("rtio")) ] reset = Signal() reset_phy = Signal() reset.attr.add("no_retiming") reset_phy.attr.add("no_retiming") self.sync += [ reset.eq(self.reset.storage), reset_phy.eq(self.reset_phy.storage) ] self.specials += [ AsyncResetSynchronizer(self.cd_rio, reset), AsyncResetSynchronizer(self.cd_rio_phy, reset_phy) ] self.submodules.link_layer = link_layer.LinkLayer( chanif.encoder, chanif.decoders) self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready) if rx_synchronizer is None: rx_synchronizer = GenericRXSynchronizer() self.submodules += rx_synchronizer link_layer_sync = SimpleNamespace( tx_aux_frame=self.link_layer.tx_aux_frame, tx_aux_data=self.link_layer.tx_aux_data, tx_aux_ack=self.link_layer.tx_aux_ack, tx_rt_frame=self.link_layer.tx_rt_frame, tx_rt_data=self.link_layer.tx_rt_data, rx_aux_stb=rx_synchronizer.resync(self.link_layer.rx_aux_stb), rx_aux_frame=rx_synchronizer.resync(self.link_layer.rx_aux_frame), rx_aux_frame_perm=rx_synchronizer.resync( self.link_layer.rx_aux_frame_perm), rx_aux_data=rx_synchronizer.resync(self.link_layer.rx_aux_data), rx_rt_frame=rx_synchronizer.resync(self.link_layer.rx_rt_frame), rx_rt_frame_perm=rx_synchronizer.resync( self.link_layer.rx_rt_frame_perm), rx_rt_data=rx_synchronizer.resync(self.link_layer.rx_rt_data)) self.submodules.link_stats = link_layer.LinkLayerStats( link_layer_sync, "rtio") self.submodules.rt_packet = ClockDomainsRenamer("rtio")( rt_packet_satellite.RTPacketSatellite(link_layer_sync)) self.comb += self.rt_packet.reset.eq(self.cd_rio.rst) coarse_ts = Signal(64 - fine_ts_width) self.sync.rtio += \ If(self.rt_packet.tsc_load, coarse_ts.eq(self.rt_packet.tsc_load_value) ).Else( coarse_ts.eq(coarse_ts + 1) ) self.comb += self.rt_packet.cri.counter.eq(coarse_ts << fine_ts_width) self.submodules.outputs = ClockDomainsRenamer("rio")(SED( channels, fine_ts_width, "sync", lane_count=lane_count, fifo_depth=fifo_depth, enable_spread=False, report_buffer_space=True, interface=self.rt_packet.cri)) self.comb += self.outputs.coarse_timestamp.eq(coarse_ts) self.sync.rtio += self.outputs.minimum_coarse_timestamp.eq(coarse_ts + 16) self.submodules.inputs = ClockDomainsRenamer("rio")(InputCollector( channels, fine_ts_width, "sync", interface=self.rt_packet.cri)) self.comb += self.inputs.coarse_timestamp.eq(coarse_ts) self.submodules.rt_errors = rt_errors_satellite.RTErrorsSatellite( self.rt_packet, self.outputs) self.submodules.aux_controller = aux_controller.AuxController( self.link_layer)
def __init__(self, tsc, chanif, rx_synchronizer=None): self.reset = CSRStorage(reset=1) self.reset_phy = CSRStorage(reset=1) self.tsc_loaded = CSR() # master interface in the rtio domain self.cri = cri.Interface() self.async_errors = Record(async_errors_layout) self.clock_domains.cd_rio = ClockDomain() self.clock_domains.cd_rio_phy = ClockDomain() self.comb += [ self.cd_rio.clk.eq(ClockSignal("rtio")), self.cd_rio_phy.clk.eq(ClockSignal("rtio")) ] reset = Signal() reset_phy = Signal() reset.attr.add("no_retiming") reset_phy.attr.add("no_retiming") self.sync += [ reset.eq(self.reset.storage), reset_phy.eq(self.reset_phy.storage) ] self.specials += [ AsyncResetSynchronizer(self.cd_rio, reset), AsyncResetSynchronizer(self.cd_rio_phy, reset_phy) ] self.submodules.link_layer = link_layer.LinkLayer( chanif.encoder, chanif.decoders) self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready) if rx_synchronizer is None: rx_synchronizer = GenericRXSynchronizer() self.submodules += rx_synchronizer link_layer_sync = SimpleNamespace( tx_aux_frame=self.link_layer.tx_aux_frame, tx_aux_data=self.link_layer.tx_aux_data, tx_aux_ack=self.link_layer.tx_aux_ack, tx_rt_frame=self.link_layer.tx_rt_frame, tx_rt_data=self.link_layer.tx_rt_data, rx_aux_stb=rx_synchronizer.resync(self.link_layer.rx_aux_stb), rx_aux_frame=rx_synchronizer.resync(self.link_layer.rx_aux_frame), rx_aux_frame_perm=rx_synchronizer.resync( self.link_layer.rx_aux_frame_perm), rx_aux_data=rx_synchronizer.resync(self.link_layer.rx_aux_data), rx_rt_frame=rx_synchronizer.resync(self.link_layer.rx_rt_frame), rx_rt_frame_perm=rx_synchronizer.resync( self.link_layer.rx_rt_frame_perm), rx_rt_data=rx_synchronizer.resync(self.link_layer.rx_rt_data)) self.submodules.link_stats = link_layer.LinkLayerStats( link_layer_sync, "rtio") self.submodules.rt_packet = ClockDomainsRenamer("rtio")( rt_packet_satellite.RTPacketSatellite(link_layer_sync, interface=self.cri)) self.comb += self.rt_packet.reset.eq(self.cd_rio.rst) self.comb += [ tsc.load.eq(self.rt_packet.tsc_load), tsc.load_value.eq(self.rt_packet.tsc_load_value) ] ps_tsc_load = PulseSynchronizer("rtio", "sys") self.submodules += ps_tsc_load self.comb += ps_tsc_load.i.eq(self.rt_packet.tsc_load) self.sync += [ If(self.tsc_loaded.re, self.tsc_loaded.w.eq(0)), If(ps_tsc_load.o, self.tsc_loaded.w.eq(1)) ] self.submodules.rt_errors = rt_errors_satellite.RTErrorsSatellite( self.rt_packet, tsc, self.async_errors)