def __init__(self, nwords): self.ttl0 = Signal() self.ttl1 = Signal() self.transceivers = DummyTransceiverPair(nwords) self.submodules.master = DRTIOMaster(self.transceivers.alice, fine_ts_width=0) self.submodules.master_ki = rtio.KernelInitiator(self.master.cri) rx_synchronizer = DummyRXSynchronizer() self.submodules.phy0 = ttl_simple.Output(self.ttl0) self.submodules.phy1 = ttl_simple.Output(self.ttl1) self.submodules.phy2 = SimpleIOPHY(512, 32) # test wide output data rtio_channels = [ rtio.Channel.from_phy(self.phy0), rtio.Channel.from_phy(self.phy1), rtio.Channel.from_phy(self.phy2), ] self.submodules.satellite = DRTIOSatellite(self.transceivers.bob, rtio_channels, rx_synchronizer, lane_count=4, fifo_depth=8, fine_ts_width=0) self.satellite.reset.storage.reset = 0 self.satellite.reset.storage_full.reset = 0 self.satellite.reset_phy.storage.reset = 0 self.satellite.reset_phy.storage_full.reset = 0
def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) platform = self.platform self.platform.add_extension(_sma_spi) rtio_channels = [] phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) ams101_dac = self.platform.request("ams101_dac", 0) phy = ttl_simple.Output(ams101_dac.ldac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = spi2.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=4)) phy = spi2.SPIMaster(self.platform.request("sma_spi")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=128)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, *args, **kwargs): _MasterBase.__init__(self, *args, **kwargs) platform = self.platform platform.add_extension(_dio("eem0")) rtio_channels = [] phy = ttl_simple.Output(platform.request("user_led", 0)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for sc in self.sfp_ctl: phy = ttl_simple.Output(sc.led) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(8): pads = platform.request("eem0", i) phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self): platform = self.platform platform.add_extension(nist_qc2.fmc_adapter_io) rtio_channels = [] clock_generators = [] # All TTL channels are In+Out capable for i in range(40): phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) # CLK0, CLK1 are for clock generators, on backplane SMP connectors for i in range(2): phy = ttl_simple.ClockGen(platform.request("clkout", i)) self.submodules += phy clock_generators.append(rtio.Channel.from_phy(phy)) # user SMA on KC705 board phy = ttl_serdes_7series.InOut_8X( platform.request("user_sma_gpio_n_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) # AMS101 DAC on KC705 XADC header - optional ams101_dac = self.platform.request("ams101_dac", 0) phy = ttl_simple.Output(ams101_dac.ldac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) # add clock generators after TTLs rtio_channels += clock_generators phy = spi2.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) for i in range(4): phy = spi2.SPIMaster(self.platform.request("spi", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128)) for backplane_offset in range(2): phy = dds.AD9914(platform.request("dds", backplane_offset), 12, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, description, hw_rev=None, **kwargs): if hw_rev is None: hw_rev = description["hw_rev"] self.class_name_override = description["variant"] StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) self.config["SI5324_AS_SYNTHESIZER"] = None self.config["RTIO_FREQUENCY"] = "{:.1f}".format( description["rtio_frequency"] / 1e6) if "ext_ref_frequency" in description: self.config["SI5324_EXT_REF"] = None self.config["EXT_REF_FREQUENCY"] = "{:.1f}".format( description["ext_ref_frequency"] / 1e6) if hw_rev == "v1.0": # EEM clock fan-out from Si5324, not MMCX self.comb += self.platform.request("clk_sel").eq(1) has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"]) if has_grabber: self.grabber_csr_group = [] self.rtio_channels = [] eem_7series.add_peripherals(self, description["peripherals"]) if hw_rev in ("v1.0", "v1.1"): for i in (1, 2): print("SFP LED at RTIO channel 0x{:06x}".format( len(self.rtio_channels))) sfp_ctl = self.platform.request("sfp_ctl", i) phy = ttl_simple.Output(sfp_ctl.led) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) if hw_rev == "v2.0": for i in (1, 2): print("USER LED at RTIO channel 0x{:06x}".format( len(self.rtio_channels))) phy = ttl_simple.Output(self.platform.request("user_led", i)) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.rtio_channels.append(rtio.LogChannel()) self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"]) if has_grabber: self.config["HAS_GRABBER"] = None self.add_csr_group("grabber", self.grabber_csr_group) for grabber in self.grabber_csr_group: self.platform.add_false_path_constraints( self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
def __init__(self, *args, **kwargs): _SatelliteBase.__init__(self, *args, **kwargs) self.rtio_channels = [] phy = ttl_simple.Output(self.platform.request("user_led", 0)) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(1, 3): phy = ttl_simple.Output(self.platform.request("sfp_ctl", i).led) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) eem.DIO.add_std(self, 0, ttl_serdes_7series.InOut_8X, ttl_serdes_7series.InOut_8X) self.add_rtio(self.rtio_channels)
def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) platform = self.platform platform.add_extension(_dio("eem0")) platform.add_extension(_dio("eem1")) platform.add_extension(_dio("eem2")) # platform.add_extension(_urukul("eem3", "eem4")) # platform.add_extension(_novogorny("eem5")) # EEM clock fan-out from Si5324, not MMCX self.comb += platform.request("clk_sel").eq(1) rtio_channels = [] for eem in "eem0 eem1 eem2".split(): for i in range(8): phy = ttl_serdes_7series.Output_8X(platform.request(eem, i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in (1, 2): sfp_ctl = platform.request("sfp_ctl", i) phy = ttl_simple.Output(sfp_ctl.led) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, hw_rev=None, **kwargs): if hw_rev is None: hw_rev = "v1.1" _StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) self.config["SI5324_AS_SYNTHESIZER"] = None self.config["RTIO_FREQUENCY"] = "125.0" if hw_rev == "v1.0": # EEM clock fan-out from Si5324, not MMCX self.comb += self.platform.request("clk_sel").eq(1) self.rtio_channels = [] self.grabber_csr_group = [] eem.DIO.add_std(self, 4, ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) eem.Urukul.add_std(self, 3, 2, ttl_serdes_7series.Output_8X) eem.Sampler.add_std(self, 6, 5, ttl_serdes_7series.Output_8X) eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X) eem.Grabber.add_std(self, 1, 0) for i in (1, 2): sfp_ctl = self.platform.request("sfp_ctl", i) phy = ttl_simple.Output(sfp_ctl.led) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.rtio_channels.append(rtio.LogChannel()) self.add_rtio(self.rtio_channels) self.config["HAS_GRABBER"] = None self.add_csr_group("grabber", self.grabber_csr_group) self.platform.add_false_path_constraints( self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
def __init__(self, hw_rev=None, **kwargs): if hw_rev is None: hw_rev = "v1.1" _StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) self.config["SI5324_AS_SYNTHESIZER"] = None # self.config["SI5324_EXT_REF"] = None self.config["RTIO_FREQUENCY"] = "125.0" if hw_rev == "v1.0": # EEM clock fan-out from Si5324, not MMCX self.comb += self.platform.request("clk_sel").eq(1) self.rtio_channels = [] eem.DIO.add_std(self, 5, ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) eem.DIO.add_std(self, 6, ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) eem.Urukul.add_std(self, 0, 1, ttl_serdes_7series.Output_8X) eem.Sampler.add_std(self, 2, 3, ttl_serdes_7series.Output_8X) eem.Zotino.add_std(self, 4, ttl_serdes_7series.Output_8X) for i in (1, 2): sfp_ctl = self.platform.request("sfp_ctl", i) phy = ttl_simple.Output(sfp_ctl.led) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.rtio_channels.append(rtio.LogChannel()) self.add_rtio(self.rtio_channels)
def __init__(self, hw_rev=None, *args, **kwargs): if hw_rev is None: hw_rev = "v1.1" _SatelliteBase.__init__(self, rtio_clk_freq=125e6, hw_rev=hw_rev, *args, **kwargs) self.rtio_channels = [] eem.DIO.add_std(self, 0, ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) eem.DIO.add_std(self, 1, ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) eem.DIO.add_std(self, 2, ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X) eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X) eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X) for i in (0, 1): phy = ttl_simple.Output(self.platform.request("user_led", i)) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X) self.add_rtio(self.rtio_channels)
def __init__(self, **kwargs): self.ttl0 = Signal() self.ttl1 = Signal() self.submodules.phy0 = ttl_simple.Output(self.ttl0) self.submodules.phy1 = ttl_simple.Output(self.ttl1) rtio_channels = [ rtio.Channel.from_phy(self.phy0), rtio.Channel.from_phy(self.phy1) ] self.submodules.sed = SED(rtio_channels, 0, "sync", **kwargs) self.sync += [ self.sed.coarse_timestamp.eq(self.sed.coarse_timestamp + 1), self.sed.minimum_coarse_timestamp.eq(self.sed.coarse_timestamp + 16) ]
def __init__(self, ws): self.ttl0 = Signal() self.ttl1 = Signal() self.submodules.phy0 = ttl_simple.Output(self.ttl0) self.submodules.phy1 = ttl_simple.Output(self.ttl1) rtio_channels = [ rtio.Channel.from_phy(self.phy0), rtio.Channel.from_phy(self.phy1) ] sequence = encode_sequence(test_writes_full_stack, ws) bus = wishbone.Interface(ws * 8) self.submodules.memory = wishbone.SRAM(256, init=sequence, bus=bus) self.submodules.dut = dma.DMA(bus) self.submodules.rtio = rtio.Core(rtio_channels) self.comb += self.dut.cri.connect(self.rtio.cri)
def __init__(self, *args, **kwargs): _MasterBase.__init__(self, *args, **kwargs) self.rtio_channels = [] phy = ttl_simple.Output(self.platform.request("user_led", 0)) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) for sc in self.sfp_ctl: phy = ttl_simple.Output(sc.led) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) eem.DIO.add_std(self, 0, ttl_serdes_7series.InOut_8X, ttl_serdes_7series.InOut_8X) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.rtio_channels.append(rtio.LogChannel()) self.add_rtio(self.rtio_channels)
def __init__(self, nwords): self.ttl0 = Signal() self.ttl1 = Signal() self.transceivers = DummyTransceiverPair(nwords) self.submodules.master = DRTIOMaster(self.transceivers.alice) self.submodules.master_ki = rtio.KernelInitiator(self.master.cri) rx_synchronizer = DummyRXSynchronizer() self.submodules.phy0 = ttl_simple.Output(self.ttl0) self.submodules.phy1 = ttl_simple.Output(self.ttl1) self.submodules.phy2 = SimpleIOPHY(512, 32) # test wide output data rtio_channels = [ rtio.Channel.from_phy(self.phy0, ofifo_depth=4), rtio.Channel.from_phy(self.phy1, ofifo_depth=4), rtio.Channel.from_phy(self.phy2, ofifo_depth=4), ] self.submodules.satellite = DRTIOSatellite(self.transceivers.bob, rtio_channels, rx_synchronizer)
def __init__(self): self.ttl0 = Signal() self.ttl1 = Signal() self.ttl2 = Signal() self.submodules.phy0 = ttl_simple.Output(self.ttl0) self.submodules.phy1 = ttl_simple.Output(self.ttl1) self.submodules.phy2 = ttl_simple.Output(self.ttl2) self.phy2.rtlink.o.enable_replace = False self.submodules.phy3 = BusyPHY() rtio_channels = [ rtio.Channel.from_phy(self.phy0), rtio.Channel.from_phy(self.phy1), rtio.Channel.from_phy(self.phy2), rtio.Channel.from_phy(self.phy3), ] self.submodules.output_driver = output_driver.OutputDriver( rtio_channels, 0, LANE_COUNT, 4 * LANE_COUNT)
def __init__(self, *args, **kwargs): _SatelliteBase.__init__(self, *args, **kwargs) self.rtio_channels = [] phy = ttl_simple.Output(self.platform.request("user_led", 0)) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) # matches Tester EEM numbers eem.DIO.add_std(self, 5, ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) self.add_rtio(self.rtio_channels)
def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) self.config["SI5324_AS_SYNTHESIZER"] = None self.config["RTIO_FREQUENCY"] = "125.0" platform = self.platform platform.add_extension(_urukul("eem1", "eem0")) platform.add_extension(_dio("eem2")) platform.add_extension(_dio("eem3")) platform.add_extension(_dio("eem4")) platform.add_extension(_dio("eem5")) platform.add_extension(_dio("eem6")) # EEM clock fan-out from Si5324, not MMCX self.comb += platform.request("clk_sel").eq(1) # EEM2-6: TTL rtio_channels = [] for i in range(40): eem_offset, port = divmod(i, 8) pads = platform.request("eem{}".format(2 + eem_offset), port) phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) # EEM0, EEM1: Urukul phy = spi2.SPIMaster(self.platform.request("eem1_spi_p"), self.platform.request("eem1_spi_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) pads = platform.request("eem1_dds_reset") self.specials += DifferentialOutput(0, pads.p, pads.n) for signal in "io_update sw0 sw1 sw2 sw3".split(): pads = platform.request("eem1_{}".format(signal)) phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in (1, 2): sfp_ctl = platform.request("sfp_ctl", i) phy = ttl_simple.Output(sfp_ctl.led) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) # Adding a sniffer on the kernel_cpu ibus self.submodules += Sniffer( self.platform.request("wishbone_kernel_ibus", 0), self.kernel_cpu.cpu.ibus) # Adding a sniffer on the kernel_cpu dbus self.submodules += Sniffer( self.platform.request("wishbone_kernel_dbus", 0), self.kernel_cpu.cpu.dbus) self.add_hal_interface() # RTIO Channels self.rtio_channels = [] quantum_cmd_out = ttl_simple.Output( self.platform.request("quantum_cmd", 0)) self.submodules += quantum_cmd_out quantum_valid_out = ttl_simple.Output( self.platform.request("quantum_valid", 0)) self.submodules += quantum_valid_out self.rtio_channels.append(rtio.Channel.from_phy(quantum_cmd_out)) self.rtio_channels.append(rtio.Channel.from_phy(quantum_valid_out)) self.rtio_channels.append(rtio.LogChannel()) self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.add_rtio(self.rtio_channels) # self.config["HAS_RTIO_LOG"] = None self.submodules.emulator = Emulator( pads=self.platform.request("sdram_backdoor")) self.csr_devices.append("emulator") # This value represents the start address of the <.callMain>: # function in the runtime.obj. The entry point 0x40000000 would # otherwise perform quite a long clearing of the .bss section that # is still clean in this case. self.config["second_stage_offset"] = 0x40001034
def __init__(self, *args, **kwargs): _SatelliteBase.__init__(self, *args, **kwargs) platform = self.platform platform.add_extension(_dio("eem0")) rtio_channels = [] phy = ttl_simple.Output(platform.request("user_led", 0)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(1, 3): phy = ttl_simple.Output(platform.request("sfp_ctl", i).led) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(8): pads = platform.request("eem0", i) phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_rtio(rtio_channels)
def __init__(self, cpu_type="or1k", **kwargs): _NIST_Ions.__init__(self, cpu_type, **kwargs) platform = self.platform platform.add_extension(nist_qc1.fmc_adapter_io) self.comb += [ platform.request("ttl_l_tx_en").eq(1), platform.request("ttl_h_tx_en").eq(1) ] rtio_channels = [] for i in range(2): phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) for i in range(15): phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) phy = ttl_simple.ClockGen(platform.request("ttl", 15)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_DDS_COUNT"] = 1 self.config["DDS_CHANNELS_PER_BUS"] = 8 self.config["DDS_AD9858"] = True phy = dds.AD9858(platform.request("dds"), 8) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4)) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels) assert self.rtio.fine_ts_width <= 3 self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
def __init__(self, nwords): self.ttl0 = Signal() self.ttl1 = Signal() self.transceivers = DummyTransceiverPair(nwords) self.submodules.tsc_master = rtio.TSC("async") self.submodules.master = DRTIOMaster(self.tsc_master, self.transceivers.alice) self.submodules.master_ki = rtio.KernelInitiator( self.tsc_master, self.master.cri) rx_synchronizer = DummyRXSynchronizer() self.submodules.phy0 = ttl_simple.Output(self.ttl0) self.submodules.phy1 = ttl_simple.Output(self.ttl1) self.submodules.phy2 = SimpleIOPHY(512, 32) # test wide output data rtio_channels = [ rtio.Channel.from_phy(self.phy0), rtio.Channel.from_phy(self.phy1), rtio.Channel.from_phy(self.phy2), ] self.submodules.tsc_satellite = rtio.TSC("sync") self.submodules.satellite = DRTIOSatellite(self.tsc_satellite, self.transceivers.bob, rx_synchronizer) self.satellite.reset.storage.reset = 0 self.satellite.reset.storage_full.reset = 0 self.satellite.reset_phy.storage.reset = 0 self.satellite.reset_phy.storage_full.reset = 0 self.submodules.satellite_rtio = SyncRTIO(self.tsc_satellite, rtio_channels, lane_count=4, fifo_depth=8) self.comb += [ self.satellite.cri.connect(self.satellite_rtio.cri), self.satellite.async_errors.eq(self.satellite_rtio.async_errors), ]
def __init__(self, hw_rev=None, **kwargs): if hw_rev is None: hw_rev = "v1.1" _StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) self.config["SI5324_AS_SYNTHESIZER"] = None # self.config["SI5324_EXT_REF"] = None self.config["RTIO_FREQUENCY"] = "125.0" if hw_rev == "v1.0": # EEM clock fan-out from Si5324, not MMCX self.comb += self.platform.request("clk_sel").eq(1) self.rtio_channels = [] # EEM0, EEM1: DIO eem.DIO.add_std(self, 0, ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) eem.DIO.add_std(self, 1, ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X) # EEM3/2: Sampler, EEM5/4: Urukul, EEM7/6: Urukul eem.SUServo.add_std(self, eems_sampler=(3, 2), eems_urukul0=(5, 4), eems_urukul1=(7, 6)) for i in (1, 2): sfp_ctl = self.platform.request("sfp_ctl", i) phy = ttl_simple.Output(sfp_ctl.led) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.rtio_channels.append(rtio.LogChannel()) self.add_rtio(self.rtio_channels) pads = self.platform.lookup_request("sampler3_adc_data_p") self.platform.add_false_path_constraints(pads.clkout, self.rtio_crg.cd_rtio.clk) self.platform.add_false_path_constraints(pads.clkout, self.crg.cd_sys.clk)
def __init__(self, hw_rev=None, **kwargs): if hw_rev is None: hw_rev = "v1.1" _MasterBase.__init__(self, hw_rev=hw_rev, **kwargs) self.rtio_channels = [] phy = ttl_simple.Output(self.platform.request("user_led", 0)) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) # matches Tester EEM numbers eem.DIO.add_std(self, 5, ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X) eem.Urukul.add_std(self, 1, 0, ttl_serdes_7series.Output_8X) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.rtio_channels.append(rtio.LogChannel()) self.add_rtio(self.rtio_channels)
def __init__(self, platform, cpu_type="or1k", **kwargs): _NIST_QCx.__init__(self, platform, cpu_type, **kwargs) platform.add_extension(nist_qc1.fmc_adapter_io) self.comb += [ platform.request("ttl_l_tx_en").eq(1), platform.request("ttl_h_tx_en").eq(1) ] rtio_channels = [] for i in range(2): phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) for i in range(15): phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Inout(platform.request("user_sma_gpio_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels)) phy = ttl_simple.ClockGen(platform.request("ttl", 15)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels)) self.add_constant("DDS_CHANNEL_COUNT", 8) self.add_constant("DDS_AD9858") phy = dds.AD9858(platform.request("dds"), 8) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4)) self.add_rtio(rtio_channels)
def __init__(self, platform, cpu_type="or1k", **kwargs): _NIST_QCx.__init__(self, platform, cpu_type, **kwargs) platform.add_extension(nist_qc2.fmc_adapter_io) rtio_channels = [] for i in range(16): if i == 14: # TTL14 is for the clock generator continue if i % 4 == 3: phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) else: phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Inout(platform.request("user_sma_gpio_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels)) phy = ttl_simple.ClockGen(platform.request("ttl", 14)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels)) self.add_constant("DDS_CHANNEL_COUNT", 11) self.add_constant("DDS_AD9914") self.add_constant("DDS_ONEHOT_SEL") phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4)) self.add_rtio(rtio_channels)
def __init__(self, **kwargs): SatelliteBase.__init__(self, **kwargs) platform = self.platform self.submodules += RTMUARTForward(platform) rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 0) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 1) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_rtio(rtio_channels)
def __init__(self, jdcg_type, **kwargs): SatelliteBase.__init__(self, 150e6, identifier_suffix="." + jdcg_type, **kwargs) platform = self.platform self.submodules += RTMUARTForward(platform) # RTM bitstream upload slave_fpga_cfg = self.platform.request("rtm_fpga_cfg") self.submodules.slave_fpga_cfg = gpio.GPIOTristate([ slave_fpga_cfg.cclk, slave_fpga_cfg.din, slave_fpga_cfg.done, slave_fpga_cfg.init_b, slave_fpga_cfg.program_b, ]) self.csr_devices.append("slave_fpga_cfg") self.config["SLAVE_FPGA_GATEWARE"] = 0x200000 self.rtio_channels = rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 0) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 1) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.jesd_crg = jesd204_tools.UltrascaleCRG( platform, use_rtio_clock=True) cls = { "sawg": JDCGSAWG, "pattern": JDCGPattern, "syncdds": JDCGSyncDDS }[jdcg_type] self.submodules.jdcg_0 = cls(platform, self.crg, self.jesd_crg, 0) self.submodules.jdcg_1 = cls(platform, self.crg, self.jesd_crg, 1) self.csr_devices.append("jesd_crg") self.csr_devices.append("jdcg_0") self.csr_devices.append("jdcg_1") self.config["HAS_JDCG"] = None self.add_csr_group("jdcg", ["jdcg_0", "jdcg_1"]) self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) rtio_channels.extend(rtio.Channel.from_phy(phy) for sawg in self.jdcg_0.sawgs + self.jdcg_1.sawgs for phy in sawg.phys) # FMC-VHDCI-EEM DIOs x 2 (all OUTPUTs) platform.add_connectors(fmcdio_vhdci_eem.connectors) output_4x = partial(ttl_serdes_ultrascale.Output, 4) eem.DIO.add_std(self, 0, output_4x, output_4x, iostandard=lambda eem: IOStandard("LVDS")) eem.DIO.add_std(self, 1, output_4x, output_4x, iostandard=lambda eem: IOStandard("LVDS")) # FMC-DIO-32ch-LVDS-a Direction Control Pins (via shift register) as TTLs x 3 platform.add_extension(fmcdio_vhdci_eem.io) print("fmcdio_vhdci_eem.[CLK, SER, LATCH] starting at RTIO channel 0x{:06x}" .format(len(rtio_channels))) fmcdio_dirctl = platform.request("fmcdio_dirctl", 0) fmcdio_dirctl_phys = [ ttl_simple.Output(fmcdio_dirctl.clk), ttl_simple.Output(fmcdio_dirctl.ser), ttl_simple.Output(fmcdio_dirctl.latch) ] for phy in fmcdio_dirctl_phys: self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) workaround_us_lvds_tristate(platform) self.add_rtio(rtio_channels) self.submodules.sysref_sampler = jesd204_tools.SysrefSampler( platform.request("amc_fpga_sysref", 0), self.rtio_tsc.coarse_ts) self.csr_devices.append("sysref_sampler") self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref) self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref) if jdcg_type == "syncdds": self.comb += [ self.jdcg_0.coarse_ts.eq(self.rtio_tsc.coarse_ts), self.jdcg_1.coarse_ts.eq(self.rtio_tsc.coarse_ts), ]
def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) platform = self.platform platform.add_extension(nist_clock.fmc_adapter_io) rtio_channels = [] for i in range(16): if i % 4 == 3: phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) else: phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(2): phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) ams101_dac = self.platform.request("ams101_dac", 0) phy = ttl_simple.Output(ams101_dac.ldac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.ClockGen(platform.request("la32_p")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = spi2.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=4)) for i in range(3): phy = spi2.SPIMaster(self.platform.request("spi", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=128)) phy = spi2.SPIMaster(platform.request("sdcard_spi_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=4)) phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, with_sawg, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, ident=artiq_version, ethmac_nrxslots=4, ethmac_ntxslots=4, **kwargs) AMPSoC.__init__(self) if with_sawg: warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.") platform = self.platform rtio_clk_freq = 150e6 self.submodules += Microscope(platform.request("serial", 1), self.clk_freq) # Si5324 used as a free-running oscillator, to avoid dependency on RTM. self.submodules.si5324_rst_n = gpio.GPIOOut( platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.config["SI5324_AS_SYNTHESIZER"] = None self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) self.comb += [ platform.request("sfp_tx_disable", i).eq(0) for i in range(2) ] self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("si5324_clkout"), data_pads=[platform.request("sfp", i) for i in range(2)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") drtio_csr_group = [] drtio_memory_group = [] drtio_cri = [] for i in range(2): core_name = "drtio" + str(i) memory_name = "drtio" + str(i) + "_aux" drtio_csr_group.append(core_name) drtio_memory_group.append(memory_name) core = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})( DRTIOMaster(self.drtio_transceiver.channels[i])) setattr(self.submodules, core_name, core) drtio_cri.append(core.cri) self.csr_devices.append(core_name) memory_address = self.mem_map["drtio_aux"] + 0x800 * i self.add_wb_slave(memory_address, 0x800, core.aux_controller.bus) self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtio", drtio_csr_group) self.add_memory_group("drtio_aux", drtio_memory_group) rtio_clk_period = 1e9 / rtio_clk_freq gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk, gth.rxoutclk) for gth in self.drtio_transceiver.gths[1:]: platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.rxoutclk) rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 0) self.comb += sma_io.direction.eq(1) phy = ttl_simple.Output(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 1) self.comb += sma_io.direction.eq(0) phy = ttl_simple.InOut(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") self.submodules.rtio_core = rtio.Core(rtio_channels, glbl_fine_ts_width=3) self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator() self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA( self.get_native_sdram_if())) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( [self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri] + drtio_cri) self.register_kernel_cpu_csrdevice("cri_con")
def __init__(self, with_sawg, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, ident=artiq_version, **kwargs) if with_sawg: warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.") platform = self.platform rtio_clk_freq = 150e6 self.submodules += Microscope(platform.request("serial", 1), self.clk_freq) self.submodules.rtio_clkmul = _RTIOClockMultiplier( platform, rtio_clk_freq) rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 0) self.comb += sma_io.direction.eq(1) phy = ttl_simple.Output(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sma_io = platform.request("sma_io", 1) self.comb += sma_io.direction.eq(0) phy = ttl_simple.InOut(sma_io.level) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("si5324_clkout"), data_pads=[platform.request("sfp", 0)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.drtio0 = rx0( DRTIOSatellite(self.drtio_transceiver.channels[0], rtio_channels, self.rx_synchronizer)) self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus) self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None self.add_csr_group("drtio", ["drtio0"]) self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), si5324_clkout_fabric=platform.request("si5324_clkout_fabric")) platform.add_platform_command( "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]", mmcm_ps=self.siphaser.mmcm_ps_output) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut( platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None rtio_clk_period = 1e9 / rtio_clk_freq gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk, gth.rxoutclk)