def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(self.platform)
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
# Only add MonInj core if there is anything to monitor
if any([len(c.probes) for c in rtio_channels]):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.rtio_crg.cd_rtio.clk)
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio_tsc, self.rtio_core.cri, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(self.platform)
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.rtio_crg.cd_rtio.clk)
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def add_rtio(self, rtio_channels):
# Only add MonInj core if there is anything to monitor
if any([len(c.probes) for c in rtio_channels]):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + self.drtio_cri,
enable_routing=True)
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio_tsc, self.cri_con.switch.slave,
self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk,
use_sma=False)
self.csr_devices.append("rtio_crg")
self.config["HAS_RTIO_CLOCK_SWITCH"] = None
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri])
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.rtio_crg.cd_rtio.clk)
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri,
self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
self.csr_devices.append("rtio_crg")
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.rtio_crg.cd_rtio.clk)
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
self.platform.add_platform_command(
"set_false_path -quiet "
"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
"-to [get_pins -filter {{REF_PIN_NAME == D}} "
"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
)
def add_rtio(self, rtio_channels):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri],
[self.local_io.cri] + self.drtio_cri,
mode="sync", enable_routing=True)
self.csr_devices.append("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
def add_rtio(self, rtio_channels):
# Only add MonInj core if there is anything to monitor
if any([len(c.probes) for c in rtio_channels]):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri],
[self.local_io.cri] + self.drtio_cri,
mode="sync", enable_routing=True)
self.csr_devices.append("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
def add_rtio(self, rtio_channels):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + self.drtio_cri,
enable_routing=True)
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
def add_rtio(self, rtio_channels):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(rtio_channels, glbl_fine_ts_width=3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + self.drtio_cri)
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_analyzer = rtio.Analyzer(self.cri_con.switch.slave,
self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def add_rtio(self, top, rtio_channels):
#self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
#self.csr_devices.append("rtio_crg")
#self.config["HAS_RTIO_CLOCK_SWITCH"] = None
top.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
top.submodules.rtio_core = rtio.Core(top.rtio_tsc,
rtio_channels,
lane_count=2)
#self.submodules.rtio_core = rtio.Core(rtio_channels)
top.csr_devices.append("rtio_core")
top.submodules.rtio = rtio.KernelInitiator(top.rtio_tsc)
#self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
# rtio.DMA(self.get_native_sdram_if()))
#self.register_kernel_cpu_csrdevice("rtio")
#self.register_kernel_cpu_csrdevice("rtio_dma")
top.submodules.cri_con = rtio.CRIInterconnectShared(
[top.rtio.cri], #self.rtio_dma.cri],
[top.rtio_core.cri])
#self.register_kernel_cpu_csrdevice("cri_con")
top.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
top.csr_devices.append("rtio_moninj")
def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG()
self.csr_devices.append("rtio_crg")
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.csr_devices.append("rtio")
self.submodules.dma = MAXI_DMA(bus=self.ps7.s_axi_acp,
user=self.ps7.s_axi_acp_user,
trigger_stb=self.evento_stb)
self.csr_devices.append("dma")
self.submodules.rtio_dma = DMA_KernelInitiator(engine=self.dma)
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri])
self.csr_devices.append("cri_con")
self.platform.add_false_path_constraints(self.rtio_crg.cd_rtio.clk)
self.comb += self.rtio_crg.cd_sys.clk.eq(self.cd_sys.clk)
def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
self.csr_devices.append("rtio_crg")
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri])
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.rtio_crg.cd_rtio.clk.attr.add("keep")
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.rtio_crg.cd_rtio.clk)
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio, self.rtio_core.cri.counter, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
RTMCommon.__init__(self)
add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
self.config["HMC830_REF"] = "100"
platform = self.platform
rtio_clk_freq = 150e6
self.submodules.si5324_rst_n = gpio.GPIOOut(
platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_SAYMA_REF"] = None
self.comb += [
platform.request("sfp_tx_disable", i).eq(0) for i in range(2)
]
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("dac_refclk", 0),
data_pads=[platform.request("sfp", i) for i in range(2)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.config["HMC7043_ENABLE_CLK1"] = None
drtio_csr_group = []
drtio_memory_group = []
drtio_cri = []
for i in range(2):
core_name = "drtio" + str(i)
memory_name = "drtio" + str(i) + "_aux"
drtio_csr_group.append(core_name)
drtio_memory_group.append(memory_name)
core = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})(
DRTIOMaster(self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
memory_address = self.mem_map["drtio_aux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, core.aux_controller.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_memory_group("drtio_aux", drtio_memory_group)
rtio_clk_period = 1e9 / rtio_clk_freq
gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk,
gth.rxoutclk)
for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gth.rxoutclk)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_crg")
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs + self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(rtio_channels,
glbl_fine_ts_width=3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + drtio_cri)
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
self.rtio_core.coarse_ts, self.ad9154_crg.jref)
self.csr_devices.append("sysref_sampler")
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
if with_sawg:
warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.")
platform = self.platform
rtio_clk_freq = 150e6
self.submodules += Microscope(platform.request("serial", 1),
self.clk_freq)
# Si5324 used as a free-running oscillator, to avoid dependency on RTM.
self.submodules.si5324_rst_n = gpio.GPIOOut(
platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.comb += [
platform.request("sfp_tx_disable", i).eq(0) for i in range(2)
]
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("si5324_clkout"),
data_pads=[platform.request("sfp", i) for i in range(2)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
drtio_csr_group = []
drtio_memory_group = []
drtio_cri = []
for i in range(2):
core_name = "drtio" + str(i)
memory_name = "drtio" + str(i) + "_aux"
drtio_csr_group.append(core_name)
drtio_memory_group.append(memory_name)
core = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})(
DRTIOMaster(self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
memory_address = self.mem_map["drtio_aux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, core.aux_controller.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_memory_group("drtio_aux", drtio_memory_group)
rtio_clk_period = 1e9 / rtio_clk_freq
gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk,
gth.rxoutclk)
for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gth.rxoutclk)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(rtio_channels,
glbl_fine_ts_width=3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + drtio_cri)
self.register_kernel_cpu_csrdevice("cri_con")
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
# forward RTM UART to second FTDI UART channel
serial_1 = platform.request("serial", 1)
serial_rtm = platform.request("serial_rtm")
self.comb += [
serial_1.tx.eq(serial_rtm.rx),
serial_rtm.tx.eq(serial_1.rx)
]
# RTM bitstream upload
slave_fpga_cfg = self.platform.request("rtm_fpga_cfg")
self.submodules.slave_fpga_cfg = gpio.GPIOTristate([
slave_fpga_cfg.cclk,
slave_fpga_cfg.din,
slave_fpga_cfg.done,
slave_fpga_cfg.init_b,
slave_fpga_cfg.program_b,
])
self.csr_devices.append("slave_fpga_cfg")
# self.config["HAS_SLAVE_FPGA"] = None
self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
# AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb")
serwb_phy_amc = serwb.phy.SERWBPHY(platform.device,
serwb_pads,
mode="master")
self.submodules.serwb_phy_amc = serwb_phy_amc
self.csr_devices.append("serwb_phy_amc")
serwb_core = serwb.core.SERWBCore(serwb_phy_amc,
int(self.clk_freq),
mode="slave")
self.submodules += serwb_core
self.add_wb_slave(self.mem_map["serwb"], 8192,
serwb_core.etherbone.wishbone.bus)
# RTIO
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_crg = AD9154CRG(platform)
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_crg")
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs + self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.clock_domains.cd_rtio = ClockDomain()
self.comb += [
self.cd_rtio.clk.eq(ClockSignal("jesd")),
self.cd_rtio.rst.eq(ResetSignal("jesd"))
]
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio_core.cri, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])
# forward RTM UART to second FTDI UART channel
serial_1 = platform.request("serial", 1)
serial_rtm = platform.request("serial_rtm")
self.comb += [
serial_1.tx.eq(serial_rtm.rx),
serial_rtm.tx.eq(serial_1.rx)
]
# RTM bitstream upload
rtm_fpga_cfg = platform.request("rtm_fpga_cfg")
self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg)
self.csr_devices.append("rtm_fpga_cfg")
# AMC/RTM serwb
serwb_pll = serwb.phy.SERWBPLL(125e6, 625e6, vco_div=2)
self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk)
self.submodules += serwb_pll
serwb_pads = platform.request("amc_rtm_serwb")
serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="master")
self.submodules.serwb_phy_amc = serwb_phy_amc
self.csr_devices.append("serwb_phy_amc")
serwb_phy_amc.serdes.cd_serwb_serdes.clk.attr.add("keep")
serwb_phy_amc.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes.clk, 40*1e9/serwb_pll.linerate),
platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_20x.clk, 2*1e9/serwb_pll.linerate),
platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk, 8*1e9/serwb_pll.linerate)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
serwb_phy_amc.serdes.cd_serwb_serdes.clk,
serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk)
serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=True)
self.submodules += serwb_core
self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
# RTIO
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_crg = AD9154CRG(platform)
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_crg")
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs +
self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.clock_domains.cd_rtio = ClockDomain()
self.comb += [
self.cd_rtio.clk.eq(ClockSignal("jesd")),
self.cd_rtio.rst.eq(ResetSignal("jesd"))
]
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def __init__(self, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
rtio_clk_freq = 150e6
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
self.config["SI5324_FREE_RUNNING"] = None
self.comb += platform.request("sfp_ctl", 2).tx_disable.eq(0)
self.submodules.transceiver = gtp_7series.GTP(
qpll_channel=self.drtio_qpll_channel,
data_pads=[platform.request("sfp", 2)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
DRTIOMaster(self.transceiver.channels[0]))
self.csr_devices.append("drtio0")
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
self.drtio0.aux_controller.bus)
self.add_memory_region("drtio0_aux",
self.mem_map["drtio_aux"] | self.shadow_base,
0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", ["drtio0"])
self.add_memory_group("drtio_aux", ["drtio0_aux"])
rtio_clk_period = 1e9 / rtio_clk_freq
for gtp in self.transceiver.gtps:
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
rtio_channels = []
phy = ttl_simple.Output(platform.request("user_led", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.Output(platform.request("sfp_ctl", 1).led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(rtio_channels,
glbl_fine_ts_width=3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri, self.drtio0.cri])
self.register_kernel_cpu_csrdevice("cri_con")
def __init__(self, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
add_identifier(self)
platform = self.platform
rtio_clk_freq = 150e6
self.submodules.si5324_rst_n = gpio.GPIOOut(
platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.comb += [
platform.request("sfp_tx_disable", i).eq(0) for i in range(2)
]
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("si5324_clkout", 0),
data_pads=[platform.request("sfp", i) for i in range(2)] +
[platform.request("rtm_gth", i) for i in range(8)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
drtio_csr_group = []
drtio_memory_group = []
drtio_cri = []
for i in range(10):
core_name = "drtio" + str(i)
memory_name = "drtio" + str(i) + "_aux"
drtio_csr_group.append(core_name)
drtio_memory_group.append(memory_name)
core = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})(
DRTIOMaster(self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
memory_address = self.mem_map["drtio_aux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, core.aux_controller.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_memory_group("drtio_aux", drtio_memory_group)
rtio_clk_period = 1e9 / rtio_clk_freq
gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk,
gth.rxoutclk)
for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gth.rxoutclk)
self.rtio_channels = rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
platform.add_extension(fmcdio_vhdci_eem.io)
platform.add_connectors(fmcdio_vhdci_eem.connectors)
fmcdio_dirctl = platform.request("fmcdio_dirctl")
for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
phy = ttl_simple.Output(s)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
eem.DIO.add_std(self,
2,
ttl_simple.Output,
ttl_simple.Output,
iostandard="LVDS")
eem.Urukul.add_std(self, 1, 0, ttl_simple.Output, iostandard="LVDS")
eem.Zotino.add_std(self, 3, ttl_simple.Output, iostandard="LVDS")
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(rtio_channels,
glbl_fine_ts_width=3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + drtio_cri)
self.register_kernel_cpu_csrdevice("cri_con")
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
RTMCommon.__init__(self)
add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
self.config["HMC830_REF"] = "100"
platform = self.platform
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_SAYMA_REF"] = None
# ensure pins are properly biased and terminated
si5324_clkout = platform.request("si5324_clkout", 0)
self.specials += Instance(
"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
attr={("DONT_TOUCH", "true")})
# RTIO
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_crg")
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs +
self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.clock_domains.cd_rtio = ClockDomain()
self.comb += [
self.cd_rtio.clk.eq(ClockSignal("jesd")),
self.cd_rtio.rst.eq(ResetSignal("jesd"))
]
self.submodules.rtio_tsc = rtio.TSC("async")
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri,
self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
self.rtio_tsc.coarse_ts, self.ad9154_crg.jref)
self.csr_devices.append("sysref_sampler")
def __init__(self, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
self.comb += platform.request("sfp_tx_disable_n").eq(1)
tx_pads = platform.request("sfp_tx")
rx_pads = platform.request("sfp_rx")
# 1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
clock_pads=platform.request("sgmii_clock"),
tx_pads=tx_pads,
rx_pads=rx_pads,
sys_clk_freq=self.clk_freq,
clock_div2=True)
self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
DRTIOMaster(self.transceiver.channels[0]))
self.csr_devices.append("drtio0")
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
self.drtio0.aux_controller.bus)
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", ["drtio0"])
self.add_memory_group("drtio_aux", ["drtio0_aux"])
platform.add_extension(ad9154_fmc_ebz)
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
]
rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.transceiver.txoutclk, self.transceiver.rxoutclk)
rtio_channels = []
for i in range(8):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for sma in "user_sma_gpio_p", "user_sma_gpio_n":
phy = ttl_simple.InOut(platform.request(sma))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri, self.drtio0.cri])
self.register_kernel_cpu_csrdevice("cri_con")
def __init__(self, cpu_type="or1k", with_sawg=False, **kwargs):
MiniSoC.__init__(self,
cpu_type=cpu_type,
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
platform.toolchain.bitstream_commands.append(
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]")
self.submodules.leds = gpio.GPIOOut(
Cat(platform.request("user_led", 0),
platform.request("user_led", 1)))
self.csr_devices.append("leds")
# forward RTM UART to second FTDI UART channel
serial_1 = platform.request("serial", 1)
serial_rtm = platform.request("serial_rtm")
self.comb += [
serial_1.tx.eq(serial_rtm.rx),
serial_rtm.tx.eq(serial_1.rx)
]
# AMC/RTM serwb
serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=2)
self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk)
self.submodules += serwb_pll
serwb_pads = platform.request("amc_rtm_serwb")
serwb_phy = serwb.phy.SERWBPHY(platform.device,
serwb_pll,
serwb_pads,
mode="master")
self.submodules.serwb_phy = serwb_phy
self.csr_devices.append("serwb_phy")
serwb_phy.serdes.cd_serwb_serdes.clk.attr.add("keep")
serwb_phy.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
serwb_phy.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
platform.add_period_constraint(serwb_phy.serdes.cd_serwb_serdes.clk,
32.0),
platform.add_period_constraint(
serwb_phy.serdes.cd_serwb_serdes_20x.clk, 1.6),
platform.add_period_constraint(serwb_phy.serdes.cd_serwb_serdes_5x.clk,
6.4)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, serwb_phy.serdes.cd_serwb_serdes.clk,
serwb_phy.serdes.cd_serwb_serdes_5x.clk)
serwb_core = serwb.core.SERWBCore(serwb_phy,
int(self.clk_freq),
mode="slave")
self.submodules += serwb_core
self.add_wb_slave(self.mem_map["serwb"], 8192,
serwb_core.etherbone.wishbone.bus)
# RTIO
rtio_channels = []
for i in (2, 3):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in (0, 1):
sma_io = platform.request("sma_io", i)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
if with_sawg:
self.submodules.ad9154_0 = AD9154(platform)
self.csr_devices.append("ad9154_0")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy) for sawg in self.ad9154_0.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.clock_domains.cd_rtio = ClockDomain()
self.comb += [
self.cd_rtio.clk.eq(ClockSignal()),
self.cd_rtio.rst.eq(ResetSignal())
]
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio_core.cri, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def __init__(self, identifier_str=None, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
csr_address_width=15,
**kwargs)
AMPSoC.__init__(self)
add_identifier(self, identifier_str=identifier_str)
platform = self.platform
rtio_clk_freq = 150e6
self.comb += platform.request("input_clk_sel").eq(1)
self.comb += platform.request("filtered_clk_sel").eq(1)
self.submodules.si5324_rst_n = gpio.GPIOOut(
platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("cdr_clk_clean", 0),
data_pads=[platform.request("mch_fabric_d", i) for i in range(11)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
drtio_csr_group = []
drtioaux_csr_group = []
drtioaux_memory_group = []
drtio_cri = []
for i in range(len(self.drtio_transceiver.channels)):
core_name = "drtio" + str(i)
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtio_csr_group.append(core_name)
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
core = cdr(
DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, coreaux.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
rtio_clk_period = 1e9 / rtio_clk_freq
gth0 = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth0.txoutclk, rtio_clk_period / 2)
platform.add_period_constraint(gth0.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth0.txoutclk,
gth0.rxoutclk)
for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gth0.txoutclk, gth.rxoutclk)
self.rtio_channels = rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
eem.DIO.add_std(self,
2,
ttl_simple.Output,
ttl_simple.Output,
iostandard="LVDS")
eem.Urukul.add_std(self, 0, 1, ttl_simple.Output, iostandard="LVDS")
eem.Zotino.add_std(self, 3, ttl_simple.Output, iostandard="LVDS")
workaround_us_lvds_tristate(platform)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + drtio_cri,
enable_routing=True)
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
RTMCommon.__init__(self)
self.config["HMC830_REF"] = "100"
platform = self.platform
# RTIO
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_crg = AD9154CRG(platform)
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_crg")
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs +
self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.clock_domains.cd_rtio = ClockDomain()
self.comb += [
self.cd_rtio.clk.eq(ClockSignal("jesd")),
self.cd_rtio.rst.eq(ResetSignal("jesd"))
]
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
RTMCommon.__init__(self)
add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
self.config["HMC830_REF"] = "100"
platform = self.platform
rtio_clk_freq = 150e6
self.submodules.si5324_rst_n = gpio.GPIOOut(
platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_SAYMA_REF"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
# ensure pins are properly biased and terminated
si5324_clkout = platform.request("cdr_clk_clean", 0)
self.specials += Instance("IBUFDS_GTE3",
i_CEB=0,
i_I=si5324_clkout.p,
i_IB=si5324_clkout.n,
attr={("DONT_TOUCH", "true")})
self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
self.csr_devices.append("ad9154_crg")
self.comb += [
platform.request("sfp_tx_disable", i).eq(0) for i in range(2)
]
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=self.ad9154_crg.refclk,
data_pads=[platform.request("sata")] +
[platform.request("sfp", i) for i in range(2)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
drtio_csr_group = []
drtioaux_csr_group = []
drtioaux_memory_group = []
drtio_cri = []
for i in range(3):
core_name = "drtio" + str(i)
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtio_csr_group.append(core_name)
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
core = cdr(
DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, coreaux.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
rtio_clk_period = 1e9 / rtio_clk_freq
gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period / 2)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
self.drtio_transceiver.cd_rtio.clk.attr.add("keep")
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.drtio_transceiver.cd_rtio.clk,
gth.rxoutclk)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk)
for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gth.rxoutclk)
platform.add_false_path_constraints(
self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk)
platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk,
self.drtio_transceiver.cd_rtio.clk)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs + self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + drtio_cri,
enable_routing=True)
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
platform.request("dac_sysref"), self.rtio_tsc.coarse_ts)
self.csr_devices.append("sysref_sampler")
self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref)
self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref)
def __init__(self, cpu_type="or1k", **kwargs):
MiniSoC.__init__(self,
cpu_type=cpu_type,
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
self.platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
platform = self.platform
platform.add_extension(ad9154_fmc_ebz)
self.submodules.leds = gpio.GPIOOut(
Cat(platform.request("user_led", 0),
platform.request("user_led", 1)))
self.csr_devices.append("leds")
i2c = platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.config["CONVERTER_SPI_DAC_CS"] = 0
self.config["CONVERTER_SPI_CLK_CS"] = 1
self.config["HAS_AD9516"] = None
self.submodules.ad9154 = AD9154(platform)
self.csr_devices.append("ad9154")
rtio_channels = []
phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sysref_pads = platform.request("ad9154_sysref")
phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
self.submodules += phy
rtio_channels.append(
rtio.Channel.from_phy(phy, ififo_depth=32, ofifo_depth=2))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy) for sawg in self.ad9154.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_crg = _PhaserCRG(platform,
self.ad9154.jesd.cd_jesd.clk)
self.csr_devices.append("rtio_crg")
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
# self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
self.register_kernel_cpu_csrdevice("rtio")
# self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri], # , self.rtio_dma.cri],
[self.rtio_core.cri])
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio, self.rtio_core.cri.counter, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.rtio_crg.cd_rtio.clk)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ad9154.jesd.cd_jesd.clk)
for phy in self.ad9154.jesd.phys:
platform.add_false_path_constraints(self.crg.cd_sys.clk,
phy.gtx.cd_tx.clk)
def __init__(self, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
rtio_clk_freq = 150e6
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
sfp_ctl = [platform.request("sfp_ctl", i) for i in range(1, 3)]
self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctl]
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=self.drtio_qpll_channel,
data_pads=[platform.request("sfp", i) for i in range(1, 3)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += self.disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
drtio_csr_group = []
drtio_memory_group = []
drtio_cri = []
for i in range(2):
core_name = "drtio" + str(i)
memory_name = "drtio" + str(i) + "_aux"
drtio_csr_group.append(core_name)
drtio_memory_group.append(memory_name)
core = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})(
DRTIOMaster(self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
memory_address = self.mem_map["drtio_aux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, core.aux_controller.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_memory_group("drtio_aux", drtio_memory_group)
rtio_clk_period = 1e9 / rtio_clk_freq
for gtp in self.drtio_transceiver.gtps:
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
rtio_channels = []
phy = ttl_simple.Output(platform.request("user_led", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for sc in sfp_ctl:
phy = ttl_simple.Output(sc.led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(rtio_channels,
glbl_fine_ts_width=3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + drtio_cri)
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_analyzer = rtio.Analyzer(
self.cri_con.switch.slave, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def __init__(self, gateware_identifier_str=None, sma_as_sat=False, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,
**kwargs)
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
self.platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
if isinstance(self.platform.toolchain, XilinxISEToolchain):
self.platform.toolchain.bitgen_opt += " -g compress"
platform = self.platform
self.comb += platform.request("sfp_tx_disable_n").eq(1)
tx_pads = [
platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
]
rx_pads = [
platform.request("sfp_rx"), platform.request("user_sma_mgt_rx")
]
if sma_as_sat:
tx_pads = tx_pads[::-1]
rx_pads = rx_pads[::-1]
# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("si5324_clkout"),
tx_pads=tx_pads,
rx_pads=rx_pads,
sys_clk_freq=self.clk_freq)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
drtioaux_csr_group = []
drtioaux_memory_group = []
drtiorep_csr_group = []
self.drtio_cri = []
for i in range(len(self.drtio_transceiver.channels)):
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
# Satellite
if i == 0:
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(DRTIOSatellite(
self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
# Repeaters
else:
corerep_name = "drtiorep" + str(i-1)
drtiorep_csr_group.append(corerep_name)
core = cdr(DRTIORepeater(
self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, corerep_name, core)
self.drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800,
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.add_csr_group("drtiorep", drtiorep_csr_group)
self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
# Si5324 Phaser
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ultrascale=False,
rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
]
rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
# Constrain TX & RX timing for the first transceiver channel
# (First channel acts as master for phase alignment for all channels' TX)
gtx0 = self.drtio_transceiver.gtxs[0]
platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtx0.txoutclk, gtx0.rxoutclk)
# Constrain RX timing for the each transceiver channel
# (Each channel performs single-lane phase alignment for RX)
for gtx in self.drtio_transceiver.gtxs[1:]:
platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtx.rxoutclk)
rtio_channels = []
for i in range(8):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for sma in "user_sma_gpio_p", "user_sma_gpio_n":
phy = ttl_simple.InOut(platform.request(sma))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri],
[self.local_io.cri] + self.drtio_cri,
mode="sync", enable_routing=True)
self.csr_devices.append("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
def __init__(self, cfg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
self.comb += platform.request("sfp_tx_disable_n").eq(1)
tx_pads = platform.request("sfp_tx")
rx_pads = platform.request("sfp_rx")
if cfg == "simple_gbe":
# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
# simple TTLs
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
clock_pads=platform.request("sgmii_clock"),
tx_pads=tx_pads,
rx_pads=rx_pads,
sys_clk_freq=self.clk_freq,
clock_div2=True)
elif cfg == "sawg_3g":
# 3Gb link, 150MHz RTIO clock
# with SAWG on local RTIO and AD9154-FMC-EBZ
platform.add_extension(ad9154_fmc_ebz)
self.submodules.transceiver = gtx_7series.GTX_3G(
clock_pads=platform.request("ad9154_refclk"),
tx_pads=tx_pads,
rx_pads=rx_pads,
sys_clk_freq=self.clk_freq)
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.config["CONVERTER_SPI_DAC_CS"] = 0
self.config["CONVERTER_SPI_CLK_CS"] = 1
self.config["HAS_AD9516"] = None
else:
raise ValueError
self.submodules.drtio = DRTIOMaster(self.transceiver)
self.csr_devices.append("drtio")
self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]),
self.drtio.aux_controller.bus)
self.add_memory_region("drtio_aux",
self.mem_map["drtio_aux"] | self.shadow_base,
0x800)
self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")),
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
]
rtio_clk_period = 1e9 / self.transceiver.rtio_clk_freq
platform.add_period_constraint(self.transceiver.txoutclk,
rtio_clk_period)
platform.add_period_constraint(self.transceiver.rxoutclk,
rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.transceiver.txoutclk,
self.transceiver.rxoutclk)
rtio_channels = []
for i in range(8):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for sma in "user_sma_gpio_p", "user_sma_gpio_n":
phy = ttl_simple.Inout(platform.request(sma))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.drtio.cri, self.rtio_core.cri])
