def setParent(self, parentNode):
for aFuncNode in self.auxFuncVec:
aFuncNode.removeParent()
self.removeChild(aFuncNode)
parentNode.addChild(aFuncNode)
self.auxFuncVec = [] # IrNodeAnalogFunction.empty;
IrNode.setParent(self, parentNode)
def __init__(self):
IrNode.__init__(self)
self.additive = 0
self.multiplicative = False
self.affine = False
self.ddtTopNode = False
self.onDdtPath = False
self.VARSFX = '__'
def setConnectedToModule(self):
# SETCONNECTEDTOMODULE
if self.varObj is None:
# notify module about this new var and get a MsVariable object
# in return
self.addVarToModule()
IrNode.setConnectedToModule(self)
return
def addChild(self, childNode):
# ADDCHILD
if self.nChild == 3:
error((
'Error adding a child to an IrNodeIfElse. This node'\
' already has 3 children!'
))
IrNode.addChild(self, childNode)
return
def addChild(self, childNode):
# ADDCHILD
if self.nChild >= 2:
error(
'This assignment already has 2 children. The number'\
' of children in an assignment cannot be more than 2!'
)
else:
IrNode.addChild(self, childNode)
return
def addChild(self, childNode):
# we are redefining the addChild method (inhereted from IrNode)
# below because of functions like limexp.
# These functions have to be added to the top module.
# But there is a chance that they are first encountered in
# an analog function.
# Hence, we would like them to be added to the parent of
# this analog function.
# The same reasoning would apply if Verilog-A allowed
# analog function declarations in other analog functions.
# But it does not.
if childNode.hasType('IrNodeAnalogFunction') == True:
self.auxFuncVec.append(childNode)
IrNode.addChild(self, childNode)
def __init__(self, name='', terminalList=[]):
IrNode.__init__(self)
self.terminalList = [] # list of terminals (strings)
self.nodeList = [] # list of nodes (strings)
self.internalNodeList = [
] # list of nodes that are not terminals (strings)
self.branchList = [] # list of branches (strings)
self.refLabel = '' # label of the reference node (string)
self.refNode = None # MsNode object
self.network = None # MsNetwork Object
self.varMap = AttrDict()
self.parmMap = AttrDict()
self.parmNameArr = []
# note that contrary to vars and parms,
# funcs are not ModSpec objects.
self.funcMap = AttrDict()
self.nodeMap = AttrDict()
self.branchMap = AttrDict()
self.disciplineMap = AttrDict()
self.network = MsNetwork()
self.connectedToModule = True
# number of terminals
self.nTerminal = 0
# number of Nodes
self.nNode = 0
self.nFeQe = 0
# number of internal equations (includes implicit equations)
self.nFiQi = 0
self.nExpOut = 0
self.nIntUnk = 0
self.nInput = 0
self.nOtherIo = 0
self.derivLevel = 0
self.expOutPotentialVec = [] # MsPotential
self.expOutFlowVec = [] # MsTerminalFlow
self.intUnkPotentialVec = [] # MsPotential
self.intUnkFlowVec = [] # MsFlow
self.otherIoPotentialVec = [] # MsPotential
self.otherIoFlowVec = [] # MsFlow
self.intUnkPfVec = [] # MsPotential
self.expOutPfVec = [] # MsPotential
self.otherIoPfVec = [] # MsPotential
self.implicitContribVec = [] # IrNodeContribution
self.nImplicitContrib = 0
self.expOutList = []
self.intUnkList = []
self.analogNode = None # IrNodeAnalog
# internal equation index (includes internal nodes,
# otherIO equations and implicit equations).
self.intEqnIdx = 0
self.intEqnNameList = []
self.nodeCollapseTree = None
self.fullModel = None # MsModel
self.nodeCollapseVarStr = ''
self.nodeCollapseParmStr = ''
self.name = name
self.setTerminalList(terminalList)
def addChild(self, childNode):
IrNode.addChild(self, childNode)
childNode.setAdditive(self.additive)
return
def __init__(self):
IrNode.__init__(self)
def __init__(self, indentLevel=0):
IrNode.__init__(self)
self.indentLevel = indentLevel
def addVarToModule(self, varLabel, isDerivative):
""" ADDVARTOMODULE
"""
varObj = IrNode.addVarToModule(self, varLabel, True)
return varObj
def __init__(self):
""" IRNODEDERIVATIVEBLOCK
"""
IrNode.__init__(self)
def __init__(self, branchObj):
IrNode.__init__(self)
self.branch = branchObj # MsBranch object
def acceptVisitor(self, visitor, *args):
# ACCEPTVISITOR
self.computeCoreModel()
out = IrNode.acceptVisitor(self, visitor, *args)
return out
def __init__(self, modelObj=None):
IrNode.__init__(self)
self.modelObj = modelObj
self.printMode = ''
def addVarToModule(self):
# ADDVARTOMODULE
self.varObj = IrNode.addVarToModule(self.parent, self.label)
return