def __init__(self, *args, **kwargs): """ Define the ARM's system's memory, registers etc. """ Architecture.__init__(self, *args, **kwargs) self.name = "ARM" self.word_width_bits = 32 memory = Memory( 0, # The zeroth and only memory ["Memory", "Mem", "memory", "mem"], # Names for the main/only memory 32, # 32-bit address bus 8, # 8-bit memory words [ARMAssembler()], # Use the ARM assembler []) # TODO: add a disassembler self.memories.append(memory) self._define_register_bank(memory, ["Current", "current"], 0, True) self._define_register_bank(memory, ["User", "System", "user", "system"], 32) self._define_register_bank(memory, ["Supervisor", "supervisor"], 64) self._define_register_bank(memory, ["Abort", "abort"], 96) self._define_register_bank(memory, ["Undefined", "undef", "undefined", "undef"], 128) self._define_register_bank(memory, ["IRQ", "irq"], 160) self._define_register_bank(memory, ["FIQ", "fiq"], 192)
def __init__(self, *args, **kwargs): """ Define the MU0 system's memory, registers etc. """ Architecture.__init__(self, *args, **kwargs)