def bench(): # Parameters DATA_WIDTH = 64 HDR_WIDTH = (DATA_WIDTH / 32) AXIS_DATA_WIDTH = DATA_WIDTH AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH > 8) AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH / 8) ENABLE_PADDING = 1 ENABLE_DIC = 1 MIN_FRAME_LENGTH = 64 BIT_REVERSE = 0 SCRAMBLER_DISABLE = 0 PRBS31_ENABLE = 1 TX_SERDES_PIPELINE = 2 RX_SERDES_PIPELINE = 2 BITSLIP_HIGH_CYCLES = 1 BITSLIP_LOW_CYCLES = 8 COUNT_125US = 125000 / 6.4 TX_FIFO_DEPTH = 4096 TX_FIFO_PIPELINE_OUTPUT = 2 TX_FRAME_FIFO = 1 TX_DROP_BAD_FRAME = TX_FRAME_FIFO TX_DROP_WHEN_FULL = 0 RX_FIFO_DEPTH = 4096 RX_FIFO_PIPELINE_OUTPUT = 2 RX_FRAME_FIFO = 1 RX_DROP_BAD_FRAME = RX_FRAME_FIFO RX_DROP_WHEN_FULL = RX_FRAME_FIFO LOGIC_PTP_PERIOD_NS = 0x6 LOGIC_PTP_PERIOD_FNS = 0x6666 PTP_PERIOD_NS = 0x6 PTP_PERIOD_FNS = 0x6666 PTP_USE_SAMPLE_CLOCK = 0 TX_PTP_TS_ENABLE = 1 RX_PTP_TS_ENABLE = 1 TX_PTP_TS_FIFO_DEPTH = 64 RX_PTP_TS_FIFO_DEPTH = 64 PTP_TS_WIDTH = 96 TX_PTP_TAG_ENABLE = 1 PTP_TAG_WIDTH = 16 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) rx_clk = Signal(bool(0)) rx_rst = Signal(bool(0)) tx_clk = Signal(bool(0)) tx_rst = Signal(bool(0)) logic_clk = Signal(bool(0)) logic_rst = Signal(bool(0)) ptp_sample_clk = Signal(bool(0)) tx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) tx_axis_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:]) tx_axis_tvalid = Signal(bool(0)) tx_axis_tlast = Signal(bool(0)) tx_axis_tuser = Signal(bool(0)) s_axis_tx_ptp_ts_tag = Signal(intbv(0)[PTP_TAG_WIDTH:]) s_axis_tx_ptp_ts_valid = Signal(bool(0)) m_axis_tx_ptp_ts_ready = Signal(bool(0)) rx_axis_tready = Signal(bool(0)) m_axis_rx_ptp_ts_ready = Signal(bool(0)) serdes_rx_data = Signal(intbv(0)[DATA_WIDTH:]) serdes_rx_hdr = Signal(intbv(1)[HDR_WIDTH:]) ptp_ts_96 = Signal(intbv(0)[PTP_TS_WIDTH:]) ifg_delay = Signal(intbv(0)[8:]) tx_prbs31_enable = Signal(bool(0)) rx_prbs31_enable = Signal(bool(0)) serdes_rx_data_int = Signal(intbv(0)[DATA_WIDTH:]) serdes_rx_hdr_int = Signal(intbv(1)[HDR_WIDTH:]) # Outputs tx_axis_tready = Signal(bool(0)) s_axis_tx_ptp_ts_ready = Signal(bool(1)) m_axis_tx_ptp_ts_96 = Signal(intbv(0)[PTP_TS_WIDTH:]) m_axis_tx_ptp_ts_tag = Signal(intbv(0)[PTP_TAG_WIDTH:]) m_axis_tx_ptp_ts_valid = Signal(bool(0)) rx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:]) rx_axis_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:]) rx_axis_tvalid = Signal(bool(0)) rx_axis_tlast = Signal(bool(0)) rx_axis_tuser = Signal(bool(0)) m_axis_rx_ptp_ts_96 = Signal(intbv(0)[PTP_TS_WIDTH:]) m_axis_rx_ptp_ts_valid = Signal(bool(0)) serdes_tx_data = Signal(intbv(0)[DATA_WIDTH:]) serdes_tx_hdr = Signal(intbv(1)[HDR_WIDTH:]) serdes_rx_bitslip = Signal(bool(0)) tx_error_underflow = Signal(bool(0)) tx_fifo_overflow = Signal(bool(0)) tx_fifo_bad_frame = Signal(bool(0)) tx_fifo_good_frame = Signal(bool(0)) rx_error_bad_frame = Signal(bool(0)) rx_error_bad_fcs = Signal(bool(0)) rx_bad_block = Signal(bool(0)) rx_block_lock = Signal(bool(0)) rx_high_ber = Signal(bool(0)) rx_fifo_overflow = Signal(bool(0)) rx_fifo_bad_frame = Signal(bool(0)) rx_fifo_good_frame = Signal(bool(0)) # sources and sinks axis_source_pause = Signal(bool(0)) axis_sink_pause = Signal(bool(0)) serdes_source = baser_serdes_ep.BaseRSerdesSource() serdes_source_logic = serdes_source.create_logic( rx_clk, tx_data=serdes_rx_data_int, tx_header=serdes_rx_hdr_int, name='serdes_source') serdes_sink = baser_serdes_ep.BaseRSerdesSink() serdes_sink_logic = serdes_sink.create_logic(tx_clk, rx_data=serdes_tx_data, rx_header=serdes_tx_hdr, name='serdes_sink') axis_source = axis_ep.AXIStreamSource() axis_source_logic = axis_source.create_logic(logic_clk, logic_rst, tdata=tx_axis_tdata, tkeep=tx_axis_tkeep, tvalid=tx_axis_tvalid, tready=tx_axis_tready, tlast=tx_axis_tlast, tuser=tx_axis_tuser, pause=axis_source_pause, name='axis_source') axis_sink = axis_ep.AXIStreamSink() axis_sink_logic = axis_sink.create_logic(logic_clk, logic_rst, tdata=rx_axis_tdata, tkeep=rx_axis_tkeep, tvalid=rx_axis_tvalid, tready=rx_axis_tready, tlast=rx_axis_tlast, tuser=rx_axis_tuser, pause=axis_sink_pause, name='axis_sink') tx_ptp_ts_tag_source = axis_ep.AXIStreamSource() tx_ptp_ts_tag_source_logic = tx_ptp_ts_tag_source.create_logic( logic_clk, logic_rst, tdata=s_axis_tx_ptp_ts_tag, tvalid=s_axis_tx_ptp_ts_valid, tready=s_axis_tx_ptp_ts_ready, name='tx_ptp_ts_tag_source') tx_ptp_ts_sink = axis_ep.AXIStreamSink() tx_ptp_ts_sink_logic = tx_ptp_ts_sink.create_logic( logic_clk, logic_rst, tdata=(m_axis_tx_ptp_ts_96, m_axis_tx_ptp_ts_tag), tvalid=m_axis_tx_ptp_ts_valid, tready=m_axis_tx_ptp_ts_ready, name='tx_ptp_ts_sink') rx_ptp_ts_sink = axis_ep.AXIStreamSink() rx_ptp_ts_sink_logic = rx_ptp_ts_sink.create_logic( logic_clk, logic_rst, tdata=m_axis_rx_ptp_ts_96, tvalid=m_axis_rx_ptp_ts_valid, tready=m_axis_rx_ptp_ts_ready, name='rx_ptp_ts_sink') # PTP clock ptp_clock = ptp.PtpClock(period_ns=LOGIC_PTP_PERIOD_NS, period_fns=LOGIC_PTP_PERIOD_FNS) ptp_logic = ptp_clock.create_logic(logic_clk, logic_rst, ts_64=ptp_ts_96) # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, rx_clk=rx_clk, rx_rst=rx_rst, tx_clk=tx_clk, tx_rst=tx_rst, logic_clk=logic_clk, logic_rst=logic_rst, ptp_sample_clk=ptp_sample_clk, tx_axis_tdata=tx_axis_tdata, tx_axis_tkeep=tx_axis_tkeep, tx_axis_tvalid=tx_axis_tvalid, tx_axis_tready=tx_axis_tready, tx_axis_tlast=tx_axis_tlast, tx_axis_tuser=tx_axis_tuser, s_axis_tx_ptp_ts_tag=s_axis_tx_ptp_ts_tag, s_axis_tx_ptp_ts_valid=s_axis_tx_ptp_ts_valid, s_axis_tx_ptp_ts_ready=s_axis_tx_ptp_ts_ready, m_axis_tx_ptp_ts_96=m_axis_tx_ptp_ts_96, m_axis_tx_ptp_ts_tag=m_axis_tx_ptp_ts_tag, m_axis_tx_ptp_ts_valid=m_axis_tx_ptp_ts_valid, m_axis_tx_ptp_ts_ready=m_axis_tx_ptp_ts_ready, rx_axis_tdata=rx_axis_tdata, rx_axis_tkeep=rx_axis_tkeep, rx_axis_tvalid=rx_axis_tvalid, rx_axis_tready=rx_axis_tready, rx_axis_tlast=rx_axis_tlast, rx_axis_tuser=rx_axis_tuser, m_axis_rx_ptp_ts_96=m_axis_rx_ptp_ts_96, m_axis_rx_ptp_ts_valid=m_axis_rx_ptp_ts_valid, m_axis_rx_ptp_ts_ready=m_axis_rx_ptp_ts_ready, serdes_tx_data=serdes_tx_data, serdes_tx_hdr=serdes_tx_hdr, serdes_rx_data=serdes_rx_data, serdes_rx_hdr=serdes_rx_hdr, serdes_rx_bitslip=serdes_rx_bitslip, tx_error_underflow=tx_error_underflow, tx_fifo_overflow=tx_fifo_overflow, tx_fifo_bad_frame=tx_fifo_bad_frame, tx_fifo_good_frame=tx_fifo_good_frame, rx_error_bad_frame=rx_error_bad_frame, rx_error_bad_fcs=rx_error_bad_fcs, rx_bad_block=rx_bad_block, rx_block_lock=rx_block_lock, rx_high_ber=rx_high_ber, rx_fifo_overflow=rx_fifo_overflow, rx_fifo_bad_frame=rx_fifo_bad_frame, rx_fifo_good_frame=rx_fifo_good_frame, ptp_ts_96=ptp_ts_96, ifg_delay=ifg_delay, tx_prbs31_enable=tx_prbs31_enable, rx_prbs31_enable=rx_prbs31_enable) @always(delay(4)) def clkgen(): clk.next = not clk tx_clk.next = not tx_clk rx_clk.next = not rx_clk logic_clk.next = not logic_clk ptp_sample_clk.next = not ptp_sample_clk load_bit_offset = [] @instance def shift_bits(): bit_offset = 0 last_data = 0 while True: yield clk.posedge if load_bit_offset: bit_offset = load_bit_offset.pop(0) if serdes_rx_bitslip: bit_offset += 1 bit_offset = bit_offset % 66 data = int(serdes_rx_data_int) << 2 | int(serdes_rx_hdr_int) out_data = ((last_data | data << 66) >> 66 - bit_offset) & 0x3ffffffffffffffff last_data = data serdes_rx_data.next = out_data >> 2 serdes_rx_hdr.next = out_data & 3 @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 tx_rst.next = 1 rx_rst.next = 1 logic_rst.next = 1 yield clk.posedge rst.next = 0 tx_rst.next = 0 rx_rst.next = 0 logic_rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge ifg_delay.next = 12 # testbench stimulus # wait for block lock while not rx_block_lock: yield clk.posedge # dump garbage while not axis_sink.empty(): axis_sink.recv() yield clk.posedge print("test 1: test rx packet") current_test.next = 1 test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(32)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() serdes_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame)) yield axis_sink.wait() rx_frame = axis_sink.recv() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame yield delay(100) yield clk.posedge print("test 2: test tx packet") current_test.next = 2 test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(32)) test_frame.update_fcs() axis_frame = test_frame.build_axis() tx_ptp_ts_tag_source.send([1234]) axis_source.send(axis_frame) yield serdes_sink.wait() rx_frame = serdes_sink.recv() assert rx_frame.data[0:8] == bytearray( b'\x55\x55\x55\x55\x55\x55\x55\xD5') eth_frame = eth_ep.EthFrame() eth_frame.parse_axis_fcs(rx_frame.data[8:]) print(hex(eth_frame.eth_fcs)) print(hex(eth_frame.calc_fcs())) assert len(eth_frame.payload.data) == 46 assert eth_frame.eth_fcs == eth_frame.calc_fcs() assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac assert eth_frame.eth_src_mac == test_frame.eth_src_mac assert eth_frame.eth_type == test_frame.eth_type assert eth_frame.payload.data.index(test_frame.payload.data) == 0 yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters DATA_WIDTH = 64 KEEP_WIDTH = (DATA_WIDTH / 8) CTRL_WIDTH = (DATA_WIDTH / 8) HDR_WIDTH = (DATA_WIDTH / 32) ENABLE_PADDING = 1 ENABLE_DIC = 1 MIN_FRAME_LENGTH = 64 PTP_PERIOD_NS = 0x6 PTP_PERIOD_FNS = 0x6666 TX_PTP_TS_ENABLE = 0 TX_PTP_TS_WIDTH = 96 TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE TX_PTP_TAG_WIDTH = 16 RX_PTP_TS_ENABLE = 0 RX_PTP_TS_WIDTH = 96 TX_USER_WIDTH = (TX_PTP_TAG_WIDTH if TX_PTP_TAG_ENABLE else 0) + 1 RX_USER_WIDTH = (RX_PTP_TS_WIDTH if RX_PTP_TS_ENABLE else 0) + 1 BIT_REVERSE = 0 SCRAMBLER_DISABLE = 0 PRBS31_ENABLE = 1 TX_SERDES_PIPELINE = 2 RX_SERDES_PIPELINE = 2 SLIP_COUNT_WIDTH = 3 COUNT_125US = 125000 / 6.4 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) rx_clk = Signal(bool(0)) rx_rst = Signal(bool(0)) tx_clk = Signal(bool(0)) tx_rst = Signal(bool(0)) tx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) tx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) tx_axis_tvalid = Signal(bool(0)) tx_axis_tlast = Signal(bool(0)) tx_axis_tuser = Signal(intbv(0)[TX_USER_WIDTH:]) serdes_rx_data = Signal(intbv(0)[DATA_WIDTH:]) serdes_rx_hdr = Signal(intbv(1)[HDR_WIDTH:]) tx_ptp_ts = Signal(intbv(0)[TX_PTP_TS_WIDTH:]) rx_ptp_ts = Signal(intbv(0)[RX_PTP_TS_WIDTH:]) ifg_delay = Signal(intbv(0)[8:]) tx_prbs31_enable = Signal(bool(0)) rx_prbs31_enable = Signal(bool(0)) serdes_rx_data_int = Signal(intbv(0)[DATA_WIDTH:]) serdes_rx_hdr_int = Signal(intbv(1)[HDR_WIDTH:]) # Outputs tx_axis_tready = Signal(bool(0)) rx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) rx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) rx_axis_tvalid = Signal(bool(0)) rx_axis_tlast = Signal(bool(0)) rx_axis_tuser = Signal(intbv(0)[RX_USER_WIDTH:]) serdes_tx_data = Signal(intbv(0)[DATA_WIDTH:]) serdes_tx_hdr = Signal(intbv(1)[HDR_WIDTH:]) serdes_rx_bitslip = Signal(bool(0)) tx_axis_ptp_ts = Signal(intbv(0)[TX_PTP_TS_WIDTH:]) tx_axis_ptp_ts_tag = Signal(intbv(0)[TX_PTP_TAG_WIDTH:]) tx_axis_ptp_ts_valid = Signal(bool(0)) tx_start_packet = Signal(intbv(0)[2:]) tx_error_underflow = Signal(bool(0)) rx_start_packet = Signal(intbv(0)[2:]) rx_error_count = Signal(intbv(0)[7:]) rx_error_bad_frame = Signal(bool(0)) rx_error_bad_fcs = Signal(bool(0)) rx_bad_block = Signal(bool(0)) rx_block_lock = Signal(bool(0)) rx_high_ber = Signal(bool(0)) # sources and sinks axis_source_pause = Signal(bool(0)) serdes_source = baser_serdes_ep.BaseRSerdesSource() serdes_source_logic = serdes_source.create_logic( rx_clk, tx_data=serdes_rx_data_int, tx_header=serdes_rx_hdr_int, name='serdes_source') serdes_sink = baser_serdes_ep.BaseRSerdesSink() serdes_sink_logic = serdes_sink.create_logic(tx_clk, rx_data=serdes_tx_data, rx_header=serdes_tx_hdr, name='serdes_sink') axis_source = axis_ep.AXIStreamSource() axis_source_logic = axis_source.create_logic(tx_clk, tx_rst, tdata=tx_axis_tdata, tkeep=tx_axis_tkeep, tvalid=tx_axis_tvalid, tready=tx_axis_tready, tlast=tx_axis_tlast, tuser=tx_axis_tuser, pause=axis_source_pause, name='axis_source') axis_sink = axis_ep.AXIStreamSink() axis_sink_logic = axis_sink.create_logic(rx_clk, rx_rst, tdata=rx_axis_tdata, tkeep=rx_axis_tkeep, tvalid=rx_axis_tvalid, tlast=rx_axis_tlast, tuser=rx_axis_tuser, name='axis_sink') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, rx_clk=rx_clk, rx_rst=rx_rst, tx_clk=tx_clk, tx_rst=tx_rst, tx_axis_tdata=tx_axis_tdata, tx_axis_tkeep=tx_axis_tkeep, tx_axis_tvalid=tx_axis_tvalid, tx_axis_tready=tx_axis_tready, tx_axis_tlast=tx_axis_tlast, tx_axis_tuser=tx_axis_tuser, rx_axis_tdata=rx_axis_tdata, rx_axis_tkeep=rx_axis_tkeep, rx_axis_tvalid=rx_axis_tvalid, rx_axis_tlast=rx_axis_tlast, rx_axis_tuser=rx_axis_tuser, serdes_tx_data=serdes_tx_data, serdes_tx_hdr=serdes_tx_hdr, serdes_rx_data=serdes_rx_data, serdes_rx_hdr=serdes_rx_hdr, serdes_rx_bitslip=serdes_rx_bitslip, tx_ptp_ts=tx_ptp_ts, rx_ptp_ts=rx_ptp_ts, tx_axis_ptp_ts=tx_axis_ptp_ts, tx_axis_ptp_ts_tag=tx_axis_ptp_ts_tag, tx_axis_ptp_ts_valid=tx_axis_ptp_ts_valid, tx_start_packet=tx_start_packet, tx_error_underflow=tx_error_underflow, rx_start_packet=rx_start_packet, rx_error_count=rx_error_count, rx_error_bad_frame=rx_error_bad_frame, rx_error_bad_fcs=rx_error_bad_fcs, rx_bad_block=rx_bad_block, rx_block_lock=rx_block_lock, rx_high_ber=rx_high_ber, ifg_delay=ifg_delay, tx_prbs31_enable=tx_prbs31_enable, rx_prbs31_enable=rx_prbs31_enable) @always(delay(4)) def clkgen(): clk.next = not clk tx_clk.next = not tx_clk rx_clk.next = not rx_clk load_bit_offset = [] @instance def shift_bits(): bit_offset = 0 last_data = 0 while True: yield clk.posedge if load_bit_offset: bit_offset = load_bit_offset.pop(0) if serdes_rx_bitslip: bit_offset += 1 bit_offset = bit_offset % 66 data = int(serdes_rx_data_int) << 2 | int(serdes_rx_hdr_int) out_data = ((last_data | data << 66) >> 66 - bit_offset) & 0x3ffffffffffffffff last_data = data serdes_rx_data.next = out_data >> 2 serdes_rx_hdr.next = out_data & 3 @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 tx_rst.next = 1 rx_rst.next = 1 yield clk.posedge rst.next = 0 tx_rst.next = 0 rx_rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge ifg_delay.next = 12 # testbench stimulus # wait for block lock while not rx_block_lock: yield clk.posedge # dump garbage while not axis_sink.empty(): axis_sink.recv() yield clk.posedge print("test 1: test rx packet") current_test.next = 1 test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(32)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() serdes_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame)) yield axis_sink.wait() rx_frame = axis_sink.recv() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame yield delay(100) yield clk.posedge print("test 2: test tx packet") current_test.next = 2 test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(32)) test_frame.update_fcs() axis_frame = test_frame.build_axis() axis_source.send(axis_frame) yield serdes_sink.wait() rx_frame = serdes_sink.recv() assert rx_frame.data[0:8] == bytearray( b'\x55\x55\x55\x55\x55\x55\x55\xD5') eth_frame = eth_ep.EthFrame() eth_frame.parse_axis_fcs(rx_frame.data[8:]) print(hex(eth_frame.eth_fcs)) print(hex(eth_frame.calc_fcs())) assert len(eth_frame.payload.data) == 46 assert eth_frame.eth_fcs == eth_frame.calc_fcs() assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac assert eth_frame.eth_src_mac == test_frame.eth_src_mac assert eth_frame.eth_type == test_frame.eth_type assert eth_frame.payload.data.index(test_frame.payload.data) == 0 yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters DATA_WIDTH = 64 KEEP_WIDTH = (DATA_WIDTH / 8) HDR_WIDTH = 2 ENABLE_PADDING = 1 ENABLE_DIC = 1 MIN_FRAME_LENGTH = 64 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) s_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) s_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) s_axis_tvalid = Signal(bool(0)) s_axis_tlast = Signal(bool(0)) s_axis_tuser = Signal(bool(0)) ifg_delay = Signal(intbv(0)[8:]) # Outputs s_axis_tready = Signal(bool(0)) encoded_tx_data = Signal(intbv(0)[DATA_WIDTH:]) encoded_tx_hdr = Signal(intbv(1)[HDR_WIDTH:]) start_packet_0 = Signal(bool(0)) start_packet_4 = Signal(bool(0)) error_underflow = Signal(bool(0)) # sources and sinks source_pause = Signal(bool(0)) source = axis_ep.AXIStreamSource() source_logic = source.create_logic(clk, rst, tdata=s_axis_tdata, tkeep=s_axis_tkeep, tvalid=s_axis_tvalid, tready=s_axis_tready, tlast=s_axis_tlast, tuser=s_axis_tuser, pause=source_pause, name='source') sink = baser_serdes_ep.BaseRSerdesSink() sink_logic = sink.create_logic(clk, rx_data=encoded_tx_data, rx_header=encoded_tx_hdr, scramble=False, name='sink') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, s_axis_tdata=s_axis_tdata, s_axis_tkeep=s_axis_tkeep, s_axis_tvalid=s_axis_tvalid, s_axis_tready=s_axis_tready, s_axis_tlast=s_axis_tlast, s_axis_tuser=s_axis_tuser, encoded_tx_data=encoded_tx_data, encoded_tx_hdr=encoded_tx_hdr, ifg_delay=ifg_delay, start_packet_0=start_packet_0, start_packet_4=start_packet_4, error_underflow=error_underflow) @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge ifg_delay.next = 12 # testbench stimulus for payload_len in list(range(1, 18)) + list(range(40, 58)): yield clk.posedge print("test 1: test packet, length %d" % payload_len) current_test.next = 1 test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(payload_len)) test_frame.update_fcs() axis_frame = test_frame.build_axis() source.send(axis_frame) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data[0:8] == bytearray( b'\x55\x55\x55\x55\x55\x55\x55\xD5') eth_frame = eth_ep.EthFrame() eth_frame.parse_axis_fcs(rx_frame.data[8:]) print(hex(eth_frame.eth_fcs)) print(hex(eth_frame.calc_fcs())) assert len(eth_frame.payload.data) == max(payload_len, 46) assert eth_frame.eth_fcs == eth_frame.calc_fcs() assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac assert eth_frame.eth_src_mac == test_frame.eth_src_mac assert eth_frame.eth_type == test_frame.eth_type assert eth_frame.payload.data.index(test_frame.payload.data) == 0 assert sink.empty() yield delay(100) yield clk.posedge print("test 2: back-to-back packets, length %d" % payload_len) current_test.next = 2 test_frame1 = eth_ep.EthFrame() test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame1.eth_src_mac = 0x5A5152535455 test_frame1.eth_type = 0x8000 test_frame1.payload = bytearray(range(payload_len)) test_frame1.update_fcs() test_frame2 = eth_ep.EthFrame() test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame2.eth_src_mac = 0x5A5152535455 test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(payload_len)) test_frame2.update_fcs() axis_frame1 = test_frame1.build_axis() axis_frame2 = test_frame2.build_axis() source.send(axis_frame1) source.send(axis_frame2) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data[0:8] == bytearray( b'\x55\x55\x55\x55\x55\x55\x55\xD5') eth_frame = eth_ep.EthFrame() eth_frame.parse_axis_fcs(rx_frame.data[8:]) print(hex(eth_frame.eth_fcs)) print(hex(eth_frame.calc_fcs())) assert len(eth_frame.payload.data) == max(payload_len, 46) assert eth_frame.eth_fcs == eth_frame.calc_fcs() assert eth_frame.eth_dest_mac == test_frame1.eth_dest_mac assert eth_frame.eth_src_mac == test_frame1.eth_src_mac assert eth_frame.eth_type == test_frame1.eth_type assert eth_frame.payload.data.index(test_frame1.payload.data) == 0 yield sink.wait() rx_frame = sink.recv() assert rx_frame.data[0:8] == bytearray( b'\x55\x55\x55\x55\x55\x55\x55\xD5') eth_frame = eth_ep.EthFrame() eth_frame.parse_axis_fcs(rx_frame.data[8:]) print(hex(eth_frame.eth_fcs)) print(hex(eth_frame.calc_fcs())) assert len(eth_frame.payload.data) == max(payload_len, 46) assert eth_frame.eth_fcs == eth_frame.calc_fcs() assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac assert eth_frame.eth_src_mac == test_frame2.eth_src_mac assert eth_frame.eth_type == test_frame2.eth_type assert eth_frame.payload.data.index(test_frame2.payload.data) == 0 assert sink.empty() yield delay(100) yield clk.posedge print("test 3: tuser assert, length %d" % payload_len) current_test.next = 3 test_frame1 = eth_ep.EthFrame() test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame1.eth_src_mac = 0x5A5152535455 test_frame1.eth_type = 0x8000 test_frame1.payload = bytearray(range(payload_len)) test_frame1.update_fcs() test_frame2 = eth_ep.EthFrame() test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame2.eth_src_mac = 0x5A5152535455 test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(payload_len)) test_frame2.update_fcs() axis_frame1 = test_frame1.build_axis() axis_frame2 = test_frame2.build_axis() axis_frame1.last_cycle_user = 1 source.send(axis_frame1) source.send(axis_frame2) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data[0:8] == bytearray( b'\x55\x55\x55\x55\x55\x55\x55\xD5') assert rx_frame.error[-1] # bad packet yield sink.wait() rx_frame = sink.recv() assert rx_frame.data[0:8] == bytearray( b'\x55\x55\x55\x55\x55\x55\x55\xD5') eth_frame = eth_ep.EthFrame() eth_frame.parse_axis_fcs(rx_frame.data[8:]) print(hex(eth_frame.eth_fcs)) print(hex(eth_frame.calc_fcs())) assert len(eth_frame.payload.data) == max(payload_len, 46) assert eth_frame.eth_fcs == eth_frame.calc_fcs() assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac assert eth_frame.eth_src_mac == test_frame2.eth_src_mac assert eth_frame.eth_type == test_frame2.eth_type assert eth_frame.payload.data.index(test_frame2.payload.data) == 0 assert sink.empty() yield delay(100) for payload_len in list(range(46, 54)): yield clk.posedge print("test 4: test stream, length %d" % payload_len) current_test.next = 4 for i in range(10): test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(payload_len)) test_frame.update_fcs() axis_frame = test_frame.build_axis() source.send(axis_frame) for i in range(10): yield sink.wait() rx_frame = sink.recv() assert rx_frame.data[0:8] == bytearray( b'\x55\x55\x55\x55\x55\x55\x55\xD5') eth_frame = eth_ep.EthFrame() eth_frame.parse_axis_fcs(rx_frame.data[8:]) assert len(eth_frame.payload.data) == max(payload_len, 46) assert eth_frame.eth_fcs == eth_frame.calc_fcs() assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac assert eth_frame.eth_src_mac == test_frame.eth_src_mac assert eth_frame.eth_type == test_frame.eth_type assert eth_frame.payload.data.index( test_frame.payload.data) == 0 yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters DATA_WIDTH = 64 KEEP_WIDTH = int(DATA_WIDTH / 8) CTRL_WIDTH = int(DATA_WIDTH / 8) HDR_WIDTH = int(DATA_WIDTH / 32) ENABLE_PADDING = 1 ENABLE_DIC = 1 MIN_FRAME_LENGTH = 64 BIT_REVERSE = 0 SCRAMBLER_DISABLE = 0 SLIP_COUNT_WIDTH = 3 COUNT_125US = 125000 / 6.4 TX_FIFO_ADDR_WIDTH = 12 - (KEEP_WIDTH - 1).bit_length() TX_FRAME_FIFO = 1 TX_DROP_BAD_FRAME = TX_FRAME_FIFO TX_DROP_WHEN_FULL = 0 RX_FIFO_ADDR_WIDTH = 12 - (KEEP_WIDTH - 1).bit_length() RX_FRAME_FIFO = 1 RX_DROP_BAD_FRAME = RX_FRAME_FIFO RX_DROP_WHEN_FULL = RX_FRAME_FIFO # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) rx_clk = Signal(bool(0)) rx_rst = Signal(bool(0)) tx_clk = Signal(bool(0)) tx_rst = Signal(bool(0)) logic_clk = Signal(bool(0)) logic_rst = Signal(bool(0)) tx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) tx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) tx_axis_tvalid = Signal(bool(0)) tx_axis_tlast = Signal(bool(0)) tx_axis_tuser = Signal(bool(0)) rx_axis_tready = Signal(bool(0)) serdes_rx_data = Signal(intbv(0)[DATA_WIDTH:]) serdes_rx_hdr = Signal(intbv(1)[HDR_WIDTH:]) ifg_delay = Signal(intbv(0)[8:]) serdes_rx_data_int = Signal(intbv(0)[DATA_WIDTH:]) serdes_rx_hdr_int = Signal(intbv(1)[HDR_WIDTH:]) # Outputs tx_axis_tready = Signal(bool(0)) rx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) rx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) rx_axis_tvalid = Signal(bool(0)) rx_axis_tlast = Signal(bool(0)) rx_axis_tuser = Signal(bool(0)) serdes_tx_data = Signal(intbv(0)[DATA_WIDTH:]) serdes_tx_hdr = Signal(intbv(1)[HDR_WIDTH:]) serdes_rx_bitslip = Signal(bool(0)) tx_error_underflow = Signal(bool(0)) tx_fifo_overflow = Signal(bool(0)) tx_fifo_bad_frame = Signal(bool(0)) tx_fifo_good_frame = Signal(bool(0)) rx_error_bad_frame = Signal(bool(0)) rx_error_bad_fcs = Signal(bool(0)) rx_bad_block = Signal(bool(0)) rx_block_lock = Signal(bool(0)) rx_high_ber = Signal(bool(0)) rx_fifo_overflow = Signal(bool(0)) rx_fifo_bad_frame = Signal(bool(0)) rx_fifo_good_frame = Signal(bool(0)) # sources and sinks axis_source_pause = Signal(bool(0)) serdes_source = baser_serdes_ep.BaseRSerdesSource() serdes_source_logic = serdes_source.create_logic( rx_clk, tx_data=serdes_rx_data_int, tx_header=serdes_rx_hdr_int, name='serdes_source') serdes_sink = baser_serdes_ep.BaseRSerdesSink() serdes_sink_logic = serdes_sink.create_logic(tx_clk, rx_data=serdes_tx_data, rx_header=serdes_tx_hdr, name='serdes_sink') axis_source = axis_ep.AXIStreamSource() axis_source_logic = axis_source.create_logic(logic_clk, logic_rst, tdata=tx_axis_tdata, tkeep=tx_axis_tkeep, tvalid=tx_axis_tvalid, tready=tx_axis_tready, tlast=tx_axis_tlast, tuser=tx_axis_tuser, pause=axis_source_pause, name='axis_source') axis_sink = axis_ep.AXIStreamSink() axis_sink_logic = axis_sink.create_logic(logic_clk, logic_rst, tdata=rx_axis_tdata, tkeep=rx_axis_tkeep, tvalid=rx_axis_tvalid, tready=rx_axis_tready, tlast=rx_axis_tlast, tuser=rx_axis_tuser, name='axis_sink') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, rx_clk=rx_clk, rx_rst=rx_rst, tx_clk=tx_clk, tx_rst=tx_rst, logic_clk=logic_clk, logic_rst=logic_rst, tx_axis_tdata=tx_axis_tdata, tx_axis_tkeep=tx_axis_tkeep, tx_axis_tvalid=tx_axis_tvalid, tx_axis_tready=tx_axis_tready, tx_axis_tlast=tx_axis_tlast, tx_axis_tuser=tx_axis_tuser, rx_axis_tdata=rx_axis_tdata, rx_axis_tkeep=rx_axis_tkeep, rx_axis_tvalid=rx_axis_tvalid, rx_axis_tready=rx_axis_tready, rx_axis_tlast=rx_axis_tlast, rx_axis_tuser=rx_axis_tuser, serdes_tx_data=serdes_tx_data, serdes_tx_hdr=serdes_tx_hdr, serdes_rx_data=serdes_rx_data, serdes_rx_hdr=serdes_rx_hdr, serdes_rx_bitslip=serdes_rx_bitslip, tx_error_underflow=tx_error_underflow, tx_fifo_overflow=tx_fifo_overflow, tx_fifo_bad_frame=tx_fifo_bad_frame, tx_fifo_good_frame=tx_fifo_good_frame, rx_error_bad_frame=rx_error_bad_frame, rx_error_bad_fcs=rx_error_bad_fcs, rx_bad_block=rx_bad_block, rx_block_lock=rx_block_lock, rx_high_ber=rx_high_ber, rx_fifo_overflow=rx_fifo_overflow, rx_fifo_bad_frame=rx_fifo_bad_frame, rx_fifo_good_frame=rx_fifo_good_frame, ifg_delay=ifg_delay) @always(delay(4)) def clkgen(): clk.next = not clk tx_clk.next = not tx_clk rx_clk.next = not rx_clk logic_clk.next = not logic_clk load_bit_offset = [] @instance def shift_bits(): bit_offset = 0 last_data = 0 while True: yield clk.posedge if load_bit_offset: bit_offset = load_bit_offset.pop(0) if serdes_rx_bitslip: bit_offset += 1 bit_offset = bit_offset % 66 data = int(serdes_rx_data_int) << 2 | int(serdes_rx_hdr_int) out_data = ((last_data | data << 66) >> 66 - bit_offset) & 0x3ffffffffffffffff last_data = data serdes_rx_data.next = out_data >> 2 serdes_rx_hdr.next = out_data & 3 @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 tx_rst.next = 1 rx_rst.next = 1 logic_rst.next = 1 yield clk.posedge rst.next = 0 tx_rst.next = 0 rx_rst.next = 0 logic_rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge ifg_delay.next = 12 # testbench stimulus yield clk.posedge print("test 1: test rx packet") current_test.next = 1 test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(32)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() serdes_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame)) yield axis_sink.wait() rx_frame = axis_sink.recv() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame yield delay(100) yield clk.posedge print("test 2: test tx packet") current_test.next = 2 test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(32)) test_frame.update_fcs() axis_frame = test_frame.build_axis() axis_source.send(axis_frame) yield serdes_sink.wait() rx_frame = serdes_sink.recv() assert rx_frame.data[0:8] == bytearray( b'\x55\x55\x55\x55\x55\x55\x55\xD5') eth_frame = eth_ep.EthFrame() eth_frame.parse_axis_fcs(rx_frame.data[8:]) print(hex(eth_frame.eth_fcs)) print(hex(eth_frame.calc_fcs())) assert len(eth_frame.payload.data) == 46 assert eth_frame.eth_fcs == eth_frame.calc_fcs() assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac assert eth_frame.eth_src_mac == test_frame.eth_src_mac assert eth_frame.eth_type == test_frame.eth_type assert eth_frame.payload.data.index(test_frame.payload.data) == 0 yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters DATA_WIDTH = 64 CTRL_WIDTH = (DATA_WIDTH / 8) HDR_WIDTH = 2 BIT_REVERSE = 0 SCRAMBLER_DISABLE = 0 PRBS31_ENABLE = 1 TX_SERDES_PIPELINE = 2 RX_SERDES_PIPELINE = 2 SLIP_COUNT_WIDTH = 3 COUNT_125US = 1250 / 6.4 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) rx_clk = Signal(bool(0)) rx_rst = Signal(bool(0)) tx_clk = Signal(bool(0)) tx_rst = Signal(bool(0)) xgmii_txd = Signal(intbv(0)[DATA_WIDTH:]) xgmii_txc = Signal(intbv(0)[CTRL_WIDTH:]) serdes_rx_data = Signal(intbv(0)[DATA_WIDTH:]) serdes_rx_hdr = Signal(intbv(1)[HDR_WIDTH:]) tx_prbs31_enable = Signal(bool(0)) rx_prbs31_enable = Signal(bool(0)) serdes_rx_data_int = Signal(intbv(0)[DATA_WIDTH:]) serdes_rx_hdr_int = Signal(intbv(1)[HDR_WIDTH:]) # Outputs xgmii_rxd = Signal(intbv(0)[DATA_WIDTH:]) xgmii_rxc = Signal(intbv(0)[CTRL_WIDTH:]) serdes_tx_data = Signal(intbv(0)[DATA_WIDTH:]) serdes_tx_hdr = Signal(intbv(0)[HDR_WIDTH:]) serdes_rx_bitslip = Signal(bool(0)) rx_error_count = Signal(intbv(0)[7:]) rx_bad_block = Signal(bool(0)) rx_block_lock = Signal(bool(0)) rx_high_ber = Signal(bool(0)) # sources and sinks xgmii_source = xgmii_ep.XGMIISource() xgmii_source_logic = xgmii_source.create_logic(tx_clk, tx_rst, txd=xgmii_txd, txc=xgmii_txc, name='xgmii_source') xgmii_sink = xgmii_ep.XGMIISink() xgmii_sink_logic = xgmii_sink.create_logic(rx_clk, rx_rst, rxd=xgmii_rxd, rxc=xgmii_rxc, name='xgmii_sink') serdes_source = baser_serdes_ep.BaseRSerdesSource() serdes_source_logic = serdes_source.create_logic( rx_clk, tx_data=serdes_rx_data_int, tx_header=serdes_rx_hdr_int, name='serdes_source') serdes_sink = baser_serdes_ep.BaseRSerdesSink() serdes_sink_logic = serdes_sink.create_logic(tx_clk, rx_data=serdes_tx_data, rx_header=serdes_tx_hdr, name='serdes_sink') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, rx_clk=rx_clk, rx_rst=rx_rst, tx_clk=tx_clk, tx_rst=tx_rst, xgmii_txd=xgmii_txd, xgmii_txc=xgmii_txc, xgmii_rxd=xgmii_rxd, xgmii_rxc=xgmii_rxc, serdes_tx_data=serdes_tx_data, serdes_tx_hdr=serdes_tx_hdr, serdes_rx_data=serdes_rx_data, serdes_rx_hdr=serdes_rx_hdr, serdes_rx_bitslip=serdes_rx_bitslip, rx_error_count=rx_error_count, rx_bad_block=rx_bad_block, rx_block_lock=rx_block_lock, rx_high_ber=rx_high_ber, tx_prbs31_enable=tx_prbs31_enable, rx_prbs31_enable=rx_prbs31_enable) @always(delay(4)) def clkgen(): clk.next = not clk rx_clk.next = not rx_clk tx_clk.next = not tx_clk load_bit_offset = [] @instance def shift_bits(): bit_offset = 0 last_data = 0 while True: yield clk.posedge if load_bit_offset: bit_offset = load_bit_offset.pop(0) if serdes_rx_bitslip: bit_offset += 1 bit_offset = bit_offset % 66 data = int(serdes_rx_data_int) << 2 | int(serdes_rx_hdr_int) out_data = ((last_data | data << 66) >> 66 - bit_offset) & 0x3ffffffffffffffff last_data = data serdes_rx_data.next = out_data >> 2 serdes_rx_hdr.next = out_data & 3 @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 tx_rst.next = 1 rx_rst.next = 1 yield clk.posedge rst.next = 0 tx_rst.next = 0 rx_rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus # wait for block lock while not rx_block_lock: yield clk.posedge # dump garbage while not xgmii_sink.empty(): xgmii_sink.recv() yield clk.posedge print("test 1: test RX packet") current_test.next = 1 test_frame = bytearray(range(128)) xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame) xgmii_source.send(xgmii_frame) yield serdes_sink.wait() rx_frame = serdes_sink.recv() assert rx_frame.data == xgmii_frame.data assert xgmii_sink.empty() assert serdes_sink.empty() yield delay(100) yield clk.posedge print("test 2: test TX packet") current_test.next = 2 test_frame = bytearray(range(128)) xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame) serdes_source.send(xgmii_frame) yield xgmii_sink.wait() rx_frame = xgmii_sink.recv() assert rx_frame.data == xgmii_frame.data assert xgmii_sink.empty() assert serdes_sink.empty() yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters DATA_WIDTH = 64 CTRL_WIDTH = (DATA_WIDTH / 8) HDR_WIDTH = 2 BIT_REVERSE = 0 SCRAMBLER_DISABLE = 0 PRBS31_ENABLE = 1 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) xgmii_txd = Signal(intbv(0)[DATA_WIDTH:]) xgmii_txc = Signal(intbv(0)[CTRL_WIDTH:]) tx_prbs31_enable = Signal(bool(0)) # Outputs serdes_tx_data = Signal(intbv(0)[DATA_WIDTH:]) serdes_tx_hdr = Signal(intbv(0)[HDR_WIDTH:]) # sources and sinks source = xgmii_ep.XGMIISource() source_logic = source.create_logic(clk, rst, txd=xgmii_txd, txc=xgmii_txc, name='source') sink = baser_serdes_ep.BaseRSerdesSink() sink_logic = sink.create_logic(clk, rx_data=serdes_tx_data, rx_header=serdes_tx_hdr, name='sink') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, xgmii_txd=xgmii_txd, xgmii_txc=xgmii_txc, serdes_tx_data=serdes_tx_data, serdes_tx_hdr=serdes_tx_hdr, tx_prbs31_enable=tx_prbs31_enable) @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus for payload_len in list(range(16, 34)): yield clk.posedge print("test 1: test packet, length %d" % payload_len) current_test.next = 1 test_frame = bytearray(range(payload_len)) xgmii_frame = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame) source.send(xgmii_frame) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame.data assert sink.empty() yield delay(100) yield clk.posedge print("test 2: back-to-back packets, length %d" % payload_len) current_test.next = 2 test_frame1 = bytearray(range(payload_len)) test_frame2 = bytearray(range(payload_len)) xgmii_frame1 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame1) xgmii_frame2 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame2) source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame1.data yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame2.data assert sink.empty() yield delay(100) yield clk.posedge print("test 3: errored frame, length %d" % payload_len) current_test.next = 3 test_frame1 = bytearray(range(payload_len)) test_frame2 = bytearray(range(payload_len)) xgmii_frame1 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame1) xgmii_frame2 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame2) xgmii_frame1.error = 1 source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() #assert rx_frame.data == xgmii_frame1.data yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame2.data assert sink.empty() yield delay(100) yield clk.posedge print("test 4: PRBS31 generation") current_test.next = 4 tx_prbs31_enable.next = True yield delay(100) prbs_gen = prbs31(66) prbs_data = [next(prbs_gen) for x in range(100)] for k in range(20): yield clk.posedge data = int(serdes_tx_data) << 2 | int(serdes_tx_hdr) assert data in prbs_data tx_prbs31_enable.next = False yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters DATA_WIDTH = 64 CTRL_WIDTH = (DATA_WIDTH/8) HDR_WIDTH = 2 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) xgmii_txd = Signal(intbv(0)[DATA_WIDTH:]) xgmii_txc = Signal(intbv(0)[CTRL_WIDTH:]) # Outputs encoded_tx_data = Signal(intbv(0)[DATA_WIDTH:]) encoded_tx_hdr = Signal(intbv(0)[HDR_WIDTH:]) # sources and sinks source = xgmii_ep.XGMIISource() source_logic = source.create_logic( clk, rst, txd=xgmii_txd, txc=xgmii_txc, name='source' ) sink = baser_serdes_ep.BaseRSerdesSink() sink_logic = sink.create_logic( clk, rx_data=encoded_tx_data, rx_header=encoded_tx_hdr, scramble=False, name='sink' ) # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation( "vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, xgmii_txd=xgmii_txd, xgmii_txc=xgmii_txc, encoded_tx_data=encoded_tx_data, encoded_tx_hdr=encoded_tx_hdr ) @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus for payload_len in list(range(16,34)): yield clk.posedge print("test 1: test packet, length %d" % payload_len) current_test.next = 1 test_frame = bytearray(range(payload_len)) xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame) source.send(xgmii_frame) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame.data assert sink.empty() yield delay(100) yield clk.posedge print("test 2: back-to-back packets, length %d" % payload_len) current_test.next = 2 test_frame1 = bytearray(range(payload_len)) test_frame2 = bytearray(range(payload_len)) xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame1) xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame2) source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame1.data yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame2.data assert sink.empty() yield delay(100) yield clk.posedge print("test 3: errored frame, length %d" % payload_len) current_test.next = 3 test_frame1 = bytearray(range(payload_len)) test_frame2 = bytearray(range(payload_len)) xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame1) xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame2) xgmii_frame1.error = 1 source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() #assert rx_frame.data == xgmii_frame1.data yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame2.data assert sink.empty() yield delay(100) raise StopSimulation return instances()