def BTND_released(self, args):
global lock
self.BTND.configure(image=button_off)
self.BTND.grid()
BTND_state = 0
states = {}
all_states = {"T10":SW0_state, "T9":SW1_state, "V9":SW2_state, "M8":SW3_state, "N8":SW4_state,\
"U8":SW5_state, "V8":SW6_state, "T5":SW7_state, "A8":BTNU_state, "C4":BTNL_state, "B8":BTNS_state,\
"D9":BTNR_state, "C9":BTND_state, "V10":CLK}
for elem in inputs:
states[elem] = all_states[ucf[elem]]
(out_vals, null) = fpga.execute(inputs, states, outputs, ops, lock)
rep_output(out_vals, lock)
def SW7_toggle(self, args):
global SW7_state
global lock
SW7_state ^= 1
self.SW7.configure(image=switch_on if SW7_state else switch_off)
self.SW7.grid()
states = {}
all_states = {"T10":SW0_state, "T9":SW1_state, "V9":SW2_state, "M8":SW3_state, "N8":SW4_state,\
"U8":SW5_state, "V8":SW6_state, "T5":SW7_state, "A8":BTNU_state, "C4":BTNL_state, "B8":BTNS_state,\
"D9":BTNR_state, "C9":BTND_state, "V10":CLK}
for elem in inputs:
states[elem] = all_states[ucf[elem]]
(out_vals, null) = fpga.execute(inputs, states, outputs, ops, lock)
rep_output(out_vals, lock)
def clock_pulse():
global clk_id
global lock
clk_id = app.after(4, clock_pulse)
if lock == 1: return
global CLK
global ops
CLK ^= 1
states = {}
all_states = {"T10":SW0_state, "T9":SW1_state, "V9":SW2_state, "M8":SW3_state, "N8":SW4_state,\
"U8":SW5_state, "V8":SW6_state, "T5":SW7_state, "A8":BTNU_state, "C4":BTNL_state, "B8":BTNS_state,\
"D9":BTNR_state, "C9":BTND_state, "V10":CLK}
for elem in inputs:
states[elem] = all_states[ucf[elem]]
(out_vals, ops) = fpga.execute(inputs, states, outputs, ops, lock)
rep_output(out_vals, lock)
def open_file():
global clk_id
global lock
if clk_id != -1: app.after_cancel(clk_id)
global inputs
global outputs
global ops
global ucf
global seg
global AN_state
global CLK
global AN0_id
global AN1_id
global AN2_id
global AN3_id
inputs = []
outputs = []
ops = []
ucf = {}
seg = 0
AN_state = [1, 1, 1, 1]
CLK = 0
AN0_id = -1
AN1_id = -1
AN2_id = -1
AN3_id = -1
(inputs, outputs, ops, ucf) = fpga.interpret_file(
filedialog.askopenfilename(initialdir=".",
title="Open Schematic",
filetypes=[("Schematic files", "*.sch")]),
"main")
states = {}
all_states = {"T10":SW0_state, "T9":SW1_state, "V9":SW2_state, "M8":SW3_state, "N8":SW4_state,\
"U8":SW5_state, "V8":SW6_state, "T5":SW7_state, "A8":BTNU_state, "C4":BTNL_state, "B8":BTNS_state,\
"D9":BTNR_state, "C9":BTND_state, "V10":CLK}
for elem in inputs:
states[elem] = all_states[ucf[elem]]
(out_vals, ops) = fpga.execute(inputs, states, outputs, ops, lock)
rep_output(out_vals, lock)
if any(ucf[elem] == "V10" for elem in inputs):
clk_id = app.after(4, clock_pulse)