def test_output(NO): LOGNO = NO _, _, _, dout = assemble(main, LOGN, LOGNI, LOGNO, mode='parallel') output = DefineOutput(dout, LOGN, NO) assert len(output.pc) == LOGN assert len(output.O) == NO
def test_asm(): mem, seq, din, dout = assemble(prog, LOGN, LOGNI, LOGNO) #print(mem) assert mem == [[[1, 0], [0], [1, 0, 0, 0, 0], [1, 0, 0, 0, 0]], [[1, 0], [0], [0, 1, 0, 0, 0], [0, 1, 0, 0, 0]], [[1, 0], [0], [1, 1, 0, 0, 0], [0, 0, 1, 0, 0]], [[0, 0], [0], [1, 0, 1, 0, 0], [1, 0, 1, 0, 0]], [[0, 1], [0], [1, 0, 1, 0, 0], [1, 0, 1, 0, 0]], [[1, 0], [0], [1, 1, 1, 0, 0], [0, 1, 1, 0, 0]], [[0, 0], [0], [0, 0, 0, 1, 0], [0, 0, 0, 1, 0]], [[0, 1], [0], [0, 0, 0, 1, 0], [0, 0, 0, 1, 0]], [[1, 0], [0], [1, 1, 0, 1, 0], [1, 0, 0, 1, 0]], [[1, 0], [1], [1, 1, 0, 1, 0], [0, 1, 0, 1, 0]], [[0, 1], [0], [0, 0, 1, 1, 0], [0, 0, 1, 1, 0]], [[0, 0], [0], [0, 0, 1, 1, 0], [0, 0, 1, 1, 0]], [[1, 0], [0], [1, 0, 1, 1, 0], [1, 1, 1, 1, 0]], [[1, 0], [1], [0, 1, 1, 1, 0], [1, 1, 1, 1, 0]], [[0, 0], [0], [0, 0, 0, 0, 1], [0, 0, 0, 0, 1]], [[0, 1], [0], [0, 0, 0, 0, 1], [0, 0, 0, 0, 1]], [[1, 0], [0], [1, 0, 0, 0, 1], [0, 1, 0, 0, 1]], [[1, 0], [1], [0, 0, 1, 0, 1], [1, 1, 0, 0, 1]], [[1, 0], [1], [1, 1, 0, 0, 1], [0, 0, 1, 0, 1]], [[0, 1], [0], [1, 0, 1, 0, 1], [1, 0, 1, 0, 1]], [[0, 0], [0], [1, 0, 1, 0, 1], [1, 0, 1, 0, 1]], [[1, 0], [0], [0, 0, 0, 0, 0], [0, 0, 0, 0, 0]], [[1, 0], [0], [0, 0, 0, 0, 0], [1, 1, 1, 0, 1]], [[1, 0], [0], [0, 0, 0, 1, 1], [0, 0, 0, 0, 0]], [[1, 0], [0], [0, 0, 0, 0, 0], [0, 0, 0, 0, 0]], [[1, 0], [0], [1, 1, 0, 1, 1], [0, 1, 0, 1, 1]], [[1, 0], [0], [1, 1, 0, 1, 1], [0, 0, 1, 1, 1]], [[1, 0], [0], [1, 0, 1, 1, 1], [1, 0, 1, 1, 1]], [[1, 0], [0], [0, 0, 1, 1, 1], [1, 0, 1, 1, 1]], [[0, 1], [0], [0, 1, 1, 1, 1], [0, 1, 1, 1, 1]], [[0, 0], [0], [1, 1, 1, 1, 1], [1, 1, 1, 1, 1]], [[1, 0], [0], [0, 0, 0, 0, 0], [0, 0, 0, 0, 0]]]
def test_input(NI): LOGNI = clog2(NI) _, _, din, _ = assemble(main, LOGN, LOGNI, LOGNO) input = DefineInput(din, LOGN, LOGNI) assert len(input.pc) == LOGN assert len(input.I) == NI print(input)
def test_decoded_output(NO): if NO == 1: LOGNO = clog2(NO + 1) + 1 else: LOGNO = clog2(NO) + 1 _, _, _, dout = assemble(main, LOGN, LOGNI, LOGNO) output = DefineDecodedOutput(dout, LOGN, LOGNO, NO) assert len(output.pc) == LOGN assert len(output.O) == NO
def test_decoded_clock(has_ce, has_reset): NO = 2 LOGNO = clog2(NO) + 1 _, _, _, dout = assemble(main, LOGN, LOGNI, LOGNO) output = DefineDecodedOutput(dout, LOGN, LOGNO, NO, has_ce=has_ce, has_reset=has_reset) assert len(output.pc) == LOGN assert len(output.O) == NO assert not has_ce or hasattr(output, 'CE') assert not has_reset or hasattr(output, 'RESET')
from bit1.isa import nop, delay from bit1.isa import jump from bit1.isa import if0, if1, ifelse from bit1.isa import skip, skipif0, skipif1 from bit1.isa import halt set( O0 ) clr( O0 ) mov( I0, O0 ) not_( I0, O0 ) and_( I0, I1, O0 ) or_( I0, I1, O0 ) xor( I0, I1, O0 ) delay(1) jump( 0 ) if0( I0, 0 ) if1( I0, 0 ) ifelse( I0, 0, 0 ) skipif0( I0 ) #skipif1( I0 ) skip_( ) pause( I0 ) nop() halt( ) mem, _, _, _ = assemble(prog, LOGN, LOGNI, LOGNO) disassemble(mem)
def test_seq(): _, control, _, _ = assemble(main, LOGN, LOGNI, LOGNO) seq = DefineSeq(control, LOGN) assert len(seq.O) == LOGN print(seq)