def create_agent(self, network):
if network.check_consistency() is False:
return self.INCONSISTENT
if network.check_grounding() is False:
return self.NOT_GROUNDED
for module, super_module in network.super_modules.items():
if super_module in network.module_dictionary:
network.unit_dic[super_module].add_submodule(
module, network.unit_dic[module])
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug("Adding a module {} to {}.".format(
module, super_module))
# Main logic
top_module = brica1.Module()
for unit_key in network.unit_dic.keys():
if unit_key not in network.super_modules:
if isinstance(network.unit_dic[unit_key], brica1.Module):
top_module.add_submodule(unit_key,
network.unit_dic[unit_key])
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug(
"Adding a module {} to a BriCA agent.".format(
unit_key))
# agent = brica1.Agent(scheduler)
agent = brica1.Agent()
agent.add_submodule("__Runtime_Top_Module", top_module)
self.unit_dic = network.unit_dic
return agent
def test_lagging(self):
s = brica1.RealTimeSyncScheduler()
ca = brica1.Agent(s)
c = TimeReporterComponent()
CompSet = brica1.ComponentSet()
CompSet.add_component("C", c, 0)
ModA = brica1.Module()
ModA.add_component("CompSet", CompSet)
ca.add_submodule("ModA", ModA)
s.set_interval(0.1)
c.delay = 0
ca.step()
scheduled_time = s.current_time + s.interval
ca.step()
self.assertGreater(s.current_time, scheduled_time)
self.assertLessEqual(abs(s.current_time - scheduled_time), TOLERANCE)
self.assertFalse(s.lagged)
c_interval = 0.2
c.delay = c_interval
ca.step()
self.assertTrue(s.lagged)
def test_component(self):
s = brica1.VirtualTimeSyncScheduler(1.0)
ca = brica1.CognitiveArchitecture(s)
zero = numpy.zeros(3, dtype=numpy.short)
v = numpy.array([1, 2, 3], dtype=numpy.short)
CompA = brica1.ConstantComponent()
CompB = brica1.PipeComponent()
CompC = brica1.NullComponent()
ModA = brica1.Module()
ModA.add_component("CompA", CompA)
ModA.add_component("CompB", CompB)
ModA.add_component("CompC", CompC)
CompA.set_state("out", v)
CompA.make_out_port("out", 3)
CompB.make_in_port("in", 3)
CompB.connect(CompA, "out", "in")
CompB.make_out_port("out", 3)
CompB.set_map("in", "out")
CompC.make_in_port("in", 3)
CompC.connect(CompB, "out", "in")
ca.add_submodule("ModA", ModA)
self.assertTrue((CompA.get_state("out") == v).all())
self.assertIsNot(CompA.get_state("out"), v)
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == v ).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v).all())
self.assertTrue((CompB.get_in_port("in").buffer == v).all())
self.assertTrue((CompB.get_out_port("out").buffer == v).all())
self.assertTrue((CompC.get_in_port("in").buffer == v).all())
def create_agent(self, scheduler):
""" Add top level modules to a BriCA agent (to be called after load_file).
Args:
A brica1.Scheduler object
Returns:
A BriCA agent
"""
# Checking grounding
sub_modules = self.__sub_modules()
for unit_key in self.__unit_dic:
if not unit_key in sub_modules:
try:
module = self.__unit_dic[unit_key]
component = module.get_component(unit_key)
# TODO: Setting aliases here according to the current spec.
for port in module.in_ports:
length = module.get_in_port(port).buffer.shape[0]
component.make_in_port(port, length)
component.alias_in_port(module, port, port)
for port in module.out_ports:
length = module.get_out_port(port).buffer.shape[0]
component.make_out_port(port, length)
component.alias_out_port(module, port, port)
except KeyError:
print >> sys.stderr, "Module " + unit_key + " at the bottom not grounded as a Component!"
return
# Checking undefined modules
for unit_key in self.__super_modules:
if not unit_key in self.__unit_dic:
print >> sys.stderr, "SuperModule " + unit_key + " not defined!"
for unit_key in sub_modules:
if not unit_key in self.__unit_dic:
print >> sys.stderr, "SuperModule " + unit_key + " not defined!"
# Main logic
top_module = brica1.Module()
for unit_key in self.__unit_dic.keys():
if not unit_key in self.__super_modules:
if isinstance(self.__unit_dic[unit_key], brica1.Module):
top_module.add_submodule(unit_key,
self.__unit_dic[unit_key])
print "Adding a module " + unit_key + " to a BriCA agent."
agent = brica1.Agent(scheduler)
agent.add_submodule("__Runtime_Top_Module", top_module)
return agent
def __add_a_module(self, module):
module_name = module["Name"].strip()
if module_name == "":
return
module_name = self.__prefix_base_name_space(
module_name) # Prefixing the base name space
if not module_name in self.__unit_dic:
print "Creating " + module_name + "."
self.__unit_dic[module_name] = brica1.Module(
) # New Module instance
if module_name in self.__super_modules and self.__super_modules[
module_name] in self.__unit_dic:
# Registering it as a submodule according to previously defined hierarchy.
self.__unit_dic[
self.__super_modules[module_name]].add_submodule(
self.__unit_dic[module_name])
for submodule in self.__super_modules:
# Registering it as a supermodule according to previously defined hierarchy.
if self.__super_modules[
submodule] == module_name and submodule in self.__unit_dic:
self.__unit_dic[module_name].add_submodule(
self.__unit_dic[submodule])
if "ImplClass" in module:
# if an implementation class is specified
implclass = module["ImplClass"].strip()
if implclass != "":
print "Use the existing ImplClass " + implclass + " for " + module_name + "."
try:
component = eval(implclass +
'()') # New ImplClass instance
self.__unit_dic[module_name].add_component(
module_name, component)
except:
print >> sys.stderr, "Component " + implclass + " not found for " + module_name + "!"
if "SuperModule" in module:
supermodule = module["SuperModule"].strip()
if supermodule != "":
supermodule = self.__prefix_base_name_space(supermodule)
self.__add_subunit(supermodule, module_name)
if "SubModules" in module:
for submodule in module["SubModules"]:
submodule = self.__prefix_base_name_space(submodule)
self.__add_subunit(module_name, submodule)
def _(bm):
s = brica1.VirtualTimeSyncScheduler(1.0)
agent = brica1.Agent(s)
compA = brica1.ConstantComponent()
compB = brica1.NullComponent()
mod = brica1.Module();
mod.add_component('compA', compA)
mod.add_component('compB', compB)
compA.make_out_port('out', 256*256*3)
compB.make_in_port('in', 256*256*3)
brica1.connect((compA, 'out'), (compB, 'in'))
agent.add_submodule('mod', mod)
for _ in bm:
agent.step()
def relayer():
Comp = brica1.PipeComponent()
Comp.make_in_port("in", 3)
Comp.make_out_port("out", 3)
Comp.set_map("in", "out")
Mod = brica1.Module()
Mod.make_in_port("in", 3)
Mod.make_out_port("out", 3)
Mod.add_component("Comp", Comp)
Scheduler = brica1.RealTimeSyncScheduler()
Agent = brica1.Agent(Scheduler)
Agent.make_in_port("in", 3)
Agent.make_out_port("out", 3)
Agent.add_submodule("Mod", Mod)
brica1.alias_in_port((Agent, "in"), (Mod, "in"))
brica1.alias_out_port((Agent, "out"), (Mod, "out"))
brica1.alias_in_port((Mod, "in"), (Comp, "in"))
brica1.alias_out_port((Mod, "out"), (Comp, "out"))
def converter(msg):
return np.array(list(msg.data), dtype=np.int16)
Adapter = brica1.ros.ROSAdapter("relayer")
Adapter.setup_subscriber("chatter0", Int16MultiArray, "out", 3, converter)
Adapter.setup_publisher("chatter1", "in", 3)
brica1.connect((Adapter, "out"), (Agent, "in"))
brica1.connect((Agent, "out"), (Adapter, "in"))
while not rospy.is_shutdown():
Agent.step()
print "Agent in port: {}".format(Agent.get_in_port("in").buffer)
print "Agent out port: {}".format(Agent.get_out_port("out").buffer)
mnist['data'] = mnist['data'].astype(np.float32)
mnist['data'] /= 255
mnist['target'] = mnist['target'].astype(np.int32)
N_train = 60000
x_train, x_test = np.split(mnist['data'], [N_train])
y_train, y_test = np.split(mnist['target'], [N_train])
N_test = y_test.size
f = open('sda.pkl', 'rb')
stacked_autoencoder = pickle.load(f)
f.close()
scheduler = brica1.VirtualTimeSyncScheduler()
agent = brica1.Agent(scheduler)
module = brica1.Module()
module.add_component("stacked_autoencoder", stacked_autoencoder)
agent.add_submodule("module", module)
time = 0.0
sum_loss1 = 0
sum_loss2 = 0
sum_loss3 = 0
sum_loss4 = 0
sum_accuracy = 0
for batchnum in xrange(0, N_test, batchsize):
x_batch = x_test[batchnum:batchnum + batchsize]
y_batch = y_test[batchnum:batchnum + batchsize]
motor_comp = module["Base.OutputModule"] \
.get_component("Base.OutputModule")
else:
agent = brica1.Agent(scheduler)
visual_comp = VisualAreaComponent()
motor_comp = MotorAreaComponent()
hipp_comp = HippocampusComponent()
CompSet = brica1.ComponentSet()
CompSet.add_component("visual_area_component", visual_comp, 0)
CompSet.add_component("hippocampus_component", hipp_comp, 1)
CompSet.add_component("motor_area_component", motor_comp, 2)
main_module = brica1.Module()
main_module.add_component("component_set", CompSet)
# visual to hippocampus
visual_comp.set_state("out_body_position", np.zeros(2, dtype=np.short))
visual_comp.make_out_port("out_body_position", 2)
hipp_comp.make_in_port("in_body_position", 2)
brica1.connect((visual_comp, "out_body_position"),
(hipp_comp, "in_body_position"))
# visual to motor
motor_comp.make_in_port("in_body_position", 2)
brica1.connect((visual_comp, "out_body_position"),
(motor_comp, "in_body_position"))
visual_comp.set_state("out_body_velocity", np.zeros(2,
dtype=np.float32))
svm = SVMComponent(2)
svm.fit(X, y)
RFC = RandomForestClassifierComponent(2)
RFC.fit(X, y)
SR = SVMvsRFC_Component(1)
# Connect the components
brica1.connect((feeder, "out0"), (svm, "in0"))
brica1.connect((feeder, "out0"), (RFC, "in0"))
brica1.connect((svm, "out0"), (SR, "in0"))
brica1.connect((RFC, "out0"), (SR, "in1"))
# Add components to module
mod = brica1.Module()
mod.add_component("feeder", feeder)
mod.add_component("svm", svm)
mod.add_component("RFC", RFC)
mod.add_component("SR", SR)
# Setup scheduler and agent
s = brica1.VirtualTimeSyncScheduler()
a = brica1.Agent(s)
a.add_submodule("mod", mod)
# Test the classifier
svm_result = []
RFC_result = []
svm_vs_RFC = []
def check_consistency(self):
"""
Args:
None
return:
true iff no fatal inconsistency in the network
function:
see the consistency check section below.
"""
for module_name in self.module_dictionary:
if module_name not in self.unit_dic:
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug("Creating {}.".format(module_name))
self.unit_dic[module_name] = brica1.Module(
) # New Module instance
# SuperModules of consistency check
for module, superModule in self.super_modules.items():
if superModule not in self.module_dictionary:
app_logger.error(
"Super Module {} is not defined!".format(superModule))
return False
# Loop check
if self.__loop_check(superModule, module):
app_logger.error(
"Loop detected while trying to add {} as a subunit to {}!".
format(module, superModule))
return False
# SubModules of consistency check
for superModule, subModules in self.sub_modules.items():
for subModule in subModules:
if subModule not in self.module_dictionary:
app_logger.error(
"Sub Module {} is not defined!".format(subModule))
return False
# Loop check
if self.__loop_check(superModule, subModule):
app_logger.error(
"Loop detected while trying to add {} as a subunit to {}!"
.format(superModule, subModule))
return False
# Port of consistency check
for module_name in self.module_dictionary:
ports = self.module_dictionary[module_name]["Ports"]
if len(ports) == 0:
app_logger.error(
"The specified module {} does not have the port!".format(
module_name))
return False
for port in ports:
if not module_name + "." + port in self.__ports:
app_logger.error(
"The specified module {} does not have the port!".
format(module_name))
return False
for port_name, v in self.__ports.items():
# Fatal if the specified modules have not been defined.
if "Module" not in v:
app_logger.error(
"Module is not defined in the port {}!".format(port_name))
return False
module_name = v["Module"]
if module_name not in self.module_dictionary:
app_logger.error(
"Specified module {} is not defined in the port {}!".
format(module_name, port_name))
return False
# Fatal if the shape has not been defined.
if "Shape" not in v:
app_logger.error(
"Shape is not defined in the port {}!".format(port_name))
return False
length = v["Shape"]
if length < 1:
app_logger.error(
"Incorrect length of Shape for the port {}!".format(
port_name))
return False
# Fatal if the specified modules do not have the port, abort with a message.
module = self.module_dictionary[module_name]
pv = port_name.split(".")
last_port_name = pv[len(pv) - 1]
if last_port_name not in module["Ports"]:
app_logger.error(
"Port {} is not defined in the module {}!".format(
last_port_name, module_name))
return False
module = self.unit_dic[module_name]
if v["IO"] == "Input":
module.make_in_port(last_port_name, length)
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug(
"Creating an input port {} (length {}) to {}.".format(
last_port_name, length, module_name))
elif v["IO"] == "Output":
module.make_out_port(last_port_name, length)
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug(
"Creating an output port {} (length {}) to {}.".format(
last_port_name, length, module_name))
# Connection of consistency check
for k, v in self.__connections.items():
# Fatal if the specified ports have not been defined.
if not v[0] in self.__ports:
app_logger.error(
"The specified port {} is not defined in connection {}.".
format(v[0], k))
return False
if not v[1] in self.__ports:
app_logger.error(
"The specified port {} is not defined in connection {}.".
format(v[1], k))
return False
tp = v[0].split(".")
to_port = tp[len(tp) - 1]
fp = v[1].split(".")
from_port = fp[len(fp) - 1]
to_unit = self.__ports[v[0]]["Module"]
from_unit = self.__ports[v[1]]["Module"]
# if from_unit & to_unit belong to the same level
if ((from_unit not in self.__super_sub_modules) and (to_unit not in self.__super_sub_modules)) or \
(from_unit in self.__super_sub_modules and to_unit in self.__super_sub_modules and (
self.__super_sub_modules[from_unit] == self.__super_sub_modules[to_unit])):
try:
fr_port_obj = self.unit_dic[from_unit].get_out_port(
from_port)
to_port_obj = self.unit_dic[to_unit].get_in_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
app_logger.error("Port dimension unmatch!")
return False
# Creating a connection
brica1.connect((self.unit_dic[from_unit], from_port),
(self.unit_dic[to_unit], to_port))
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug(
"Creating a connection from {} of {} to {} of {}".
format(from_port, from_unit, to_port, to_unit))
except:
app_logger.error(
"adding a connection from {} to {} on the same level"
" but not from an output port to an input port!".
format(from_unit, to_unit))
return False
# else if from_unit is the direct super module of the to_unit
elif to_unit in self.__super_sub_modules and self.__super_sub_modules[
to_unit] == from_unit:
try:
fr_port_obj = self.unit_dic[from_unit].get_in_port(
from_port)
to_port_obj = self.unit_dic[to_unit].get_in_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
app_logger.error("Port dimension unmatch!")
return False
# Creating a connection (alias)
self.unit_dic[to_unit].alias_in_port(
self.unit_dic[from_unit], from_port, to_port)
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug(
"Creating a connection (alias) from {} of {} to {} of {}."
.format(from_port, from_unit, to_port, to_unit))
except:
app_logger.error(
"Error adding a connection from the super module {} to {} "
"but not from an input port to an input port!".format(
from_unit, to_unit))
return False
# else if to_unit is the direct super module of the from_unit
elif from_unit in self.__super_sub_modules and self.__super_sub_modules[
from_unit] == to_unit:
try:
fr_port_obj = self.unit_dic[from_unit].get_out_port(
from_port)
to_port_obj = self.unit_dic[to_unit].get_out_port(to_port)
if fr_port_obj.buffer.shape != to_port_obj.buffer.shape:
app_logger.error("Port dimension unmatch!")
return False
# Creating a connection (alias)
self.unit_dic[from_unit].alias_out_port(
self.unit_dic[to_unit], to_port, from_port)
if app_logger.isEnabledFor(logging.DEBUG):
app_logger.debug(
"Creating a connection (alias) from {} of {} to {} of {}."
.format(from_port, from_unit, to_port, to_unit))
except:
app_logger.error(
"Error adding a connection from {} to its super module {} "
"but not from an output port to an output port!".
format(from_unit, to_unit))
return False
# else connection level error!
else:
app_logger.error(
"Trying to add a connection between units {} and {} in a remote level!"
.format(from_unit, to_unit))
return False
return True
def test_nested(self):
s = brica1.VirtualTimeScheduler()
ca = brica1.CognitiveArchitecture(s)
zero = numpy.zeros(3, dtype=numpy.short)
v = numpy.array([1, 2, 3], dtype=numpy.short)
CompA = brica1.ConstantComponent()
CompB = brica1.PipeComponent()
CompC = brica1.NullComponent()
CompA.offset = 2.0
CompB.offset = 0.0
CompC.offset = 1.0
CompA.interval = 5.0
CompB.interval = 5.0
CompC.interval = 5.0
ModA = brica1.Module()
ModB = brica1.Module()
ModC = brica1.Module()
SupA = brica1.Module()
SupB = brica1.Module()
SupC = brica1.Module()
Top = brica1.Module()
CompA.set_state("out", v)
CompA.make_out_port("out", 3)
CompB.make_in_port("in", 3)
CompB.make_out_port("out", 3)
CompB.set_map("in", "out")
CompC.make_in_port("in", 3)
ModA.make_out_port("out", 3)
ModB.make_in_port("in", 3)
ModB.make_out_port("out", 3)
ModC.make_in_port("in", 3)
SupA.make_out_port("out", 3)
SupB.make_in_port("in", 3)
SupB.make_out_port("out", 3)
SupC.make_in_port("in", 3)
SupA.add_submodule("ModA", ModA)
SupB.add_submodule("ModB", ModB)
SupC.add_submodule("ModC", ModC)
ModA.add_component("CompA", CompA)
ModB.add_component("CompB", CompB)
ModC.add_component("CompC", CompC)
# Out ports must be aliased inside-out
CompA.alias_out_port(ModA, "out", "out")
ModA.alias_out_port(SupA, "out", "out")
# In ports must be aliased outside-in
ModB.alias_in_port(SupB, "in", "in")
CompB.alias_in_port(ModB, "in", "in")
# Out ports must be aliased inside-out
CompB.alias_out_port(ModB, "out", "out")
ModB.alias_out_port(SupB, "out", "out")
# In ports must be aliased outside-in
ModC.alias_in_port(SupC, "in", "in")
CompC.alias_in_port(ModC, "in", "in")
SupB.connect(SupA, "out", "in")
SupC.connect(SupB, "out", "in")
Top.add_submodule("SupA", SupA)
Top.add_submodule("SupB", SupB)
Top.add_submodule("SupC", SupC)
ca.add_submodule("Top", Top)
self.assertTrue((CompA.get_state("out") == v).all())
self.assertIsNot(CompA.get_state("out"), v)
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == zero).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == zero).all())
self.assertTrue((SupB.get_in_port("in").buffer == zero).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == zero).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == zero).all())
self.assertTrue((SupB.get_in_port("in").buffer == zero).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 5.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == zero).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == zero).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == zero).all())
self.assertTrue((SupB.get_in_port("in").buffer == zero).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 6.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == zero).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == zero).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == zero).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 7.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == v ).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 10.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == v ).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 11.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == zero).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == zero).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == v ).all())
self.assertTrue((SupB.get_out_port("out").buffer == zero).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 12.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v ).all())
self.assertTrue((CompB.get_in_port("in").buffer == v ).all())
self.assertTrue((CompB.get_out_port("out").buffer == v ).all())
self.assertTrue((CompC.get_in_port("in").buffer == zero).all())
self.assertTrue((ModA.get_out_port("out").buffer == v ).all())
self.assertTrue((ModB.get_in_port("in").buffer == v ).all())
self.assertTrue((ModB.get_out_port("out").buffer == v ).all())
self.assertTrue((ModC.get_in_port("in").buffer == zero).all())
self.assertTrue((SupA.get_out_port("out").buffer == v ).all())
self.assertTrue((SupB.get_in_port("in").buffer == v ).all())
self.assertTrue((SupB.get_out_port("out").buffer == v ).all())
self.assertTrue((SupC.get_in_port("in").buffer == zero).all())
self.assertEquals(time, 15.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v).all())
self.assertTrue((CompB.get_in_port("in").buffer == v).all())
self.assertTrue((CompB.get_out_port("out").buffer == v).all())
self.assertTrue((CompC.get_in_port("in").buffer == v).all())
self.assertTrue((ModA.get_out_port("out").buffer == v).all())
self.assertTrue((ModB.get_in_port("in").buffer == v).all())
self.assertTrue((ModB.get_out_port("out").buffer == v).all())
self.assertTrue((ModC.get_in_port("in").buffer == v).all())
self.assertTrue((SupA.get_out_port("out").buffer == v).all())
self.assertTrue((SupB.get_in_port("in").buffer == v).all())
self.assertTrue((SupB.get_out_port("out").buffer == v).all())
self.assertTrue((SupC.get_in_port("in").buffer == v).all())
self.assertEquals(time, 16.0)
time = ca.step()
self.assertTrue((CompA.get_out_port("out").buffer == v).all())
self.assertTrue((CompB.get_in_port("in").buffer == v).all())
self.assertTrue((CompB.get_out_port("out").buffer == v).all())
self.assertTrue((CompC.get_in_port("in").buffer == v).all())
self.assertTrue((ModA.get_out_port("out").buffer == v).all())
self.assertTrue((ModB.get_in_port("in").buffer == v).all())
self.assertTrue((ModB.get_out_port("out").buffer == v).all())
self.assertTrue((ModC.get_in_port("in").buffer == v).all())
self.assertTrue((SupA.get_out_port("out").buffer == v).all())
self.assertTrue((SupB.get_in_port("in").buffer == v).all())
self.assertTrue((SupB.get_out_port("out").buffer == v).all())
self.assertTrue((SupC.get_in_port("in").buffer == v).all())
self.assertEquals(time, 17.0)
