Python cbus_read_nodes示例

示例#1

#!/usr/bin/python

import cbus
nodes = cbus.cbus_read_nodes('ipbus_test.xml')
ctrl = nodes['CTRLREG']
idreg = nodes['IDREG']
stat = nodes['STATREG']
l1set = nodes['LFSR1_SET']
l1shift = nodes['LFSR1_SHIFT']
l1read = nodes['LFSR1_READ']
l2set = nodes['LFSR2_SET']
l2shift = nodes['LFSR2_SHIFT']
l2read = nodes['LFSR2_READ']
cbus.bus_delay(250)
print hex(idreg.read())
print "Simulating the shift register"
l1set.write(1)
for i in range(0, 10):
    print hex(l1read.read())
    l1shift.write(0)

示例#2

#!/usr/bin/python3
import cbus
nodes = cbus.cbus_read_nodes('gen', 'file://agwb_MAIN_address.xml')
cbus.bus_delay(100)
print("Test the ID")
print("ID read:" + hex(nodes['ID'].read()))
print("VER read:" + hex(nodes['VER'].read()))
cbus.bus_delay(250)
print("LINKS1 ID read:" + hex(nodes['LINKS[0].ID'].read()))
print("LINKS1 VER read:" + hex(nodes['LINKS[0].VER'].read()))
cbus.bus_delay(250)
print("LINKS1 STATUS read:" + hex(nodes['LINKS[0].STATUS'].read()))
cbus.bus_delay(250)
print("LINKS1 CTRL.START write")
nodes['LINKS[0].CTRL.START'].write(1)
cbus.bus_delay(250)
print("LINKS4 STATUS read:" + hex(nodes['LINKS[4].STATUS'].read()))
cbus.bus_delay(250)
print("Now we test bitfields")
print("LINKS4 CTRL.START write")
nodes['LINKS[4].CTRL.START'].write(1)
nodes['CTRL.CLK_ENABLE'].write(1)
cbus.bus_delay(30)
nodes['CTRL.CLK_FREQ'].write(0xc)
cbus.bus_delay(30)
nodes['CTRL.PLL_RESET'].write(1)
cbus.bus_delay(30)
nodes['CTRL.CLK_ENABLE'].write(0)
cbus.bus_delay(30)
nodes['CTRL.CLK_FREQ'].write(0x5)
cbus.bus_delay(30)

示例#3

文件： wb_test.py 项目： zwx11205131/addr_gen_wb

#!/usr/bin/python3
import cbus
nodes = cbus.cbus_read_nodes('gen', 'MAIN_address.xml')
cbus.bus_delay(100)
print("Test the ID")
print("ID read:" + hex(nodes['ID'].read()))
print("VER read:" + hex(nodes['VER'].read()))
cbus.bus_delay(250)
print("LINKS1 ID read:" + hex(nodes['LINKS[0].ID'].read()))
print("LINKS1 VER read:" + hex(nodes['LINKS[0].VER'].read()))
cbus.bus_delay(250)
print("LINKS1 STATUS read:" + hex(nodes['LINKS[0].STATUS'].read()))
cbus.bus_delay(250)
print("LINKS1 CTRL write")
nodes['LINKS[0].CTRL'].write(0xdce432)
cbus.bus_delay(250)
print("LINKS4 STATUS read:" + hex(nodes['LINKS[4].STATUS'].read()))
cbus.bus_delay(250)
print("LINKS4 CTRL write")
nodes['LINKS[4].CTRL'].write(0x35678)
print("Now we test bitfields")
nodes['CTRL.CLK_ENABLE'].write(1)
cbus.bus_delay(30)
nodes['CTRL.CLK_FREQ'].write(0xc)
cbus.bus_delay(30)
nodes['CTRL.PLL_RESET'].write(1)
cbus.bus_delay(30)
nodes['CTRL.CLK_ENABLE'].write(0)
cbus.bus_delay(30)
nodes['CTRL.CLK_FREQ'].write(0x5)
cbus.bus_delay(30)

示例#4

文件： ipbus_test.py 项目： wzab/vextproj

#!/usr/bin/python

import cbus
nodes=cbus.cbus_read_nodes('ipbus_test.xml')
ctrl=nodes['CTRLREG']
idreg=nodes['IDREG']
stat=nodes['STATREG']
l1set=nodes['LFSR1_SET']
l1shift=nodes['LFSR1_SHIFT']
l1read=nodes['LFSR1_READ']
l2set=nodes['LFSR2_SET']
l2shift=nodes['LFSR2_SHIFT']
l2read=nodes['LFSR2_READ']
cbus.bus_delay(250)
print hex(idreg.read())
print "Simulating the shift register"
l1set.write(1)
for i in range(0,10):
   print hex(l1read.read())
   l1shift.write(0)