def add_read(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
s.append(HDLAssign(rd_data, root.h_reg_rdat_int))
s.append(HDLAssign(rd_ack, root.h_rd_ack1_int))
elif isinstance(n, tree.Submap):
s.append(HDLComment("Submap {}".format(n.name)))
if n.c_interface == 'wb-32-be':
s.append(HDLAssign(rd_data, n.h_bus['dato']))
rdproc.stmts.append(HDLAssign(n.h_rd, bit_0))
s.append(HDLAssign(n.h_rd, isigs.rd_int))
s.append(HDLAssign(isigs.rd_ack, n.h_bus['ack']))
return
elif n.c_interface == 'sram':
return
else:
raise AssertionError
elif isinstance(n, tree.Array):
s.append(HDLComment("RAM {}".format(n.name)))
# TODO: handle list of registers!
r = n.children[0]
rdproc.sensitivity.append(r.h_sig_dato)
# Output ram data
s.append(HDLAssign(rd_data, r.h_sig_dato))
# Set rd signal to ram
s.append(HDLAssign(r.h_sig_rd, isigs.rd_int))
# But set it to 0 when the ram is not selected.
rdproc.stmts.append(HDLAssign(r.h_sig_rd, bit_0))
# Use delayed ack as ack.
s.append(HDLAssign(rd_ack, root.h_rd_ack1_int))
return
else:
# Blocks have been handled.
raise AssertionError
def gen_hdl_no_regrdmux(root, module, isigs):
module.stmts.append(HDLAssign(isigs.Loc_RegRdData, isigs.CRegRdData))
module.stmts.append(HDLAssign(isigs.Loc_RegRdOK, isigs.CRegRdOK))
module.stmts.append(HDLComment(None))
gen_hdl_locregrd2regrd(module.stmts, isigs)
module.stmts.append(HDLComment(None))
def gen_hdl_no_cregrdmux_dff(root, module, isigs):
module.stmts.append(
HDLAssign(isigs.Loc_CRegRdData, HDLReplicate(bit_0, None)))
module.stmts.append(HDLAssign(isigs.Loc_CRegRdOK, bit_0))
module.stmts.append(HDLAssign(isigs.Loc_CRegWrOK, bit_0))
module.stmts.append(HDLComment(None))
gen_hdl_cregrdmux_asgn(module.stmts, isigs)
module.stmts.append(HDLComment(None))
def add_read(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
if n.access != 'wo':
add_read_reg(s, n, off)
elif isinstance(n, tree.Submap):
pass
elif isinstance(n, tree.Array):
s.append(HDLComment("RAM {}".format(n.name)))
else:
# Blocks have been handled.
raise AssertionError
def gen_hdl_regrdmux_dff(root, module, pfx, isigs):
proc = HDLSync(root.h_bus['clk'], None)
proc.name = '{}RegRdMux_DFF'.format(pfx)
gen_hdl_locregrd2regrd(proc.sync_stmts, isigs)
# proc.sync_stmts.append(HDLAssign(isigs.RegWrOK, isigs.Loc_RegWrOK))
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_ext_bus_asgn(n, acc, root, module):
adr_sz = ilog2(n.c_size) - root.c_addr_word_bits
adr_lo = root.c_addr_word_bits
if not root.h_bussplit:
module.stmts.append(
HDLAssign(n.h_addr, HDLSlice(root.h_bus['adr'], adr_lo, adr_sz)))
module.stmts.append(HDLAssign(n.h_sel, n.h_sel_sig))
if acc in READ_ACCESS:
if root.h_bussplit:
module.stmts.append(
HDLAssign(n.h_rdaddr,
HDLSlice(root.h_bus['adro'], adr_lo, adr_sz)))
module.stmts.append(HDLAssign(n.h_rdsel, n.h_rdsel_sig))
module.stmts.append(
HDLAssign(n.h_rdmem, HDLAnd(n.h_rdsel_sig, root.h_bus['rd'])))
if acc in WRITE_ACCESS:
if root.h_bussplit:
module.stmts.append(
HDLAssign(n.h_wraddr,
HDLSlice(root.h_bus['adri'], adr_lo, adr_sz)))
module.stmts.append(HDLAssign(n.h_wrsel, n.h_wrsel_sig))
module.stmts.append(
HDLAssign(n.h_wrmem, HDLAnd(n.h_wrsel_sig, root.h_bus['wr'])))
module.stmts.append(HDLAssign(n.h_wrdata, root.h_bus['dati']))
module.stmts.append(HDLComment(None))
def gen_hdl_areardmux(root, module, isigs, area, areas):
proc = HDLComb()
proc.name = 'AreaRdMux'
bus_addr = root.h_bus['adro']
proc.sensitivity.extend([bus_addr, isigs.MemRdData, isigs.MemRdDone])
first = []
last = first
for a in areas:
proc.sensitivity.extend([a.h_isigs.RdData, a.h_isigs.RdDone])
stmt = gen_hdl_area_decode(root, module, a, bus_addr)
stmt.then_stmts.append(HDLAssign(isigs.RdData, a.h_isigs.RdData))
stmt.then_stmts.append(HDLAssign(isigs.RdDone, a.h_isigs.RdDone))
if root.c_buserr:
proc.sensitivity.append(a.h_isigs.RdError)
stmt.then_stmts.append(HDLAssign(isigs.RdError, a.h_isigs.RdError))
if a.h_has_external:
proc.stmts.append(HDLAssign(a.h_rdsel_sig, bit_0))
stmt.then_stmts.append(HDLAssign(a.h_rdsel_sig, bit_1))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_mem2top_rd(root, module, isigs, last)
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_wrseldec(root, module, isigs, area, pfx, wrseldec):
proc = HDLComb()
proc.name = '{}WrSelDec'.format(pfx)
bus_addr = root.h_bus['adri']
proc.sensitivity.append(bus_addr)
for r in wrseldec:
for i in reversed(range(r.c_nwords)):
proc.stmts.append(HDLAssign(r.h_wrsel[i], bit_0))
sw = HDLSwitch(
HDLSlice(bus_addr, root.c_addr_word_bits,
ilog2(area.c_size) - root.c_addr_word_bits))
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.append(sw)
stmt.else_stmts.append(HDLAssign(isigs.Loc_CRegWrOK, bit_0))
proc.stmts.append(stmt)
else:
proc.stmts.append(sw)
for reg in wrseldec:
if reg.h_has_mux:
proc.sensitivity.append(reg.h_regok)
regok = reg.h_regok
else:
regok = bit_1
for i in reversed(range(reg.c_nwords)):
ch = HDLChoiceExpr(reg.h_gena_regaddr[i])
ch.stmts.append(HDLAssign(reg.h_wrsel[i], bit_1))
ch.stmts.append(HDLAssign(isigs.Loc_CRegWrOK, regok))
sw.choices.append(ch)
ch = HDLChoiceDefault()
ch.stmts.append(HDLAssign(isigs.Loc_CRegWrOK, bit_0))
sw.choices.append(ch)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_code_fields(n, root, decls):
decls.append(HDLComment('CODE FIELDS'))
def gen_one_cf(codes, pfx, sz, lo_idx=0):
for cf in codes:
cf = cf['code-field']
cst = HDLConstant(pfx + '_' + cf['name'],
sz,
lo_idx=lo_idx,
value=HDLBinConst(cf['code'], sz))
decls.append(cst)
for e in reversed(n.children):
if isinstance(e, tree.Reg):
# code-fields for fields
for f in e.children:
codes = get_gena(f, 'code-fields', None)
if codes is not None:
gen_one_cf(
codes,
'C_Code_{}_{}_{}'.format(root.name, e.name,
f.name), f.c_rwidth, f.lo)
# code-fiels for registers
codes = get_gena(e, 'code-fields', None)
if codes is not None:
width = max([(f.hi or f.lo) + 1 for f in e.children])
gen_one_cf(codes, 'C_Code_{}_{}'.format(root.name, e.name),
width, 0)
def gen_reg_psm(n, root, decls, name, pfx):
decls.append(HDLComment('Register Preset Masks : {}'.format(name)))
mpfx = 'C_PSM_{}'.format(pfx)
for e in n.children:
if isinstance(e, tree.Reg):
psm = compute_preset(e)
e.h_gena_psm = gen_mask(decls, psm, root, e, mpfx)
def gen_hdl_misc_root(root, module, isigs):
module.stmts.append(HDLAssign(root.h_bus['dato'], isigs.RdData))
module.stmts.append(HDLAssign(root.h_bus['rack'], isigs.RdDone))
module.stmts.append(HDLAssign(root.h_bus['wack'], isigs.WrDone))
if root.c_buserr:
module.stmts.append(HDLAssign(root.h_bus['rderr'], isigs.RdError))
module.stmts.append(HDLAssign(root.h_bus['wrerr'], isigs.WrError))
module.stmts.append(HDLComment(None))
def gen_hdl_no_area(root, module, isigs):
module.stmts.append(HDLAssign(isigs.RdData, isigs.MemRdData))
module.stmts.append(HDLAssign(isigs.RdDone, isigs.MemRdDone))
module.stmts.append(HDLAssign(isigs.WrDone, isigs.MemWrDone))
if root.c_buserr:
module.stmts.append(HDLAssign(isigs.RdError, isigs.MemRdError))
module.stmts.append(HDLAssign(isigs.WrError, isigs.MemWrError))
module.stmts.append(HDLComment(None))
def wire_bus_slave_wb32(root, stmts, n):
stmts.append(HDLComment("Assignments for submap {}".format(n.name)))
stmts.append(HDLAssign(n.h_bus['cyc'], HDLOr(n.h_wr, n.h_rd)))
stmts.append(HDLAssign(n.h_bus['stb'], HDLOr(n.h_wr, n.h_rd)))
stmts.append(HDLAssign(n.h_bus['adr'], root.h_bus['adr']))
stmts.append(HDLAssign(n.h_bus['sel'], HDLReplicate(bit_1, 4)))
stmts.append(HDLAssign(n.h_bus['we'], n.h_wr))
stmts.append(HDLAssign(n.h_bus['dati'], root.h_bus['dati']))
def gen_reg_acm(n, root, decls, name, pfx):
decls.append(HDLComment('Register Auto Clear Masks : {}'.format(name)))
mpfx = 'C_ACM_{}'.format(pfx)
for e in n.children:
if isinstance(e, tree.Reg):
acm = compute_acm(e)
e.h_gena_acm = gen_mask(decls, acm, root, e, mpfx)
def add_read_process(root, module, isigs):
# Register read
rd_data = root.h_bus['dato']
rd_ack = isigs.rd_ack
rd_adr = root.h_bus.get('adr', None)
rdproc = HDLComb()
if rd_adr is not None:
rdproc.sensitivity.append(rd_adr)
if root.h_max_delay >= 1:
rdproc.sensitivity.extend(
[root.h_reg_rdat_int, root.h_rd_ack1_int, isigs.rd_int])
module.stmts.append(rdproc)
# All the read are ack'ed (including the read to unassigned addresses).
rdproc.stmts.append(HDLComment("By default ack read requests"))
rdproc.stmts.append(
HDLAssign(rd_data, HDLReplicate(bit_0, root.c_word_bits)))
rdproc.stmts.append(HDLAssign(rd_ack, bit_1))
def add_read(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
s.append(HDLAssign(rd_data, root.h_reg_rdat_int))
s.append(HDLAssign(rd_ack, root.h_rd_ack1_int))
elif isinstance(n, tree.Submap):
s.append(HDLComment("Submap {}".format(n.name)))
if n.c_interface == 'wb-32-be':
s.append(HDLAssign(rd_data, n.h_bus['dato']))
rdproc.stmts.append(HDLAssign(n.h_rd, bit_0))
s.append(HDLAssign(n.h_rd, isigs.rd_int))
s.append(HDLAssign(isigs.rd_ack, n.h_bus['ack']))
return
elif n.c_interface == 'sram':
return
else:
raise AssertionError
elif isinstance(n, tree.Array):
s.append(HDLComment("RAM {}".format(n.name)))
# TODO: handle list of registers!
r = n.children[0]
rdproc.sensitivity.append(r.h_sig_dato)
# Output ram data
s.append(HDLAssign(rd_data, r.h_sig_dato))
# Set rd signal to ram
s.append(HDLAssign(r.h_sig_rd, isigs.rd_int))
# But set it to 0 when the ram is not selected.
rdproc.stmts.append(HDLAssign(r.h_sig_rd, bit_0))
# Use delayed ack as ack.
s.append(HDLAssign(rd_ack, root.h_rd_ack1_int))
return
else:
# Blocks have been handled.
raise AssertionError
stmts = []
add_decoder(root, stmts, rd_adr, root, add_read)
rdproc.stmts.extend(stmts)
def gen_header(root, decls):
if hasattr(root, 'x_gena'):
cpfx = 'C_{}'.format(root.name)
ident_code = root.x_gena.get('ident-code')
if ident_code is not None:
width = root.c_word_size * tree.BYTE_SIZE
decls.append(HDLComment('Ident Code'))
decls.append(
HDLConstant(cpfx + '_IdentCode',
width,
value=HDLHexConst(ident_code, width)))
version = root.x_gena.get('map-version')
if version:
decls.append(HDLComment('Memory Map Version'))
cst = HDLConstant(cpfx + '_MemMapVersion',
32,
value=HDLHexConst(version, 32))
cst.eol_comment = '{}'.format(version)
decls.append(cst)
def gen_submap_addr(n, root, decls, name, pfx):
decls.append(HDLComment('Submap Addresses : {}'.format(name), nl=False))
# word_width = ilog2(root.c_word_size)
for e in n.children:
if isinstance(e, tree.Submap):
block_width = ilog2(e.c_size)
addr_width = ilog2(n.c_size) - block_width
addr = e.c_address >> block_width
cst = gen_addr_cst(decls, addr,
'C_Submap_{}_{}'.format(pfx, e.name),
addr_width, block_width, 1)
e.h_gena_area = cst
def generate_hdl(root):
isigs = Isigs()
root.h_max_delay = compute_max_delay(root)
module = gen_hdl_header(root, isigs)
# Add ports
iogroup = root.get_extension('x_hdl', 'iogroup')
if iogroup is not None:
root.h_itf = HDLInterface('t_' + iogroup)
module.global_decls.append(root.h_itf)
grp = module.add_port_group(iogroup, root.h_itf, True)
grp.comment = 'Wires and registers'
root.h_ports = grp
else:
root.h_itf = None
root.h_ports = module
add_ports(root, module, root)
module.stmts.append(HDLComment('Assign outputs'))
root.h_ram = None
root.h_ram_wr_dly = None
wire_regs(root, module, isigs, root)
module.stmts.append(HDLComment('Process for write requests.'))
add_write_process(root, module, isigs)
if root.h_max_delay >= 1:
root.h_reg_rdat_int = HDLSignal('reg_rdat_int', root.c_word_bits)
module.decls.append(root.h_reg_rdat_int)
root.h_rd_ack1_int = HDLSignal('rd_ack1_int')
module.decls.append(root.h_rd_ack1_int)
module.stmts.append(HDLComment('Process for registers read.'))
add_read_reg_process(root, module, isigs)
module.stmts.append(HDLComment('Process for read requests.'))
add_read_process(root, module, isigs)
return module
def gen_hdl_regdone(root, module, isigs, root_isigs, rd_delay, wr_delay):
asgn = HDLAssign(
isigs.RegRdDone,
HDLAnd(HDLIndex(root_isigs.Loc_VMERdMem, rd_delay), isigs.RegRdOK))
module.stmts.append(asgn)
asgn = HDLAssign(
isigs.RegWrDone,
HDLAnd(HDLIndex(root_isigs.Loc_VMEWrMem, wr_delay), isigs.CRegWrOK))
module.stmts.append(asgn)
module.stmts.append(HDLComment(None))
if root.c_buserr:
asgn = HDLAssign(
isigs.RegRdError,
HDLAnd(HDLIndex(root_isigs.Loc_VMERdMem, rd_delay),
HDLNot(isigs.RegRdOK)))
module.stmts.append(asgn)
asgn = HDLAssign(
isigs.RegWrError,
HDLAnd(HDLIndex(root_isigs.Loc_VMEWrMem, wr_delay),
HDLNot(isigs.CRegWrOK)))
module.stmts.append(asgn)
module.stmts.append(HDLComment(None))
def gen_hdl_regrdmux(root, module, isigs, area, pfx, rd_reg):
proc = HDLComb()
proc.name = '{}RegRdMux'.format(pfx)
bus_addr = root.h_bus['adro']
proc.sensitivity.append(bus_addr)
proc.sensitivity.append(isigs.CRegRdData)
proc.sensitivity.append(isigs.CRegRdOK)
for reg in rd_reg:
if reg.h_rdsel:
for i in reversed(range(reg.c_nwords)):
proc.stmts.append(HDLAssign(reg.h_rdsel[i], bit_0))
sw = HDLSwitch(
HDLSlice(bus_addr, root.c_addr_word_bits,
ilog2(area.c_size) - root.c_addr_word_bits))
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.append(sw)
stmt.else_stmts.append(HDLAssign(isigs.Loc_RegRdData,
isigs.CRegRdData))
stmt.else_stmts.append(HDLAssign(isigs.Loc_RegRdOK, isigs.CRegRdOK))
proc.stmts.append(stmt)
else:
proc.stmts.append(sw)
regok_sensitivity = []
for reg in rd_reg:
loc = reg.h_loc_SRFF or reg.h_loc
proc.sensitivity.append(loc)
if reg.h_has_mux:
regok_sensitivity.append(reg.h_regok)
regok = reg.h_regok
else:
regok = bit_1
for i in reversed(range(reg.c_nwords)):
ch = HDLChoiceExpr(reg.h_gena_regaddr[i])
val = loc
vwidth = reg.c_rwidth // reg.c_nwords
val = HDLSlice(val, i * root.c_word_bits, vwidth)
if vwidth < root.c_word_bits:
val = HDLZext(val, vwidth)
ch.stmts.append(HDLAssign(isigs.Loc_RegRdData, val))
ch.stmts.append(HDLAssign(isigs.Loc_RegRdOK, regok))
if reg.h_rdsel:
ch.stmts.append(HDLAssign(reg.h_rdsel[i], bit_1))
sw.choices.append(ch)
ch = HDLChoiceDefault()
ch.stmts.append(HDLAssign(isigs.Loc_RegRdData, isigs.CRegRdData))
ch.stmts.append(HDLAssign(isigs.Loc_RegRdOK, isigs.CRegRdOK))
proc.sensitivity.extend(regok_sensitivity)
sw.choices.append(ch)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_memory_data(n, root, decls, name, pfx):
decls.append(HDLComment('Memory Data : {}'.format(name), nl=False))
word_width = ilog2(root.c_word_size)
addr_width = ilog2(n.c_size) - word_width
for e in n.children:
if isinstance(e, tree.Array):
addr = e.c_address >> word_width
e.h_gena_sta = gen_addr_cst(decls, addr,
'C_Mem_{}_{}_Sta'.format(pfx, e.name),
addr_width, word_width, 1)
addr = (e.c_address + e.c_size - 1) >> word_width
e.h_gena_end = gen_addr_cst(decls, addr,
'C_Mem_{}_{}_End'.format(pfx, e.name),
addr_width, word_width, 1)
def gen_hdl_strobeseq(root, module, isigs):
proc = HDLSync(root.h_bus['clk'], None)
proc.name = 'StrobeSeq'
proc.sync_stmts.append(
HDLAssign(
isigs.Loc_VMERdMem,
HDLConcat(HDLSlice(isigs.Loc_VMERdMem, 0, 2), root.h_bus['rd'])))
proc.sync_stmts.append(
HDLAssign(
isigs.Loc_VMEWrMem,
HDLConcat(HDLSlice(isigs.Loc_VMEWrMem, 0, None),
root.h_bus['wr'])))
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_memrdmux(root, module, isigs, area, pfx, mems):
proc = HDLComb()
proc.name = pfx + 'MemRdMux'
bus_addr = root.h_bus['adro']
proc.sensitivity.extend([bus_addr, isigs.RegRdData, isigs.RegRdDone])
if root.c_buserr:
proc.sensitivity.append(isigs.RegRdError)
adr_sz = ilog2(area.c_size) - root.c_addr_word_bits
adr_lo = root.c_addr_word_bits
first = []
last = first
for m in mems:
data = m.children[0]
if data.access in READ_ACCESS:
proc.sensitivity.extend([m.h_rddata, m.h_rddone])
if root.c_buserr:
proc.sensitivity.append(m.h_rderror)
proc.stmts.append(HDLAssign(m.h_rdsel_sig, bit_0))
cond = HDLAnd(HDLGe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_sta),
HDLLe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_end))
stmt = HDLIfElse(cond)
if data.access in READ_ACCESS:
stmt.then_stmts.append(HDLAssign(m.h_rdsel_sig, bit_1))
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemRdData, m.h_rddata))
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemRdDone, m.h_rddone))
if root.c_buserr:
stmt.then_stmts.append(
HDLAssign(isigs.Loc_MemRdError, m.h_rderror))
else:
stmt.then_stmts.append(
HDLAssign(isigs.Loc_MemRdData, HDLReplicate(bit_0,
data.width)))
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemRdDone, bit_0))
if root.c_buserr:
stmt.then_stmts.append(
HDLAssign(isigs.Loc_MemRdError, root.h_bus['rd']))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_reg2locmem_rd(root, module, isigs, last)
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.extend(first)
gen_hdl_reg2locmem_rd(root, module, isigs, stmt.else_stmts)
proc.stmts.append(stmt)
else:
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def add_write(s, n, off):
if n is not None:
if isinstance(n, tree.Reg):
s.append(HDLComment(n.name))
if n.access in ['wo', 'rw']:
add_write_reg(s, n, off)
elif isinstance(n, tree.Submap):
s.append(HDLComment("Submap {}".format(n.name)))
if n.c_interface == 'wb-32-be':
wrproc.rst_stmts.append(HDLAssign(n.h_wr, bit_0))
wr_if.then_stmts.append(HDLAssign(n.h_wr, bit_0))
s.append(HDLAssign(n.h_wr, bit_1))
s.append(HDLAssign(isigs.wr_ack, n.h_bus['ack']))
return
elif n.c_interface == 'sram':
s.append(HDLAssign(n.h_wr_o, bit_1))
return
else:
raise AssertionError
elif isinstance(n, tree.Array):
# TODO: handle list of registers!
r = n.children[0]
wrproc.rst_stmts.append(HDLAssign(r.h_sig_wr, bit_0))
wr_if.else_stmts.append(HDLAssign(r.h_sig_wr, bit_0))
s2 = HDLIfElse(HDLEq(root.h_ram_wr_dly, bit_0))
s.append(s2)
s2.then_stmts.append(HDLAssign(r.h_sig_wr, bit_1))
s2.then_stmts.append(HDLAssign(root.h_ram_wr_dly, bit_1))
s2.else_stmts.append(HDLAssign(root.h_ram_wr_dly, bit_0))
s2.else_stmts.append(HDLAssign(isigs.wr_ack, bit_1))
return
else:
# Including blocks.
raise AssertionError
# All the write are ack'ed (including the write to unassigned
# addresses)
s.append(HDLAssign(isigs.wr_ack, bit_1))
def gen_hdl_components(root, module):
"Generate component declarations (but only the used ones)."
if root.h_has_srff:
comp = HDLComponent('SRFFxN')
param_n = HDLParam('N', typ='P', value=HDLNumber(16))
comp.params.append(param_n)
comp.ports.extend([
HDLPort('Clk'),
HDLPort('Rst', default=bit_0),
HDLPort('Set', HDLSub(param_n, HDLNumber(1))),
HDLPort('Clr', default=bit_0),
HDLPort('Q', HDLSub(param_n, HDLNumber(1)), dir='OUT')
])
module.decls.insert(0, comp)
module.decls.insert(1, HDLComment(None))
spec = HDLComponentSpec(comp, "CommonVisual.SRFFxN(V1)")
module.decls.insert(2, spec)
module.decls.insert(3, HDLComment(None))
if root.h_has_creg:
comp = HDLComponent('CtrlRegN')
param_n = HDLParam('N', typ='I', value=HDLNumber(16))
comp.params.append(param_n)
comp.ports.extend([
HDLPort('Clk'),
HDLPort('Rst'),
HDLPort('CRegSel'),
HDLPort('WriteMem'),
HDLPort('VMEWrData', HDLSub(param_n, HDLNumber(1))),
HDLPort('AutoClrMsk', HDLSub(param_n, HDLNumber(1))),
HDLPort('CReg', HDLSub(param_n, HDLNumber(1)), dir='OUT'),
HDLPort('Preset', HDLSub(param_n, HDLNumber(1)))
])
module.decls.insert(0, comp)
module.decls.insert(1, HDLComment(None))
spec = HDLComponentSpec(comp, "CommonVisual.CtrlRegN(V1)")
module.decls.insert(2, spec)
module.decls.insert(3, HDLComment(None))
if root.h_has_rmw:
comp = HDLComponent('RMWReg')
param_n = HDLParam('N', typ='N', value=HDLNumber(8))
comp.params.append(param_n)
comp.ports.extend([
HDLPort('VMEWrData',
HDLSub(HDLMul(HDLNumber(2), param_n), HDLNumber(1))),
HDLPort('Clk'),
HDLPort('AutoClrMsk', HDLSub(param_n, HDLNumber(1))),
HDLPort('Rst'),
HDLPort('CRegSel'),
HDLPort('CReg', HDLSub(param_n, HDLNumber(1)), dir='OUT'),
HDLPort('WriteMem'),
HDLPort('Preset', HDLSub(param_n, HDLNumber(1)))
])
module.decls.insert(0, comp)
module.decls.insert(1, HDLComment(None))
spec = HDLComponentSpec(comp, "CommonVisual.RMWReg(RMWReg)")
module.decls.insert(2, spec)
module.decls.insert(3, HDLComment(None))
def gen_hdl_cregrdmux(root, module, isigs, area, pfx, wrseldec):
proc = HDLComb()
proc.name = '{}CRegRdMux'.format(pfx)
bus_addr = root.h_bus['adro']
proc.sensitivity.append(bus_addr)
sw = HDLSwitch(
HDLSlice(bus_addr, root.c_addr_word_bits,
ilog2(area.c_size) - root.c_addr_word_bits))
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.append(sw)
stmt.else_stmts.append(
HDLAssign(isigs.Loc_CRegRdData, HDLReplicate(bit_0, None)))
stmt.else_stmts.append(HDLAssign(isigs.Loc_CRegRdOK, bit_0))
proc.stmts.append(stmt)
else:
proc.stmts.append(sw)
regok_sensitivity = []
for reg in wrseldec:
if reg.h_loc:
# NOTE: not needed for WO registers!
proc.sensitivity.append(reg.h_loc)
for i in reversed(range(reg.c_nwords)):
ch = HDLChoiceExpr(reg.h_gena_regaddr[i])
if reg.access == 'wo':
val = HDLReplicate(bit_0, None)
ok = bit_0
else:
val = reg.h_loc
regw = reg.c_rwidth // reg.c_nwords
val = HDLSlice(val, i * regw, regw)
if regw < root.c_word_bits:
val = HDLZext(val, root.c_word_bits)
if reg.h_has_mux:
if i == 0:
regok_sensitivity.append(reg.h_regok)
ok = reg.h_regok
else:
ok = bit_1
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdData, val))
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdOK, ok))
sw.choices.append(ch)
ch = HDLChoiceDefault()
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdData, HDLReplicate(bit_0, None)))
ch.stmts.append(HDLAssign(isigs.Loc_CRegRdOK, bit_0))
proc.sensitivity.extend(regok_sensitivity)
sw.choices.append(ch)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_hdl_memwrmux(root, module, isigs, area, pfx, mems):
proc = HDLComb()
proc.name = pfx + 'MemWrMux'
bus_addr = root.h_bus['adri']
proc.sensitivity.extend([bus_addr, isigs.RegWrDone])
if root.c_buserr:
proc.sensitivity.append(isigs.RegWrError)
adr_sz = ilog2(area.c_size) - root.c_addr_word_bits
adr_lo = root.c_addr_word_bits
first = []
last = first
for m in mems:
data = m.children[0]
set_wrsel = data.access == 'wo' or (data.access == 'rw'
and root.c_bussplit)
if set_wrsel:
proc.stmts.append(HDLAssign(m.h_wrsel_sig, bit_0))
cond = HDLAnd(HDLGe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_sta),
HDLLe(HDLSlice(bus_addr, adr_lo, adr_sz), m.h_gena_end))
stmt = HDLIfElse(cond)
if set_wrsel:
stmt.then_stmts.append(HDLAssign(m.h_wrsel_sig, bit_1))
if data.access in WRITE_ACCESS:
proc.sensitivity.append(m.h_wrdone)
done = m.h_wrdone
else:
done = bit_0
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemWrDone, done))
if root.c_buserr:
if data.access in WRITE_ACCESS:
proc.sensitivity.append(m.h_wrerror)
err = m.h_wrerror
else:
err = root.h_bus['wr']
stmt.then_stmts.append(HDLAssign(isigs.Loc_MemWrError, err))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_reg2locmem_wr(root, module, isigs, last)
if isinstance(area, (tree.Block, tree.Submap)):
stmt = gen_hdl_area_decode(root, module, area, bus_addr)
stmt.then_stmts.extend(first)
gen_hdl_reg2locmem_wr(root, module, isigs, stmt.else_stmts)
proc.stmts.append(stmt)
else:
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
def gen_reg_addr(n, root, decls, name, pfx):
decls.append(HDLComment('Register Addresses : {}'.format(name), nl=False))
word_width = ilog2(root.c_word_size)
addr_width = ilog2(n.c_size) - word_width
for reg in n.children:
if isinstance(reg, tree.Reg):
addr = reg.c_address // root.c_word_size
# FIXME: Gena looks to use 1 instead of word_width
num = reg.c_nwords
reg.h_gena_regaddr = []
for i in range(num):
cst = gen_addr_cst(
decls, addr + i,
'C_Reg_{}_{}{}'.format(pfx, reg.name,
subsuffix(num - i - 1, num)),
addr_width, word_width, 1)
reg.h_gena_regaddr.insert(0, cst)
def expand_wishbone(root, module, isigs):
"""Create wishbone interface."""
root.h_bus = {}
root.h_bus['rst'] = module.add_port('rst_n_i')
root.h_bus['clk'] = module.add_port('clk_i')
busgroup = root.get_extension('x_hdl', 'busgroup')
addr_bits = root.c_sel_bits + root.c_blk_bits - root.c_addr_word_bits
root.h_bus.update(
gen_wishbone(module, module, 'wb', addr_bits, root.c_word_bits, None,
False, busgroup is True))
root.h_bussplit = False
if isigs:
# Bus access
module.stmts.append(HDLComment('WB decode signals'))
add_decode_wb(root, module, isigs)
def gen_hdl_areawrmux(root, module, isigs, area, areas):
proc = HDLComb()
proc.name = 'AreaWrMux'
bus_addr = root.h_bus['adri']
proc.sensitivity.extend([bus_addr, isigs.MemWrDone])
first = []
last = first
for a in areas:
proc.sensitivity.append(a.h_isigs.WrDone)
stmt = gen_hdl_area_decode(root, module, a, bus_addr)
stmt.then_stmts.append(HDLAssign(isigs.WrDone, a.h_isigs.WrDone))
if root.c_buserr:
proc.sensitivity.append(a.h_isigs.WrError)
stmt.then_stmts.append(HDLAssign(isigs.WrError, a.h_isigs.WrError))
last.append(stmt)
last = stmt.else_stmts
gen_hdl_mem2top_wr(root, module, isigs, last)
proc.stmts.extend(first)
module.stmts.append(proc)
module.stmts.append(HDLComment(None))
