def write_char_test(dut):
"""
Description:
Test ID: 7
Expected Results:
**
"""
dut.rst <= 1
dut.test_id <= 7
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Ready")
yield Timer(CLK_PERIOD * 300)
control = 0x00
control |= 1 << BIT_CTRL_EN
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#Write a characer down
char_val = 0x0101
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 10)
def first_test(dut):
"""
Description:
*
Test ID: 0
Expected Results:
*
"""
CLK_WR_PERIOD = 10
CLK_RD_PERIOD = 10
dut.rst.setimmediatevalue(1)
dut.i_enable.setimmediatevalue(0)
dut.test_id.setimmediatevalue(0)
cocotb.fork(Clock(dut.clk, CLK_WR_PERIOD).start())
cocotb.fork(Clock(dut.rd_clk, CLK_RD_PERIOD).start())
ppu = NESPPU(dut, "PPU", dut.clk, width=480, height=272)
video_out = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
yield Timer(CLK_WR_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_WR_PERIOD * 10)
dut.rst <= 1
yield Timer(CLK_WR_PERIOD * 10)
dut.i_enable <= 1
cocotb.fork(ppu.run())
#cocotb.fork(read_video(dut, video_out))
cocotb.fork(video_out.read())
yield Timer(CLK_WR_PERIOD * 80000)
def setup_interfaces(self):
"""
Setup the DUT interfaces.
"""
# coefficients interface
self.coefficients_in_clk_gen = cocotb.fork(
Clock(self.dut.coefficients_in_aclk, self.CLK_PERIOD).start())
self.axism_coeffs_in = AXI4StreamMaster(self.dut, "coefficients_in",
self.dut.coefficients_in_aclk)
# input data interface
self.data_in_clk_gen = cocotb.fork(
Clock(self.dut.data_in_aclk, self.CLK_PERIOD).start())
self.axism_data_in = AXI4StreamMaster(self.dut, "data_in",
self.dut.data_in_aclk)
# output data interface
self.data_out_clk_gen = cocotb.fork(
Clock(self.dut.data_out_aclk, self.CLK_PERIOD).start())
self.axiss_data_out = AXI4StreamSlave(self.dut, "data_out",
self.dut.data_out_aclk)
# use the input data clock
self.data_in_clk_rising = yield RisingEdge(self.dut.data_out_aclk)
yield Timer(0)
async def setup_interfaces(self):
"""
Setup the DUT interfaces.
"""
# coefficients interface
if self.COEFF_STREAM:
self.coefficients_in_clk_gen = cocotb.fork(
Clock(self.dut.coefficients_in_aclk, self.CLK_PERIOD).start())
self.axism_coeffs_in = AXI4StreamMaster(
self.dut, "coefficients_in", self.dut.coefficients_in_aclk)
else:
self.coeffs_clk_gen = cocotb.fork(
Clock(self.dut.coeffs_axi_aclk, self.CLK_PERIOD).start())
self.axim_coeffs_in = AxiLiteMaster(self.dut, "coeffs_axi",
self.dut.coeffs_axi_aclk)
# input data interface
self.data_in_clk_gen = cocotb.fork(
Clock(self.dut.data_in_aclk, self.CLK_PERIOD).start())
self.axism_data_in = AXI4StreamMaster(self.dut, "data_in",
self.dut.data_in_aclk)
# output data interface
self.data_out_clk_gen = cocotb.fork(
Clock(self.dut.data_out_aclk, self.CLK_PERIOD).start())
self.axiss_data_out = AXI4StreamSlave(self.dut, "data_out",
self.dut.data_out_aclk)
# use the input data clock
self.data_in_clk_rising = await RisingEdge(self.dut.data_out_aclk)
await Timer(0)
def write_carriage_return(dut):
"""
Description:
Demonstrate writing characters down. This will also show that the
line pointers will increment (prev line, curr line, next line)
Test ID: 2
Expected Results:
**
"""
dut.rst <= 1
dut.test_id <= 2
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Ready")
yield Timer(CLK_PERIOD * 300)
control = 0x00
control |= 1 << BIT_CTRL_EN
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#Write a characer down
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 10)
#Write a characer down
char_val = 0x42
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 10)
#Write a carriage return
char_val = 0x0D
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 100)
def first_test(dut):
"""
Description:
*
Test ID: 0
Expected Results:
*
"""
dut.rst <= 1
dut.test_id <= 0
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Ready")
yield Timer(CLK_PERIOD * 300)
def run_nestest(dut):
"""
Description:
*
Test ID: 0
Expected Results:
*
"""
dut.rst <= 1
dut.test_id <= 0
#axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
nes = NESHCI(dut, "AXIML")
video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
dut.log.info("Video in start...")
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Ready")
yield nes.reset_hci()
yield nes.reset_console()
yield Timer(CLK_PERIOD * 10)
dut.log.info("Start video in AXIS")
cocotb.fork(video_in.read())
dut.log.info("Load ROM")
yield nes.load_rom("./nestest.nes")
dut.log.info("Waiting")
#yield Timer(CLK_PERIOD * 50000)
#yield Timer(CLK_PERIOD * 100000)
yield Timer(CLK_PERIOD * 200000)
def read_all_registers(dut):
"""
Description:
Read all registers from the core
Test ID: 0
Expected Results:
A value is successfully written to the
the register of the controller.
This value should be readable from the test bench
"""
dut.rst <= 1
dut.test_id <= 0
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_out = AXI4StreamMaster(dut, "AXIMS", dut.clk, width=24)
video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.rst <= 1
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Ready")
control = 0x02
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control = 0x01
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
yield Timer(CLK_PERIOD * 100)
#Read Back All the registers, make sure they make sense
data = yield axim.read(REG_STATUS)
yield Timer(CLK_PERIOD * 10)
if data != control:
raise TestFailure(
"REG_STATUS Register was not correct, should be: 0x%08 but read: 0x%08X"
% control, data)
data = yield axim.read(REG_VIDEO_IN_SIZE)
yield Timer(CLK_PERIOD * 10)
if data != (1280 * 720):
raise TestFailure(
"REG_VIDEO_IN_SIZE Register was not correct, should be: 0x%08 but read: 0x%08X"
% ((1280 * 720), data))
data = yield axim.read(REG_VIDEO_IN_WIDTH)
yield Timer(CLK_PERIOD * 10)
if data != 1280:
raise TestFailure(
"REG_VIDEO_IN_WIDTH Register was not correct, should be: 0x%08 but read: 0x%08X"
% (1280, data))
data = yield axim.read(REG_VIDEO_IN_HEIGHT)
yield Timer(CLK_PERIOD * 10)
if data != 720:
raise TestFailure(
"REG_VIDEO_IN_HEIGHT Register was not correct, should be: 0x%08 but read: 0x%08X"
% (720, data))
data = yield axim.read(REG_VIDEO_OUT_SIZE)
yield Timer(CLK_PERIOD * 10)
if data != (1280 * 720):
raise TestFailure(
"REG_VIDEO_OUT_SIZE Register was not correct, should be: 0x%08 but read: 0x%08X"
% ((1280 * 720), data))
data = yield axim.read(REG_VIDEO_OUT_WIDTH)
yield Timer(CLK_PERIOD * 10)
if data != 1280:
raise TestFailure(
"REG_VIDEO_OUT_WIDTH Register was not correct, should be: 0x%08 but read: 0x%08X"
% (1280, data))
data = yield axim.read(REG_VIDEO_OUT_HEIGHT)
yield Timer(CLK_PERIOD * 10)
if data != 720:
raise TestFailure(
"REG_VIDEO_OUT_HEIGHT Register was not correct, should be: 0x%08 but read: 0x%08X"
% (720, data))
data = yield axim.read(REG_VIDEO_IN_START_X)
yield Timer(CLK_PERIOD * 10)
if data != 0:
raise TestFailure(
"REG_VIDEO_IN_START_X Register was not correct, should be: 0x%08 but read: 0x%08X"
% (0, data))
data = yield axim.read(REG_VIDEO_IN_START_Y)
yield Timer(CLK_PERIOD * 10)
if data != 0:
raise TestFailure(
"REG_VIDEO_IN_START_Y Register was not correct, should be: 0x%08 but read: 0x%08X"
% (0, data))
data = yield axim.read(REG_IN_FILL_PIXEL)
yield Timer(CLK_PERIOD * 10)
if data != 0:
raise TestFailure(
"REG_IN_FILL_PIXEL Register was not correct, should be: 0x%08 but read: 0x%08X"
% (0, data))
def write_center_frame(dut):
"""
Description:
Write a single frame
Test ID: 4
Expected Results:
A value is successfully written to the
the register of the controller.
This value should be readable from the test bench
"""
dut.test_id <= 4
IMAGE_IN_WIDTH = 4
IMAGE_IN_HEIGHT = 4
IMAGE_IN_SIZE = IMAGE_IN_WIDTH * IMAGE_IN_HEIGHT
IMAGE_OUT_WIDTH = 2
IMAGE_OUT_HEIGHT = 2
IMAGE_OUT_SIZE = IMAGE_OUT_WIDTH * IMAGE_OUT_HEIGHT
IMAGE_IN_START_X = 1
IMAGE_IN_START_Y = 1
video = []
for y in range(IMAGE_IN_HEIGHT):
for x in range(IMAGE_IN_WIDTH):
video.append((IMAGE_IN_WIDTH * y) + x)
dut.rst <= 1
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_out = AXI4StreamMaster(dut, "AXIMS", dut.clk, width=24)
video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.rst <= 1
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Ready")
cocotb.fork(axis_slave_listener(video_in))
control = 0x02
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_IN_WIDTH, IMAGE_IN_WIDTH)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_IN_HEIGHT, IMAGE_IN_HEIGHT)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_IN_SIZE, IMAGE_IN_SIZE)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_OUT_WIDTH, IMAGE_OUT_WIDTH)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_OUT_HEIGHT, IMAGE_OUT_HEIGHT)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_OUT_SIZE, IMAGE_OUT_SIZE)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_IN_START_X, IMAGE_IN_START_X)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_IN_START_Y, IMAGE_IN_START_Y)
yield Timer(CLK_PERIOD * 10)
control = 0x01
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
yield video_out.write(video)
yield Timer(CLK_PERIOD * 500)
def write_full_page_char_backspace_test(dut):
"""
Description:
Test backspaces
Test ID: 6
Expected Results:
**
"""
#load_font_mem(dut.dut.cosd.font_buffer.mem, "../rtl/fontdata.mem")
dut.rst <= 1
dut.test_id <= 6
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Ready")
yield Timer(CLK_PERIOD * 300)
#Write a characer down
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 5)
#Write a characer down
char_val = 0x102
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 5)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 5)
control = 0x00
control |= 1 << BIT_CTRL_EN
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#control = 0x00
#control &= ~(1 << BIT_CTRL_EN)
#yield axim.write(REG_CONTROL, control)
yield video_in.read()
yield Timer(CLK_PERIOD * 100)
#Write a characer down
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
#Write a characer down
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x42
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x43
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x44
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x45
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x46
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x47
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x48
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x49
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x4A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
'''
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x4B
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x4C
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x4D
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
'''
yield Timer(CLK_PERIOD * 100)
#Insert a backspace
char_val = 0x08
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 50)
char_val = 0x08
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 100)
char_val = 0x08
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 100)
char_val = 0x08
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 100)
char_val = 0x08
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 100)
'''
char_val = 0x08
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 100)
char_val = 0x08
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 100)
'''
yield Timer(CLK_PERIOD * 4000)
def write_full_page_char_test(dut):
"""
Description:
Test ID: 5
Expected Results:
**
"""
#load_font_mem(dut.dut.cosd.font_buffer.mem, "../rtl/fontdata.mem")
dut.rst <= 1
dut.test_id <= 5
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Ready")
yield Timer(CLK_PERIOD * 300)
#Write a characer down
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 5)
#Write a characer down
char_val = 0x102
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 5)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 5)
control = 0x00
control |= 1 << BIT_CTRL_EN
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#control = 0x00
#control &= ~(1 << BIT_CTRL_EN)
#yield axim.write(REG_CONTROL, control)
yield video_in.read()
yield Timer(CLK_PERIOD * 2000)
control |= (1 << BIT_CTRL_CLEAR_SCREEN_STB)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 4000)
#Write a characer down
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
#Write a characer down
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x0A
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
char_val = 0x41
yield axim.write(REG_CONSOLE_CHAR, char_val)
yield Timer(CLK_PERIOD * 1)
yield Timer(CLK_PERIOD * 6000)
def first_test(dut):
"""
Description:
*
Test ID: 0
Expected Results:
*
"""
dut.rst <= 1
dut.test_id <= 0
#axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
nes = NESHCI(dut, "AXIML")
video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Ready")
yield nes.reset_hci()
yield nes.reset_console()
yield Timer(CLK_PERIOD * 10)
#Go into debug mode
yield nes.enter_debug()
data = yield nes.is_debug_enabled()
print "Debug enabled: %d" % data
# Send NOP down to the core
yield nes.nop()
#Go into debug mode
yield nes.exit_debug()
data = yield nes.is_debug_enabled()
print "Debug enabled: %d" % data
yield Timer(CLK_PERIOD * 30)
#Read a CPU Register
REG_ADDR = 0x00
yield nes.write_cpu_register(REG_ADDR, 0xAB)
data = yield nes.read_cpu_register(REG_ADDR)
print "CPU Register: 0x%02X: 0x%02X" % (REG_ADDR, data)
#Write to cpu memory
data_out = [0x00, 0x01, 0x02, 0x03]
yield nes.write_cpu_mem(0x00, data_out)
data = yield nes.read_cpu_mem(0x00, len(data_out))
print "Data: ",
for d in data:
print "0x%02X " % d,
print ""
#Write to ppu memory
data_out = [0x00, 0x01, 0x02, 0x03]
yield nes.write_ppu_mem(0x00, data_out)
data = yield nes.read_ppu_mem(0x00, len(data_out))
print "Data: ",
for d in data:
print "0x%02X " % d,
print ""
yield Timer(CLK_PERIOD * 10)
#yield nes.set_cart_config(0x01234567)
yield nes.load_rom("./nestest.nes")
yield Timer(CLK_PERIOD * 300)