def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self._can_read = False
self._can_write = False
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
if hasattr(self.bus, "read"):
self.bus.read.setimmediatevalue(0)
self._can_read = True
if hasattr(self.bus, "write"):
self.bus.write.setimmediatevalue(0)
v = self.bus.writedata.value
v.binstr = "x" * len(self.bus.writedata)
self.bus.writedata <= v
self._can_write = True
if hasattr(self.bus, "byteenable"):
self.bus.byteenable.setimmediatevalue(0)
if hasattr(self.bus, "cs"):
self.bus.cs.setimmediatevalue(0)
v = self.bus.address.value
v.binstr = "x" * len(self.bus.address)
self.bus.address.setimmediatevalue(v)
def __init__(self, entity, name, clock, **kwargs):
BusDriver.__init__(self, entity, name, clock, **kwargs)
self.bus.paddr.setimmediatevalue(0)
self.bus.pwdata.setimmediatevalue(0)
self.bus.psel.setimmediatevalue(0)
self.bus.pwrite.setimmediatevalue(0)
self.bus.penable.setimmediatevalue(0)
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
# Drive default values onto bus
self.bus.rd_en.setimmediatevalue(0)
self.reqs = []
def __init__(self, entity):
BusDriver.__init__(self, entity, "", entity.CLK_BX)
self.cmd = BinaryValue(bits=len(self.bus.CMD))
self.cmd <= 0
self.bus.TRIG_EXT <= 0
self.bus.CMD <= self.cmd
def __init__(self, entity, name="", default_values=None, *args, **kwargs):
'''
See the BusDriver definition for more information on the inputs.
'''
BusDriver.__init__(self, entity=entity, name=name, *args, **kwargs)
# Create separate write and read buses.
self.__wrbus = Bus(
entity=entity,
name="", # Intentionally done this way.
signals=self._wrsignals,
optional_signals=self._optional_signals,
bus_separator="")
self.__rdbus = Bus(
entity=entity,
name="", # Intentionally done this way.
signals=self._rdsignals,
bus_separator="")
# The Bus assigned in the BusDriver shall be the write Bus.
self.bus = self.__wrbus
# Set default values.
if default_values is None:
self.__default_values = self._default_values
else:
self.__default_values = default_values
self.set_defaults()
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self.bus.A.setimmediatevalue(5)
self.bus.B.setimmediatevalue(5)
self.log.debug("Test DrvM created")
self.busy_event = Event("%s_busy" % name)
self.busy = False
def __init__(self, entity, name, clock, debug=False):
BusDriver.__init__(self, entity, name, clock)
if debug:
self.log.setLevel(logging.DEBUG)
self.bus.act <= 0
self.bus.stb <= 0
self.data = Array('B')
def __init__(self, entity, name, clock, readlatency_min=1,
readlatency_max=1, memory=None, avl_properties={}):
BusDriver.__init__(self, entity, name, clock)
if avl_properties != {}:
for key, value in self._avalon_properties.items():
self._avalon_properties[key] = avl_properties.get(key, value)
if self._avalon_properties["burstCountUnits"] != "symbols":
self.log.error("Only symbols burstCountUnits is supported")
if self._avalon_properties["addressUnits"] != "symbols":
self.log.error("Only symbols addressUnits is supported")
self._burstread = False
self._burstwrite = False
self._readable = False
self._writeable = False
self._width = None
if hasattr(self.bus, "readdata"):
self._width = len(self.bus.readdata)
self._readable = True
if hasattr(self.bus, "writedata"):
width = len(self.bus.writedata)
if (self._width is not None) and self._width != width:
self.log.error("readdata and writedata bus" +
" are not the same size")
self._width = width
self._writeable = True
if hasattr(self.bus, "burstcount"):
if hasattr(self.bus, "readdatavalid"):
self._burstread = True
self._burstwrite = True
if not self._readable and not self._writeable:
raise TestError("Attempt to instantiate useless memory")
# Allow dual port RAMs by referencing the same dictionary
if memory is None:
self._mem = {}
else:
self._mem = memory
self._val = BinaryValue(bits=self._width, bigEndian=False)
self._readlatency_min = readlatency_min
self._readlatency_max = readlatency_max
self._responses = []
self._coro = cocotb.fork(self._respond())
if hasattr(self.bus, "readdatavalid"):
self.bus.readdatavalid.setimmediatevalue(0)
if hasattr(self.bus, "waitrequest"):
self.bus.waitrequest.setimmediatevalue(0)
if hasattr(self.bus, "readdatavalid"):
self.bus.readdatavalid.setimmediatevalue(0)
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self.bus.AWVALID.setimmediatevalue(0)
self.bus.WVALID.setimmediatevalue(0)
self.bus.ARVALID.setimmediatevalue(0)
self.bus.BREADY.setimmediatevalue(0)
self.bus.RREADY.setimmediatevalue(0)
#doubt whether we can use setimmediate value for signals greater than 1bit
self.bus.AWADDR <= 0
self.bus.AWSIZE <= 0
self.bus.AWPROT <= 0
self.bus.AWLEN <= 0
self.bus.AWBURST <= 0
self.bus.AWID <= 0
self.bus.WDATA <= 0
self.bus.WSTRB <= 0
self.bus.WLAST <= 0
self.bus.WID <= 0
self.bus.ARVALID <= 0
self.bus.ARADDR <= 0
self.bus.ARSIZE <= 0
self.bus.ARPROT <= 0
self.bus.ARLEN <= 0
self.bus.ARBURST <= 0
self.bus.ARID <= 0
self.bus.RREADY <= 0
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
"""
Deasserting the AXI4 signals
"""
self.bus.AWVALID.setimmediatevalue(0)
self.bus.WVALID.setimmediatevalue(0)
self.bus.ARVALID.setimmediatevalue(0)
self.bus.BREADY.setimmediatevalue(0)
self.bus.RREADY.setimmediatevalue(0)
self.bus.AWADDR <= 0
self.bus.AWSIZE <= 0
self.bus.AWPROT <= 0
self.bus.AWLEN <= 0
self.bus.AWBURST <= 0
self.bus.AWID <= 0
self.bus.WDATA <= 0
self.bus.WSTRB <= 0
self.bus.WLAST <= 0
self.bus.WID <= 0
self.bus.ARVALID <= 0
self.bus.ARADDR <= 0
self.bus.ARSIZE <= 0
self.bus.ARPROT <= 0
self.bus.ARLEN <= 0
self.bus.ARBURST <= 0
self.bus.ARID <= 0
self.bus.RREADY <= 0
def __init__(self, entity: SimHandleBase, name: str, clock: SimHandleBase,
**kwargs: Any):
BusDriver.__init__(self, entity, name, clock, **kwargs)
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
self.bus.AWVALID.setimmediatevalue(0)
self.bus.WVALID.setimmediatevalue(0)
self.bus.ARVALID.setimmediatevalue(0)
self.bus.BREADY.setimmediatevalue(1)
self.bus.RREADY.setimmediatevalue(1)
# Set the default value (0) for the unsupported signals, which
# translate to:
# * Transaction IDs to 0
# * Region identifier to 0
# * Normal (non-exclusive) access
# * Device non-bufferable access
# * Unprivileged, secure data access
# * No QoS
unsupported_signals = [
"AWID", "AWREGION", "AWLOCK", "AWCACHE", "AWPROT", "AWQOS", "ARID",
"ARREGION", "ARLOCK", "ARCACHE", "ARPROT", "ARQOS"
]
for signal in unsupported_signals:
try:
getattr(self.bus, signal).setimmediatevalue(0)
except AttributeError:
pass
# Mutex for each channel to prevent contention
self.write_address_busy = Lock(name + "_awbusy")
self.read_address_busy = Lock(name + "_arbusy")
self.write_data_busy = Lock(name + "_wbusy")
self.read_data_busy = Lock(name + "_rbusy")
self.write_response_busy = Lock(name + "_bbusy")
def __init__(self,
entity,
name,
clock,
memory,
callback=None,
event=None,
big_endian=False,
**kwargs):
BusDriver.__init__(self, entity, name, clock, **kwargs)
self.clock = clock
self.big_endian = big_endian
self.bus.ARREADY.setimmediatevalue(1)
self.bus.RVALID.setimmediatevalue(0)
self.bus.RLAST.setimmediatevalue(0)
self.bus.AWREADY.setimmediatevalue(1)
self._memory = memory
self.write_address_busy = Lock("%s_wabusy" % name)
self.read_address_busy = Lock("%s_rabusy" % name)
self.write_data_busy = Lock("%s_wbusy" % name)
cocotb.fork(self._read_data())
cocotb.fork(self._write_data())
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
self.bus.read.setimmediatevalue(0)
self.bus.write.setimmediatevalue(0)
self.bus.address.setimmediatevalue(0)
def __init__(self, entity, name, clock, readlatency_min=1,
readlatency_max=1, memory=None):
BusDriver.__init__(self, entity, name, clock)
self._readable = False
self._writeable = False
if hasattr(self.bus, "readdata"):
self._width = len(self.bus.readdata)
self._readable = True
if hasattr(self.bus, "writedata"):
self._width = len(self.bus.writedata)
self._writeable = True
if not self._readable and not self._writeable:
raise TestError("Attempt to instantiate useless memory")
# Allow dual port RAMs by referencing the same dictionary
if memory is None:
self._mem = {}
else:
self._mem = memory
self._val = BinaryValue(bits=self._width, bigEndian=False)
self._readlatency_min = readlatency_min
self._readlatency_max = readlatency_max
self._responses = []
self._coro = cocotb.fork(self._respond())
if hasattr(self.bus, "readdatavalid"):
self.bus.readdatavalid.setimmediatevalue(0)
if hasattr(self.bus, "waitrequest"):
self.bus.waitrequest.setimmediatevalue(0)
def __init__(self, entity, name, clock, rdlag=None, blag=None):
BusDriver.__init__(self, entity, name, clock)
self.name = name
# set read and write back channels simulation lag between AXI sets valid and host responds with
# ready. If None - drive these signals
self.log.debug ("MAXIGPMaster.__init__(): super done")
if rdlag is None:
self.bus.rready.setimmediatevalue(1)
else:
self.bus.xtra_rdlag.setimmediatevalue(rdlag)
if blag is None:
self.bus.bready.setimmediatevalue(1)
else:
self.bus.xtra_blag.setimmediatevalue(blag)
self.bus.awvalid.setimmediatevalue(0)
self.bus.wvalid.setimmediatevalue(0)
self.bus.arvalid.setimmediatevalue(0)
#just in case - set unimplemented in Zynq
self.bus.arlock.setimmediatevalue(0)
self.bus.arcache.setimmediatevalue(0)
self.bus.arprot.setimmediatevalue(0)
self.bus.arqos.setimmediatevalue(0)
self.bus.awlock.setimmediatevalue(0)
self.bus.awcache.setimmediatevalue(0)
self.bus.awprot.setimmediatevalue(0)
self.bus.awqos.setimmediatevalue(0)
self.busy_channels = {}
self.log.debug ("MAXIGPMaster.__init__(): pre-lock done")
#Locks on each subchannel
for chn in self._channels:
self.log.debug ("MAXIGPMaster.__init__(): chn = %s"%(chn))
self.busy_channels[chn]=Lock("%s_%s_busy"%(name,chn))
def __init__(self,
entity,
name,
clock,
wr_fifo_name = "WR",
wr_fifo_clk = None,
wr_fifo_clk_period = 10,
rd_fifo_name = "RD",
rd_fifo_clk = None,
rd_fifo_clk_period = 10):
BusDriver.__init__(self, entity, name, clock)
if wr_fifo_clk is None:
wr_fifo_clk = entity.WR_CLK
if rd_fifo_clk is None:
rd_fifo_clk = entity.RD_CLK
self.bus.EN.setimmediatevalue(0)
self.bus.ADR.setimmediatevalue(0)
self.bus.ADR_FIXED.setimmediatevalue(0)
self.bus.ADR_WRAP.setimmediatevalue(0)
self.bus.WR_RD.setimmediatevalue(0)
self.bus.COUNT.setimmediatevalue(0)
# Mutex for each channel that we master to prevent contention
self.command_busy = Lock("%s_wabusy" % name)
cocotb.fork(Clock(wr_fifo_clk, wr_fifo_clk_period).start())
cocotb.fork(Clock(rd_fifo_clk, rd_fifo_clk_period).start())
self.write_fifo = PPFIFOWritePath(entity, wr_fifo_name, wr_fifo_clk)
self.read_fifo = PPFIFOReadPath(entity, rd_fifo_name, rd_fifo_clk)
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self.busy_channel = Lock("%s_busy"%(name))
self.bus.wr.setimmediatevalue(0)
self.bus.rd.setimmediatevalue(0)
_float_signals((self.bus.addr, self.bus.din))
self.name = name
def __init__(self, entity, name, clock, debug = False):
BusDriver.__init__(self, entity, name, clock)
if debug:
self.log.setLevel(logging.DEBUG)
self.bus.act <= 0
self.bus.stb <= 0
self.data = Array('B')
def __init__(self, entity, name, clock, shape):
self.shape = shape
for idx in mat.matrix_indexes(self.shape):
self._signals.append(self.get_element_name(idx))
BusDriver.__init__(self, entity, name, clock)
self.clk = clock
self.buffer = []
def __init__(self, entity, name, clock, **kwargs):
BusDriver.__init__(self, entity, name, clock, **kwargs)
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
self.bus.DOUT.setimmediatevalue(0)
self.bus.RXFn.setimmediatevalue(1)
self.bus.TXEn.setimmediatevalue(1)
def __init__(self, entity, name, clock, **kwargs):
BusDriver.__init__(self, entity, name, clock, **kwargs)
self._can_read = False
self._can_write = False
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
if hasattr(self.bus, "read"):
self.bus.read.setimmediatevalue(0)
self._can_read = True
if hasattr(self.bus, "write"):
self.bus.write.setimmediatevalue(0)
v = self.bus.writedata.value
v.binstr = "x" * len(self.bus.writedata)
self.bus.writedata <= v
self._can_write = True
if hasattr(self.bus, "byteenable"):
self.bus.byteenable.setimmediatevalue(0)
if hasattr(self.bus, "cs"):
self.bus.cs.setimmediatevalue(0)
v = self.bus.address.value
v.binstr = "x" * len(self.bus.address)
self.bus.address.setimmediatevalue(v)
def __init__(self, entity, filename):
self.filename = filename
logging.info('Loading file...' + filename)
BusDriver.__init__(self, entity, "", entity.CLK_BX)
self.hit = BinaryValue(bits=len(self.bus.HIT))
self.bus.TRIG_EXT <= 0
def __init__(self, entity, name, clock, buffer_size = BUFFER_SIZE, debug = False):
BusDriver.__init__(self, entity, name, clock)
if debug:
self.log.setLevel(logging.DEBUG)
self.buffer_size = buffer_size
self.bus.data.binstr = 'ZZZZZZZZ'
self.bus.txe_n <= 1
self.bus.rde_n <= 1
self.data = Array('B')
def __init__(self, entity, name, clock, mempath, memhigh=0x40000000, data_bytes=8, autoflush=True, blatency=5):
"""
@param entity Device under test
@param name port names prefix (DUT has I/O ports <name>_<signal>
@clock clock that drives this interface
@param mempath operation system path of the memory image (1GB now - 0..0x3fffffff)
@param memhigh memory high address
@param data_bytes data width, in bytes
@param autoflush flush file after each write
@param blatency number of cycles to delay write response (b) channel
"""
BusDriver.__init__(self, entity, name, clock)
self.name = name
self.log.debug ("SAXIWrSim: name='%s', mempath='%s', memhigh=0x%08x, data_bytes=%d, autoflush=%s, blatency=%d"%
(name,mempath,memhigh,data_bytes, str(autoflush), blatency))
# self.log.debug ("SAXIWrSim.__init__(): super done")
#Open file to use as system memory
try:
self._memfile=open(mempath, 'r+') #keep old file if it exists already
except:
self._memfile=open(mempath, 'w+') #create a new file if it does not exist
self.log.info ("SAXIWrSim(%s): created a new 'memory' file %s"%(name,mempath)) #
#Extend to full size
self._memfile.seek(memhigh-1)
readOK=False
try:
readOK = len(self._memfile.read(1))>0
self.log.debug ("Read from 0x%08x"%(memhigh-1)) #
except:
pass
if not readOK:
self._memfile.seek(memhigh-1)
self._memfile.write(chr(0))
self._memfile.flush()
self.log.info("Wrote to 0x%08x to extend file to full size"%(memhigh-1)) #
self.autoflush=autoflush
self.bus.wr_ready.setimmediatevalue(1) # always ready
self.bus.bresp_latency.setimmediatevalue(blatency)
if data_bytes > 4:
self._data_bytes = 8
self._address_lsb = 3
self._fmt= "<Q"
elif data_bytes > 2:
self._data_bytes = 4
self._address_lsb = 2
self._fmt= "<L"
elif data_bytes > 1:
self._data_bytes = 2
self._address_lsb = 1
self._fmt= "<H"
else:
self._data_bytes = 1
self._address_lsb = 0
self._fmt= "<B"
self.log.debug ("SAXIWrSim(%s) init done"%(self.name))
def __init__(self, entity, name, clock, **kwargs):
# config = kwargs.pop('config', {})
BusDriver.__init__(self, entity, name, clock, **kwargs)
self.bus.tvalid <= 0
self.bus.tdata <= 0
self._keep = False
if hasattr(self.bus, "keep"):
self.bus.tkeep <= 0
self._keep = True
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
BusMonitor.__init__(self, entity, name, clock)
self.clock = clock
self.bus.PWRITE.setimmediatevalue(0)
self.bus.PSELx.setimmediatevalue(0)
self.bus.PENABLE.setimmediatevalue(0)
self.bus.PADDR.setimmediatevalue(0)
self.bus.PWDATA.setimmediatevalue(0)
def __init__(self, entity, name, clock, mempath, memhigh=0x40000000, data_bytes=8):
"""
@param entity Device under test
@param name port names prefix (DUT has I/O ports <name>_<signal>
@clock clock that drives this interface
@param mempath operation system path of the memory image (1GB now - 0..0x3fffffff)
@param memhigh memory high address
@param data_bytes data width, in bytes
"""
BusDriver.__init__(self, entity, name, clock)
self.name = name
self.log.debug ("SAXIRdSim: name='%s', mempath='%s', memhigh=0x%08x, data_bytes=%d"%
(name,mempath,memhigh,data_bytes))
# self._memfile=open(mempath, 'r+')
#Open file to use as system memory
try:
self._memfile=open(mempath, 'r+') #keep old file if it exists already
except:
self._memfile=open(mempath, 'w+') #create a new file if it does not exist
self.log.info ("SAXIRdSim(%s): created a new 'memory' file %s"%(name,mempath)) #
#Extend to full size
self._memfile.seek(memhigh-1)
readOK=False
try:
readOK = len(self._memfile.read(1))>0
self.log.debug ("Read from 0x%08x"%(memhigh-1)) #
except:
pass
if not readOK:
self._memfile.seek(memhigh-1)
self._memfile.write(chr(0))
self._memfile.flush()
self.log.info("Wrote to 0x%08x to extend file to full size"%(memhigh-1)) #
self.bus.rd_valid.setimmediatevalue(0)
if data_bytes > 4:
self._data_bytes = 8
self._address_lsb = 3
self._fmt= "<Q"
elif data_bytes > 2:
self._data_bytes = 4
self._address_lsb = 2
self._fmt= "<L"
elif data_bytes > 1:
self._data_bytes = 2
self._address_lsb = 1
self._fmt= "<H"
else:
self._data_bytes = 1
self._address_lsb = 0
self._fmt= "<B"
self.log.debug("SAXIRdSim(%s) init done"%(self.name))
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
self.bus.rd_en.setimmediatevalue(0)
self.bus.wr_strb.setimmediatevalue(0)
# Mutex for each channel that we master to prevent contention
self.write_busy = Lock("%s_wbusy" % name)
self.read_busy = Lock("%s_rbusy" % name)
def __init__(self, entity, name, clock, width=32, signals_dict=None,
**kwargs):
if signals_dict is not None:
self._signals=signals_dict
BusDriver.__init__(self, entity, name, clock, **kwargs)
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
self._width = width
self.bus.dain.setimmediatevalue(0)
self.bus.lba.setimmediatevalue(1)
self.bus.rw.setimmediatevalue(0)
self.bus.cs.setimmediatevalue(1)
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self.bus.EN.setimmediatevalue(0)
self.bus.ADR.setimmediatevalue(0)
self.bus.WR_RD.setimmediatevalue(0)
self.bus.BYTE_EN.setimmediatevalue(0)
self.bus.WR_DATA.setimmediatevalue(0)
# Mutex for each channel that we master to prevent contention
self.rd_busy = Lock("%s_wbusy" % name)
self.wr_busy = Lock("%s_rbusy" % name)
def __init__(self, entity, name, clock, callback=None, **kwargs):
# config = kwargs.pop('config', {})
BusDriver.__init__(self, entity, name, clock, **kwargs)
self.bus.tvalid <= 0
self.bus.tdata <= 0
self.width = len(self.bus.tdata)
self._keep = False
self._callback = callback
if hasattr(self.bus, "tkeep"):
self.bus.tkeep <= 0
self._keep = True
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
word = BinaryValue(bits=32)
single = BinaryValue(bits=1)
word.binstr = ("x" * 32)
single.binstr = ("x")
self.bus.load_i <= single
self.bus.rst_i <= single
self.bus.dat_i <= word
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
self.bus.cyc.setimmediatevalue(0)
self.bus.stb.setimmediatevalue(0)
self.bus.we.setimmediatevalue(0)
self.bus.adr.setimmediatevalue(0)
self.bus.datwr.setimmediatevalue(0)
v = self.bus.sel.value
v.binstr = "1" * len(self.bus.sel)
self.bus.sel <= v
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self.bus.cmd_coco_dir.setimmediatevalue(0)
self.bus.data_coco_dir.setimmediatevalue(0x00)
self.bus.data_coco_out.setimmediatevalue(0xff)
self.bus.cmd_coco_out.setimmediatevalue(1)
self.bus_width = 1
# Locks implemented with cocotb Events, normal threading.Lock guys don't work
self.cmd_bus_busy_event = Event("cmd_bus_busy")
self.cmd_bus_busy = False
self.data_write_aborted = False
self.data_read_aborted = False
def __init__(self, entity):
BusDriver.__init__(self, entity, "", entity.FCLK_IN)
# Create an appropriately sized high-impedence value
self._high_impedence = BinaryValue(bits=len(self.bus.BUS_DATA))
self._high_impedence.binstr = "Z" * len(self.bus.BUS_DATA)
# Create an appropriately sized high-impedence value
self._x = BinaryValue(bits=16)
self._x.binstr = "x" * 16
# Kick off a clock generator
cocotb.fork(Clock(self.clock, 20800).start())
def __init__(self, entity, name, clock, ready_max_delay=0, **kwargs):
BusDriver.__init__(self, entity, name, clock, **kwargs)
self.log.info("Driver start initialization: %s", name)
self.bus.ready.setimmediatevalue(1)
self.delay_max = ready_max_delay
self.wait = False
cocotb.fork(self._random_ready())
def __init__(self, entity):
BusDriver.__init__(self, entity, "", entity.FCLK_IN)
# Create an appropriately sized high-impedence value
self._high_impedence = BinaryValue(bits=len(self.bus.BUS_DATA))
self._high_impedence.binstr = "Z" * len(self.bus.BUS_DATA)
# Create an appropriately sized high-impedence value
self._x = BinaryValue(bits=16)
self._x.binstr = "x" * 16
# Kick off a clock generator
cocotb.fork(Clock(self.clock, 20833).start())
def __init__(self, entity, name, clock, width=32):
BusDriver.__init__(self, entity, name, clock)
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
self._width = width
self.bus.cyc.setimmediatevalue(0)
self.bus.stb.setimmediatevalue(0)
self.bus.we.setimmediatevalue(0)
self.bus.adr.setimmediatevalue(0)
self.bus.datwr.setimmediatevalue(0)
v = self.bus.sel.value
v.binstr = "1" * len(self.bus.sel)
self.bus.sel <= v
def __init__(self, entity, name, clock, width=32):
BusDriver.__init__(self, entity, name, clock)
#Drive default values onto bus
self.width = width
self.strobe_width = width / 8
self.bus.TVALID.setimmediatevalue(0)
self.bus.TLAST.setimmediatevalue(0)
self.bus.TDATA.setimmediatevalue(0)
self.bus.TKEEP.setimmediatevalue(0)
self.bus.TID.setimmediatevalue(0)
self.bus.TDEST.setimmediatevalue(0)
self.bus.TUSER.setimmediatevalue(0)
self.write_data_busy = Lock("%s_wbusy" % name)
def __init__(self, entity, name, clock, gen):
''' The clock shall be serial '''
BusDriver.__init__(self, entity, name, clock)
# outcoming elecidle flag
self.txelecidle = 1
# queue of *parallel* values to send
self.sq = []
# stream trace of received parallel values
self.rq = []
# sata generation (~ clock frequency)
self.gen = gen
self.driveBit(0)
def __init__(self, entity, name, clock, width = 100, height = 100, y_fp = 10, y_bp = 10, x_fp = 10, x_bp = 10):
BusDriver.__init__(self, entity, name, clock)
self.width = width
self.height = height
self.y_fp = y_fp
self.y_bp = y_bp
self.x_fp = x_fp
self.x_bp = x_bp
self.bus.SOF_STB.setimmediatevalue(0)
self.bus.HSYNC.setimmediatevalue(0)
self.bus.RED.setimmediatevalue(0)
self.bus.BLUE.setimmediatevalue(0)
self.bus.GREEN.setimmediatevalue(0)
self.busy = Lock("%s_busy" % name)
def __init__(self,
entity,
name,
clock):
BusDriver.__init__(self, entity, name, clock)
self.bus.EN.setimmediatevalue(0)
self.bus.ADR.setimmediatevalue(0)
self.bus.WR_RD.setimmediatevalue(0)
self.bus.BYTE_EN.setimmediatevalue(0)
self.bus.WR_DATA.setimmediatevalue(0)
# Mutex for each channel that we master to prevent contention
self.rd_busy = Lock("%s_wbusy" % name)
self.wr_busy = Lock("%s_rbusy" % name)
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
self.bus.AWVALID.setimmediatevalue(0)
self.bus.WVALID.setimmediatevalue(0)
self.bus.ARVALID.setimmediatevalue(0)
self.bus.BREADY.setimmediatevalue(1)
self.bus.RREADY.setimmediatevalue(1)
# Mutex for each channel that we master to prevent contention
self.write_address_busy = Lock("%s_wabusy" % name)
self.read_address_busy = Lock("%s_rabusy" % name)
self.write_data_busy = Lock("%s_wbusy" % name)
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
self.bus.AWVALID.setimmediatevalue(0)
self.bus.WVALID.setimmediatevalue(0)
self.bus.ARVALID.setimmediatevalue(0)
self.bus.BREADY.setimmediatevalue(1)
self.bus.RREADY.setimmediatevalue(1)
# Mutex for each channel that we master to prevent contention
self.write_address_busy = Lock("%s_wabusy" % name)
self.read_address_busy = Lock("%s_rabusy" % name)
self.write_data_busy = Lock("%s_wbusy" % name)
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self._can_read = False
self._can_write = False
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
if hasattr(self.bus, "read"):
self.bus.read.setimmediatevalue(0)
self._can_read = True
if hasattr(self.bus, "write"):
self.bus.write.setimmediatevalue(0)
self._can_write = True
self.bus.address.setimmediatevalue(0)
def __init__(self, entity):
BusDriver.__init__(self, entity, "", entity.BUS_CLK)
# Create an appropriately sized high-impedence value
self._high_impedence = BinaryValue(bits=len(self.bus.BUS_DATA))
self._high_impedence.binstr = "Z" * len(self.bus.BUS_DATA)
# Create an appropriately sized high-impedence value
self._x = BinaryValue(bits=len(self.bus.BUS_ADD))
self._x.binstr = "x" * len(self.bus.BUS_ADD)
self._has_byte_acces = False
# Kick off a clock generator
cocotb.fork(Clock(self.clock, 5000).start())
def __init__(self, entity, name, clk):
BusDriver.__init__(self, entity, name, clk)
# initial interface states
self.bus.al_cmd_in.setimmediatevalue(0)
self.bus.al_cmd_val_in.setimmediatevalue(0)
self.bus.al_cmd_out.setimmediatevalue(0)
self.bus.al_sh_data_in.setimmediatevalue(0)
self.bus.al_sh_data_val_in.setimmediatevalue(0)
self.bus.al_sh_data_strobe_in.setimmediatevalue(0)
self.bus.al_sh_feature_in.setimmediatevalue(0)
self.bus.al_sh_feature_val_in.setimmediatevalue(0)
self.bus.al_sh_lba_lo_in.setimmediatevalue(0)
self.bus.al_sh_lba_lo_val_in.setimmediatevalue(0)
self.bus.al_sh_lba_hi_in.setimmediatevalue(0)
self.bus.al_sh_lba_hi_val_in.setimmediatevalue(0)
self.bus.al_sh_count_in.setimmediatevalue(0)
self.bus.al_sh_count_val_in.setimmediatevalue(0)
self.bus.al_sh_command_in.setimmediatevalue(0)
self.bus.al_sh_command_val_in.setimmediatevalue(0)
self.bus.al_sh_dev_in.setimmediatevalue(0)
self.bus.al_sh_dev_val_in.setimmediatevalue(0)
self.bus.al_sh_control_in.setimmediatevalue(0)
self.bus.al_sh_control_val_in.setimmediatevalue(0)
self.bus.al_sh_dma_id_lo_in.setimmediatevalue(0)
self.bus.al_sh_dma_id_lo_val_in.setimmediatevalue(0)
self.bus.al_sh_dma_id_hi_in.setimmediatevalue(0)
self.bus.al_sh_dma_id_hi_val_in.setimmediatevalue(0)
self.bus.al_sh_buf_off_in.setimmediatevalue(0)
self.bus.al_sh_buf_off_val_in.setimmediatevalue(0)
self.bus.al_sh_tran_cnt_in.setimmediatevalue(0)
self.bus.al_sh_tran_cnt_val_in.setimmediatevalue(0)
self.bus.al_sh_autoact_in.setimmediatevalue(0)
self.bus.al_sh_autoact_val_in.setimmediatevalue(0)
self.bus.al_sh_inter_in.setimmediatevalue(0)
self.bus.al_sh_inter_val_in.setimmediatevalue(0)
self.bus.al_sh_dir_in.setimmediatevalue(0)
self.bus.al_sh_dir_val_in.setimmediatevalue(0)
self.bus.al_sh_dma_cnt_in.setimmediatevalue(0)
self.bus.al_sh_dma_cnt_val_in.setimmediatevalue(0)
self.bus.al_sh_notif_in.setimmediatevalue(0)
self.bus.al_sh_notif_val_in.setimmediatevalue(0)
self.bus.al_sh_port_in.setimmediatevalue(0)
self.bus.al_sh_port_val_in.setimmediatevalue(0)
def __init__(self, entity, name, clock, width, height, hblank, vblank):
BusDriver.__init__(self, entity, name, clock)
#Drive some sensible defaults
self.bus.RGB.setimmediatevalue(0)
self.bus.HSYNC.setimmediatevalue(0)
self.bus.VSYNC.setimmediatevalue(0)
self.bus.DATA_EN.setimmediatevalue(0)
self.bus.HBLANK.setimmediatevalue(1)
self.bus.VBLANK.setimmediatevalue(1)
self.width = width
self.height = height
self.hblank = hblank
self.vblank = vblank
self.write_lock = Lock("%s_busy" % name)
def __init__(self, entity, name, clock, memory, callback=None, event=None, big_endian=False):
BusDriver.__init__(self,entity,name,clock)
self.clock = clock
self.big_endain = big_endian
self.bus.ARREADY.setimmediatevalue(1)
self.bus.RVALID.setimmediatevalue(0)
self.bus.RLAST.setimmediatevalue(0)
self.bus.AWREADY.setimmediatevalue(1)
self._memory = memory
self.write_address_busy = Lock("%s_wabusy" % name)
self.read_address_busy = Lock("%s_rabusy" % name)
self.write_data_busy = Lock("%s_wbusy" % name)
cocotb.fork(self._read_data())
cocotb.fork(self._write_data())
def __init__(self, entity, name, clock, **kwargs):
BusDriver.__init__(self, entity, name, clock)
# Drive some sensible defaults (setimmediatevalue to avoid x asserts)
self.bus.AWVALID.setimmediatevalue(0)
self.bus.WVALID.setimmediatevalue(0)
self.bus.ARVALID.setimmediatevalue(0)
self.bus.BREADY.setimmediatevalue(1)
self.bus.RREADY.setimmediatevalue(1)
# Mutex for each channel that we master to prevent contention
self.write_address_busy = Lock("%s_wabusy" % name)
self.read_address_busy = Lock("%s_rabusy" % name)
self.write_data_busy = Lock("%s_wbusy" % name)
config = kwargs.pop('config', {})
self.config = AXI4LiteMaster._default_config.copy()
for configoption, value in config.items():
self.config[configoption] = value
self.log.debug("Setting config option %s to %s" %
(configoption, str(value)))
def __init__(self, entity, file_name):
BusDriver.__init__(self, entity, "", entity.ADC_CLK)
print file_name
self.data = np.load(file_name)
def __init__(self, entity):
BusDriver.__init__(self, entity, "", entity.CLK_BX)
self.hit = BinaryValue(bits=len(self.bus.HIT))
self.hit <= 0
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self.bus.select.setimmediatevalue(0)
self.log.debug("OPBMaster created")
self.busy_event = Event("%s_busy" % name)
self.busy = False
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self.bus.ACT.setimmediatevalue(0)
self.bus.STB.setimmediatevalue(0)
self.busy = Lock("%s_busy" % name)
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self.bus.wr_stb <= 0
self.bus.wr_data <= 0
self.write_data_busy = Lock("%s_wbusy" % name)
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self.read_data_busy = Lock("%s_wbusy" % name)
self.data = Array('B')
def __init__(self, dut): BusDriver.__init__(self, dut, None, dut.Clock)
def __init__(self, entity, name, clock, width = 32):
BusDriver.__init__(self, entity, name, clock)
self.width = width
self.bus.TREADY <= 0;
self.read_data_busy = Lock("%s_wbusy" % name)
self.data = []
