def expect_setup(self, epaddr, expected_data):
actual_data = []
# wait for data to appear
for i in range(128):
self.dut._log.debug("Prime loop {}".format(i))
status = yield self.read(self.csrs['usb_setup_status'])
have = status & 0x10
if have:
break
yield RisingEdge(self.dut.clk12)
for i in range(48):
self.dut._log.debug("Read loop {}".format(i))
status = yield self.read(self.csrs['usb_setup_status'])
have = status & 0x10
if not have:
break
v = yield self.read(self.csrs['usb_setup_data'])
actual_data.append(v)
yield RisingEdge(self.dut.clk12)
if len(actual_data) < 2:
raise TestFailure("data was short (got {}, expected {})".format(
expected_data, actual_data))
actual_data, actual_crc16 = actual_data[:-2], actual_data[-2:]
self.print_ep(epaddr, "Got: %r (expected: %r)", actual_data,
expected_data)
assertEqual(expected_data, actual_data, "SETUP packet not received")
assertEqual(crc16(expected_data), actual_crc16, "CRC16 not valid")
# Acknowledge that we've handled the setup packet
yield self.write(self.csrs['usb_setup_ctrl'], 2)
def _host_send_packet(self, packet):
"""Send a USB packet."""
# Packet gets multiplied by 4x so we can send using the
# usb48 clock instead of the usb12 clock.
packet = 'JJJJJJJJ' + wrap_packet(packet)
assertEqual('J', packet[-1], "Packet didn't end in J: " + packet)
for v in packet:
if v == '0' or v == '_':
# SE0 - both lines pulled low
self.dut.usb_d_p <= 0
self.dut.usb_d_n <= 0
elif v == '1':
# SE1 - illegal, should never occur
self.dut.usb_d_p <= 1
self.dut.usb_d_n <= 1
elif v == '-' or v == 'I':
# Idle
self.dut.usb_d_p <= 1
self.dut.usb_d_n <= 0
elif v == 'J':
self.dut.usb_d_p <= 1
self.dut.usb_d_n <= 0
elif v == 'K':
self.dut.usb_d_p <= 0
self.dut.usb_d_n <= 1
else:
raise TestFailure("Unknown value: %s" % v)
yield RisingEdge(self.dut.clk48_host)
def expect_data(self, epaddr, expected_data, expected):
actual_data = []
# wait for data to appear
for i in range(128):
self.dut._log.debug("Prime loop {}".format(i))
status = yield self.read(self.csrs['usb_out_status'])
have = status & (1 << 4)
if have:
break
yield RisingEdge(self.dut.clk12)
for i in range(256):
self.dut._log.debug("Read loop {}".format(i))
status = yield self.read(self.csrs['usb_out_status'])
have = status & (1 << 4)
if not have:
break
v = yield self.read(self.csrs['usb_out_data'])
actual_data.append(v)
yield RisingEdge(self.dut.clk12)
if expected == PID.ACK:
if len(actual_data) < 2:
raise TestFailure("data {} was short".format(actual_data))
actual_data, actual_crc16 = actual_data[:-2], actual_data[-2:]
self.print_ep(epaddr, "Got: %r (expected: %r)", actual_data,
expected_data)
assertEqual(expected_data, actual_data,
"DATA packet not correctly received")
assertEqual(crc16(expected_data), actual_crc16, "CRC16 not valid")
pending = yield self.read(self.csrs['usb_out_ev_pending'])
if pending != 1:
raise TestFailure('event not generated')
yield self.write(self.csrs['usb_out_ev_pending'], pending)
def host_expect_packet(self, packet, msg=None):
self.monitor.prime()
result = yield self.monitor.wait_for_recv(1e9) # 1 ms max
if result is None:
current = get_sim_time("us")
raise TestFailure(f"No full packet received @{current}")
yield RisingEdge(self.dut.clk48_host)
self.dut.usb_d_p = 1
self.dut.usb_d_n = 0
# Check the packet received matches
expected = pp_packet(wrap_packet(packet))
actual = pp_packet(result)
nak = pp_packet(wrap_packet(handshake_packet(PID.NAK)))
if (actual == nak) and (expected != nak):
self.dut._log.warning("Got NAK, retry")
yield Timer(self.RETRY_INTERVAL, 'us')
return
else:
self.retry = False
assertEqual(expected, actual, msg)
