Python define_stream示例

示例#1

from cocotbext.axi import AxiReadBus, AxiRamRead
from cocotbext.axi.stream import define_stream

try:
    from dma_psdp_ram import PsdpRamWrite, PsdpRamWriteBus
except ImportError:
    # attempt import from current directory
    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
    try:
        from dma_psdp_ram import PsdpRamWrite, PsdpRamWriteBus
    finally:
        del sys.path[0]

DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream(
    "Desc",
    signals=[
        "axi_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"
    ],
    optional_signals=["imm", "imm_en"])

DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream(
    "DescStatus", signals=["tag", "error", "valid"])


class TB(object):
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())

示例#2

import logging
import os

import cocotb_test.simulator
import pytest

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory

from cocotbext.axi import AxiBus, AxiRam
from cocotbext.axi.stream import define_stream

DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream(
    "Desc",
    signals=["read_addr", "write_addr", "len", "tag", "valid", "ready"])

DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream(
    "DescStatus", signals=["tag", "error", "valid"])


class TB(object):
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        cocotb.fork(Clock(dut.clk, 10, units="ns").start())

示例#3

文件： test_dma_if_pcie_us_rd.py 项目： kkilictepe/verilog-pcie

from cocotbext.axi.stream import define_stream
from cocotbext.axi.utils import hexdump_str

try:
    from dma_psdp_ram import PsdpRamWrite
except ImportError:
    # attempt import from current directory
    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
    try:
        from dma_psdp_ram import PsdpRamWrite
    finally:
        del sys.path[0]

DescTransaction, DescSource, DescSink, DescMonitor = define_stream(
    "Desc",
    signals=[
        "pcie_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"
    ])

DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream(
    "DescStatus", signals=["tag", "valid"])


class TB(object):
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        # PCIe

示例#4

from scapy.utils import mac2str

import pytest
import cocotb_test.simulator

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory

from cocotbext.axi import AxiStreamBus, AxiStreamSource
from cocotbext.axi.stream import define_stream


EthHdrBus, EthHdrTransaction, EthHdrSource, EthHdrSink, EthHdrMonitor = define_stream("EthHdr",
    signals=["hdr_valid", "hdr_ready", "dest_mac", "src_mac", "type"]
)

ArpHdrBus, ArpHdrTransaction, ArpHdrSource, ArpHdrSink, ArpHdrMonitor = define_stream("ArpHdr",
    signals=["frame_valid", "frame_ready", "eth_dest_mac", "eth_src_mac", "eth_type",
    "arp_htype", "arp_ptype", "arp_hlen", "arp_plen", "arp_oper", "arp_sha", "arp_spa", "arp_tha", "arp_tpa"]
)


class TB:
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

示例#5

import random

import cocotb_test.simulator
import pytest

import cocotb
from cocotb.clock import Clock
from cocotb.queue import Queue
from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory

from cocotbext.axi import AxiLiteBus, AxiLiteMaster
from cocotbext.axi.stream import define_stream

AxiStreamBus, AxiStreamTransaction, AxiStreamSource, AxiStreamSink, AxiStreamMonitor = define_stream(
    "AxiStream",
    signals=["tvalid", "tdata"],
    optional_signals=["tready", "tkeep", "tlast", "tid", "tdest", "tuser"])


class TB(object):
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())

        self.stat_source = AxiStreamSource(
            AxiStreamBus.from_prefix(dut, "s_axis_stat"), dut.clk, dut.rst)

示例#6

文件： test_arp.py 项目： yonggeshidai/verilog-ethernet

from scapy.layers.l2 import Ether, ARP
from scapy.utils import mac2str, atol

import pytest
import cocotb_test.simulator

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory

from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
from cocotbext.axi.stream import define_stream

EthHdrBus, EthHdrTransaction, EthHdrSource, EthHdrSink, EthHdrMonitor = define_stream(
    "EthHdr",
    signals=["hdr_valid", "hdr_ready", "dest_mac", "src_mac", "type"])

ArpReqBus, ArpReqTransaction, ArpReqSource, ArpReqSink, ArpReqMonitor = define_stream(
    "ArpReq", signals=["valid", "ready", "ip"])

ArpRespBus, ArpRespTransaction, ArpRespSource, ArpRespSink, ArpRespMonitor = define_stream(
    "ArpResp", signals=["valid", "ready", "error", "mac"])


class TB:
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

示例#7

文件： test_axis_baser_tx_64.py 项目： nightseas/verilog-ethernet

from cocotbext.axi import AxiStreamBus, AxiStreamSource
from cocotbext.axi.stream import define_stream

try:
    from baser import BaseRSerdesSink
except ImportError:
    # attempt import from current directory
    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
    try:
        from baser import BaseRSerdesSink
    finally:
        del sys.path[0]


PtpTsBus, PtpTsTransaction, PtpTsSource, PtpTsSink, PtpTsMonitor = define_stream("PtpTs",
    signals=["ts", "ts_valid"],
    optional_signals=["ts_tag", "ts_ready"]
)


class TB:
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())

        self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst)
        self.sink = BaseRSerdesSink(dut.encoded_tx_data, dut.encoded_tx_hdr, dut.clk, scramble=False)

示例#8

文件： test_tx_checksum.py 项目： zzulb/corundum

from scapy.layers.l2 import Ether
from scapy.layers.inet import IP, UDP

import cocotb_test.simulator
import pytest

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory

from cocotbext.axi import AxiStreamFrame, AxiStreamSource, AxiStreamSink
from cocotbext.axi.stream import define_stream

CsumCmdTransaction, CsumCmdSource, CsumCmdSink, CsumCmdMonitor = define_stream(
    "CsumCmd",
    signals=["csum_enable", "csum_start", "csum_offset", "csum_init", "valid"],
    optional_signals=["ready"])


class TB(object):
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        cocotb.fork(Clock(dut.clk, 4, units="ns").start())

        self.source = AxiStreamSource(dut, "s_axis", dut.clk, dut.rst)
        self.sink = AxiStreamSink(dut, "m_axis", dut.clk, dut.rst)

示例#9

import scapy.utils
from scapy.layers.l2 import Ether
from scapy.layers.inet import IP, UDP, TCP

import cocotb_test.simulator
import pytest

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory

from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource
from cocotbext.axi.stream import define_stream

CsumBus, CsumTransaction, CsumSource, CsumSink, CsumMonitor = define_stream(
    "Csum", signals=["csum", "csum_valid"])


class TB(object):
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())

        self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"),
                                      dut.clk, dut.rst)
        self.sink = CsumSink(CsumBus.from_prefix(dut, "m_axis"), dut.clk,
                             dut.rst)

示例#10

文件： test_axi_dma_wr.py 项目： linjw16/corundum

import os

import cocotb_test.simulator
import pytest

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory

from cocotbext.axi import AxiWriteBus, AxiRamWrite
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource
from cocotbext.axi.stream import define_stream

DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc",
    signals=["addr", "len", "tag", "valid", "ready"],
    optional_signals=["id", "dest", "user"]
)

DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus",
    signals=["tag", "error", "valid"],
    optional_signals=["len", "id", "dest", "user"]
)


class TB(object):
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

示例#11

文件： test_pcie_msix.py 项目： nightseas/verilog-pcie

from cocotb.regression import TestFactory

from cocotbext.axi import AxiLiteBus, AxiLiteMaster
from cocotbext.axi.stream import define_stream

try:
    from pcie_if import PcieIfSink, PcieIfTxBus
except ImportError:
    # attempt import from current directory
    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
    try:
        from pcie_if import PcieIfSink, PcieIfTxBus
    finally:
        del sys.path[0]

IrqBus, IrqTransaction, IrqSource, IrqSink, IrqMonitor = define_stream(
    "Irq", signals=["index", "valid", "ready"])


@contextmanager
def assert_raises(exc_type, pattern=None):
    try:
        yield
    except exc_type as e:
        if pattern:
            assert re.match(pattern, str(e)), \
                "Correct exception type caught, but message did not match pattern"
        pass
    else:
        raise AssertionError("{} was not raised".format(exc_type.__name__))

示例#12

from scapy.layers.l2 import Ether
from scapy.layers.inet import IP, UDP, TCP

import cocotb_test.simulator
import pytest

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory

from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource
from cocotbext.axi.stream import define_stream

HashBus, HashTransaction, HashSource, HashSink, HashMonitor = define_stream(
    "Hash", signals=["hash", "hash_type", "hash_valid"])


class HashType(enum.IntFlag):
    IPV4 = 1
    IPV6 = 2
    TCP = 4
    UDP = 8


def hash_toep(data, key):
    k = len(key) * 8 - 32
    key = int.from_bytes(key, 'big')

    h = 0

示例#13

文件： test_cpl_queue_manager.py 项目： likewise/corundum

import logging
import os
import random

import cocotb_test.simulator

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory

from cocotbext.axi import AxiLiteBus, AxiLiteMaster
from cocotbext.axi.stream import define_stream

EnqueueReqBus, EnqueueReqTransaction, EnqueueReqSource, EnqueueReqSink, EnqueueReqMonitor = define_stream(
    "EnqueueReq",
    signals=["queue", "tag", "valid"],
    optional_signals=["ready"])

EnqueueRespBus, EnqueueRespTransaction, EnqueueRespSource, EnqueueRespSink, EnqueueRespMonitor = define_stream(
    "EnqueueResp",
    signals=[
        "queue", "ptr", "addr", "event", "tag", "op_tag", "full", "error",
        "valid"
    ],
    optional_signals=["ready"])

EnqueueCommitBus, EnqueueCommitTransaction, EnqueueCommitSource, EnqueueCommitSink, EnqueueCommitMonitor = define_stream(
    "EnqueueCommit", signals=["op_tag", "valid"], optional_signals=["ready"])

EventBus, EventTransaction, EventSource, EventSink, EventMonitor = define_stream(
    "Event",

示例#14

文件： test_queue_manager.py 项目： mfkiwl/corundum-fpga-100g-Ethernet

import logging
import os
import random

import cocotb_test.simulator

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory

from cocotbext.axi import AxiLiteBus, AxiLiteMaster
from cocotbext.axi.stream import define_stream

DequeueReqBus, DequeueReqTransaction, DequeueReqSource, DequeueReqSink, DequeueReqMonitor = define_stream(
    "DequeueReq",
    signals=["queue", "tag", "valid"],
    optional_signals=["ready"])

DequeueRespBus, DequeueRespTransaction, DequeueRespSource, DequeueRespSink, DequeueRespMonitor = define_stream(
    "DequeueResp",
    signals=[
        "queue", "ptr", "addr", "block_size", "cpl", "tag", "op_tag", "empty",
        "error", "valid"
    ],
    optional_signals=["ready"])

DequeueCommitBus, DequeueCommitTransaction, DequeueCommitSource, DequeueCommitSink, DequeueCommitMonitor = define_stream(
    "DequeueCommit", signals=["op_tag", "valid"], optional_signals=["ready"])

DoorbellBus, DoorbellTransaction, DoorbellSource, DoorbellSink, DoorbellMonitor = define_stream(
    "Doorbell", signals=["queue", "valid"], optional_signals=["ready"])

示例#15

文件： test_axis_frame_length_adjust.py 项目： Bucknalla/verilog-axis

import logging
import os

import cocotb_test.simulator
import pytest

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory

from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
from cocotbext.axi.stream import define_stream

StatusBus, StatusTransaction, StatusSource, StatusSink, StatusMonitor = define_stream("Status",
    signals=["frame_pad", "frame_truncate", "frame_length", "frame_original_length", "valid"],
    optional_signals=["ready"]
)


class TB(object):
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        cocotb.fork(Clock(dut.clk, 10, units="ns").start())

        self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst)
        self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst)

示例#16

文件： test_eth_axis_rx.py 项目： warikap/verilog-ethernet

from scapy.layers.l2 import Ether

import pytest
import cocotb_test.simulator

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory

from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
from cocotbext.axi.stream import define_stream


EthHdrBus, EthHdrTransaction, EthHdrSource, EthHdrSink, EthHdrMonitor = define_stream("EthHdr",
    signals=["hdr_valid", "hdr_ready", "dest_mac", "src_mac", "type"]
)


class TB:
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())

        self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst)

        self.header_sink = EthHdrSink(EthHdrBus.from_prefix(dut, "m_eth"), dut.clk, dut.rst)

示例#17

"""

import logging
import os

import cocotb_test.simulator

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory

from cocotbext.axi.stream import define_stream

CacheOpBus, CacheOpTransaction, CacheOpSource, CacheOpSink, CacheOpMonitor = define_stream(
    "CacheOp",
    signals=["valid", "ready"],
    optional_signals=["ip", "mac", "error"])


class TB:
    def __init__(self, dut):
        self.dut = dut

        self.log = logging.getLogger("cocotb.tb")
        self.log.setLevel(logging.DEBUG)

        cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())

        self.query_request_source = CacheOpSource(
            CacheOpBus.from_prefix(dut, "query_request"), dut.clk, dut.rst)
        self.query_response_sink = CacheOpSink(