def __init__(self, dut):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
# PCIe
self.rc = RootComplex()
self.dev = S10PcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=2,
# pld_clk_frequency=250e6,
l_tile=False,
pf_count=1,
max_payload_size=1024,
enable_extended_tag=True,
pf0_msi_enable=True,
pf0_msi_count=32,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_table_size=0,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00000000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00000000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals
# Clock and reset
# npor=dut.npor,
# pin_perst=dut.pin_perst,
# ninit_done=dut.ninit_done,
# pld_clk_inuse=dut.pld_clk_inuse,
# pld_core_ready=dut.pld_core_ready,
reset_status=dut.rst,
# clr_st=dut.clr_st,
# refclk=dut.refclk,
coreclkout_hip=dut.clk,
# RX interface
rx_bus=S10RxBus.from_prefix(dut, "rx_st"),
# TX interface
tx_bus=S10TxBus.from_prefix(dut, "tx_st"),
# TX flow control
tx_ph_cdts=dut.tx_ph_cdts,
tx_pd_cdts=dut.tx_pd_cdts,
tx_nph_cdts=dut.tx_nph_cdts,
tx_npd_cdts=dut.tx_npd_cdts,
tx_cplh_cdts=dut.tx_cplh_cdts,
tx_cpld_cdts=dut.tx_cpld_cdts,
tx_hdr_cdts_consumed=dut.tx_hdr_cdts_consumed,
tx_data_cdts_consumed=dut.tx_data_cdts_consumed,
tx_cdts_type=dut.tx_cdts_type,
tx_cdts_data_value=dut.tx_cdts_data_value,
# Hard IP status
# int_status=dut.int_status,
# int_status_common=dut.int_status_common,
# derr_cor_ext_rpl=dut.derr_cor_ext_rpl,
# derr_rpl=dut.derr_rpl,
# derr_cor_ext_rcv=dut.derr_cor_ext_rcv,
# derr_uncor_ext_rcv=dut.derr_uncor_ext_rcv,
# rx_par_err=dut.rx_par_err,
# tx_par_err=dut.tx_par_err,
# ltssmstate=dut.ltssmstate,
# link_up=dut.link_up,
# lane_act=dut.lane_act,
# currentspeed=dut.currentspeed,
# Power management
# pm_linkst_in_l1=dut.pm_linkst_in_l1,
# pm_linkst_in_l0s=dut.pm_linkst_in_l0s,
# pm_state=dut.pm_state,
# pm_dstate=dut.pm_dstate,
# apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
# apps_ready_entr_l23=dut.apps_ready_entr_l23,
# apps_pm_xmt_turnoff=dut.apps_pm_xmt_turnoff,
# app_init_rst=dut.app_init_rst,
# app_xfer_pending=dut.app_xfer_pending,
# Interrupt interface
app_msi_req=dut.app_msi_req,
app_msi_ack=dut.app_msi_ack,
app_msi_tc=dut.app_msi_tc,
app_msi_num=dut.app_msi_num,
app_msi_func_num=dut.app_msi_func_num,
# app_int_sts=dut.app_int_sts,
# Error interface
# serr_out=dut.serr_out,
# hip_enter_err_mode=dut.hip_enter_err_mode,
# app_err_valid=dut.app_err_valid,
# app_err_hdr=dut.app_err_hdr,
# app_err_info=dut.app_err_info,
# app_err_func_num=dut.app_err_func_num,
# Configuration output
tl_cfg_func=dut.tl_cfg_func,
tl_cfg_add=dut.tl_cfg_add,
tl_cfg_ctl=dut.tl_cfg_ctl,
# Configuration extension bus
# ceb_req=dut.ceb_req,
# ceb_ack=dut.ceb_ack,
# ceb_addr=dut.ceb_addr,
# ceb_din=dut.ceb_din,
# ceb_dout=dut.ceb_dout,
# ceb_wr=dut.ceb_wr,
# ceb_cdm_convert_data=dut.ceb_cdm_convert_data,
# ceb_func_num=dut.ceb_func_num,
# ceb_vf_num=dut.ceb_vf_num,
# ceb_vf_active=dut.ceb_vf_active,
# Hard IP reconfiguration interface
# hip_reconfig_clk=dut.hip_reconfig_clk,
# hip_reconfig_address=dut.hip_reconfig_address,
# hip_reconfig_read=dut.hip_reconfig_read,
# hip_reconfig_readdata=dut.hip_reconfig_readdata,
# hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
# hip_reconfig_write=dut.hip_reconfig_write,
# hip_reconfig_writedata=dut.hip_reconfig_writedata,
# hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
)
self.dev.log.setLevel(logging.DEBUG)
self.rc.make_port().connect(self.dev)
self.dev.functions[0].msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(
0, 2**len(dut.core_pcie_inst.axil_ctrl_awaddr))
self.dev.functions[0].configure_bar(
2, 2**len(dut.core_pcie_inst.axi_ram_awaddr))
def __init__(self, dut):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
# PCIe
self.rc = RootComplex()
self.rc.max_payload_size = 0x1 # 256 bytes
self.rc.max_read_request_size = 0x2 # 512 bytes
self.dev = S10PcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=2,
# pld_clk_frequency=250e6,
l_tile=False,
# signals
# Clock and reset
# npor=dut.npor,
# pin_perst=dut.pin_perst,
# ninit_done=dut.ninit_done,
# pld_clk_inuse=dut.pld_clk_inuse,
# pld_core_ready=dut.pld_core_ready,
reset_status=dut.rst,
# clr_st=dut.clr_st,
# refclk=dut.refclk,
coreclkout_hip=dut.clk,
# RX interface
rx_bus=S10RxBus.from_prefix(dut, "rx_st"),
# TX interface
tx_bus=S10TxBus.from_prefix(dut, "tx_st"),
# TX flow control
tx_ph_cdts=dut.tx_ph_cdts,
tx_pd_cdts=dut.tx_pd_cdts,
tx_nph_cdts=dut.tx_nph_cdts,
tx_npd_cdts=dut.tx_npd_cdts,
tx_cplh_cdts=dut.tx_cplh_cdts,
tx_cpld_cdts=dut.tx_cpld_cdts,
tx_hdr_cdts_consumed=dut.tx_hdr_cdts_consumed,
tx_data_cdts_consumed=dut.tx_data_cdts_consumed,
tx_cdts_type=dut.tx_cdts_type,
tx_cdts_data_value=dut.tx_cdts_data_value,
# Hard IP status
# int_status=dut.int_status,
# int_status_common=dut.int_status_common,
# derr_cor_ext_rpl=dut.derr_cor_ext_rpl,
# derr_rpl=dut.derr_rpl,
# derr_cor_ext_rcv=dut.derr_cor_ext_rcv,
# derr_uncor_ext_rcv=dut.derr_uncor_ext_rcv,
# rx_par_err=dut.rx_par_err,
# tx_par_err=dut.tx_par_err,
# ltssmstate=dut.ltssmstate,
# link_up=dut.link_up,
# lane_act=dut.lane_act,
# currentspeed=dut.currentspeed,
# Power management
# pm_linkst_in_l1=dut.pm_linkst_in_l1,
# pm_linkst_in_l0s=dut.pm_linkst_in_l0s,
# pm_state=dut.pm_state,
# pm_dstate=dut.pm_dstate,
# apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
# apps_ready_entr_l23=dut.apps_ready_entr_l23,
# apps_pm_xmt_turnoff=dut.apps_pm_xmt_turnoff,
# app_init_rst=dut.app_init_rst,
# app_xfer_pending=dut.app_xfer_pending,
# Interrupt interface
app_msi_req=dut.app_msi_req,
app_msi_ack=dut.app_msi_ack,
app_msi_tc=dut.app_msi_tc,
app_msi_num=dut.app_msi_num,
app_msi_func_num=dut.app_msi_func_num,
# app_int_sts=dut.app_int_sts,
# Error interface
# serr_out=dut.serr_out,
# hip_enter_err_mode=dut.hip_enter_err_mode,
# app_err_valid=dut.app_err_valid,
# app_err_hdr=dut.app_err_hdr,
# app_err_info=dut.app_err_info,
# app_err_func_num=dut.app_err_func_num,
# Configuration output
tl_cfg_func=dut.tl_cfg_func,
tl_cfg_add=dut.tl_cfg_add,
tl_cfg_ctl=dut.tl_cfg_ctl,
# Configuration extension bus
# ceb_req=dut.ceb_req,
# ceb_ack=dut.ceb_ack,
# ceb_addr=dut.ceb_addr,
# ceb_din=dut.ceb_din,
# ceb_dout=dut.ceb_dout,
# ceb_wr=dut.ceb_wr,
# ceb_cdm_convert_data=dut.ceb_cdm_convert_data,
# ceb_func_num=dut.ceb_func_num,
# ceb_vf_num=dut.ceb_vf_num,
# ceb_vf_active=dut.ceb_vf_active,
# Hard IP reconfiguration interface
# hip_reconfig_clk=dut.hip_reconfig_clk,
# hip_reconfig_address=dut.hip_reconfig_address,
# hip_reconfig_read=dut.hip_reconfig_read,
# hip_reconfig_readdata=dut.hip_reconfig_readdata,
# hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
# hip_reconfig_write=dut.hip_reconfig_write,
# hip_reconfig_writedata=dut.hip_reconfig_writedata,
# hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
)
# self.dev.log.setLevel(logging.DEBUG)
self.rc.make_port().connect(self.dev)
self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(
0,
2**len(dut.core_pcie_inst.axil_ctrl_araddr),
ext=True,
prefetch=True)
if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(
2,
2**len(dut.core_pcie_inst.axil_app_ctrl_araddr),
ext=True,
prefetch=True)
# Ethernet
self.port_mac = []
eth_int_if_width = len(dut.core_pcie_inst.core_inst.iface[0].port[0].
rx_async_fifo_inst.m_axis_tdata)
eth_clock_period = 6.4
eth_speed = 10e9
if eth_int_if_width == 64:
# 10G
eth_clock_period = 6.4
eth_speed = 10e9
elif eth_int_if_width == 128:
# 25G
eth_clock_period = 2.56
eth_speed = 25e9
elif eth_int_if_width == 512:
# 100G
eth_clock_period = 3.102
eth_speed = 100e9
for iface in dut.core_pcie_inst.core_inst.iface:
for port in iface.port:
cocotb.start_soon(
Clock(port.port_rx_clk, eth_clock_period,
units="ns").start())
cocotb.start_soon(
Clock(port.port_tx_clk, eth_clock_period,
units="ns").start())
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
mac = EthMac(tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
ifg=12,
speed=eth_speed)
self.port_mac.append(mac)
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
dut.ctrl_reg_rd_data.setimmediatevalue(0)
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
dut.ptp_sample_clk.setimmediatevalue(0)
dut.s_axis_stat_tdata.setimmediatevalue(0)
dut.s_axis_stat_tid.setimmediatevalue(0)
dut.s_axis_stat_tvalid.setimmediatevalue(0)
self.loopback_enable = False
cocotb.start_soon(self._run_loopback())
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
# PCIe
self.rc = RootComplex()
self.dev = S10PcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=2,
# pld_clk_frequency=250e6,
l_tile=False,
# signals
# Clock and reset
npor=dut.npor,
pin_perst=dut.pin_perst,
ninit_done=dut.ninit_done,
pld_clk_inuse=dut.pld_clk_inuse,
pld_core_ready=dut.pld_core_ready,
reset_status=dut.reset_status,
clr_st=dut.clr_st,
refclk=dut.refclk,
coreclkout_hip=dut.coreclkout_hip,
# RX interface
rx_bus=S10RxBus.from_prefix(dut, "rx_st"),
# TX interface
tx_bus=S10TxBus.from_prefix(dut, "tx_st"),
# TX flow control
tx_ph_cdts=dut.tx_ph_cdts,
tx_pd_cdts=dut.tx_pd_cdts,
tx_nph_cdts=dut.tx_nph_cdts,
tx_npd_cdts=dut.tx_npd_cdts,
tx_cplh_cdts=dut.tx_cplh_cdts,
tx_cpld_cdts=dut.tx_cpld_cdts,
tx_hdr_cdts_consumed=dut.tx_hdr_cdts_consumed,
tx_data_cdts_consumed=dut.tx_data_cdts_consumed,
tx_cdts_type=dut.tx_cdts_type,
tx_cdts_data_value=dut.tx_cdts_data_value,
# Hard IP status
int_status=dut.int_status,
int_status_common=dut.int_status_common,
derr_cor_ext_rpl=dut.derr_cor_ext_rpl,
derr_rpl=dut.derr_rpl,
derr_cor_ext_rcv=dut.derr_cor_ext_rcv,
derr_uncor_ext_rcv=dut.derr_uncor_ext_rcv,
rx_par_err=dut.rx_par_err,
tx_par_err=dut.tx_par_err,
ltssmstate=dut.ltssmstate,
link_up=dut.link_up,
lane_act=dut.lane_act,
currentspeed=dut.currentspeed,
# Power management
pm_linkst_in_l1=dut.pm_linkst_in_l1,
pm_linkst_in_l0s=dut.pm_linkst_in_l0s,
pm_state=dut.pm_state,
pm_dstate=dut.pm_dstate,
apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
apps_ready_entr_l23=dut.apps_ready_entr_l23,
apps_pm_xmt_turnoff=dut.apps_pm_xmt_turnoff,
app_init_rst=dut.app_init_rst,
app_xfer_pending=dut.app_xfer_pending,
# Interrupt interface
app_msi_req=dut.app_msi_req,
app_msi_ack=dut.app_msi_ack,
app_msi_tc=dut.app_msi_tc,
app_msi_num=dut.app_msi_num,
app_msi_func_num=dut.app_msi_func_num,
app_int_sts=dut.app_int_sts,
# Error interface
app_err_valid=dut.app_err_valid,
app_err_hdr=dut.app_err_hdr,
app_err_info=dut.app_err_info,
app_err_func_num=dut.app_err_func_num,
# Configuration output
tl_cfg_func=dut.tl_cfg_func,
tl_cfg_add=dut.tl_cfg_add,
tl_cfg_ctl=dut.tl_cfg_ctl,
# Configuration extension bus
ceb_req=dut.ceb_req,
ceb_ack=dut.ceb_ack,
ceb_addr=dut.ceb_addr,
ceb_din=dut.ceb_din,
ceb_dout=dut.ceb_dout,
ceb_wr=dut.ceb_wr,
ceb_cdm_convert_data=dut.ceb_cdm_convert_data,
ceb_func_num=dut.ceb_func_num,
ceb_vf_num=dut.ceb_vf_num,
ceb_vf_active=dut.ceb_vf_active,
# Hard IP reconfiguration interface
hip_reconfig_clk=dut.hip_reconfig_clk,
hip_reconfig_address=dut.hip_reconfig_address,
hip_reconfig_read=dut.hip_reconfig_read,
hip_reconfig_readdata=dut.hip_reconfig_readdata,
hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
hip_reconfig_write=dut.hip_reconfig_write,
hip_reconfig_writedata=dut.hip_reconfig_writedata,
hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
)
self.dev.log.setLevel(logging.DEBUG)
dut.npor.setimmediatevalue(1)
dut.pin_perst.setimmediatevalue(1)
dut.ninit_done.setimmediatevalue(0)
dut.pld_core_ready.setimmediatevalue(1)
dut.refclk.setimmediatevalue(0)
dut.apps_pm_xmt_pme.setimmediatevalue(0)
dut.apps_ready_entr_l23.setimmediatevalue(0)
dut.apps_pm_xmt_turnoff.setimmediatevalue(0)
dut.app_init_rst.setimmediatevalue(0)
dut.app_xfer_pending.setimmediatevalue(0)
dut.app_msi_req.setimmediatevalue(0)
dut.app_msi_tc.setimmediatevalue(0)
dut.app_msi_num.setimmediatevalue(0)
dut.app_msi_func_num.setimmediatevalue(0)
dut.app_int_sts.setimmediatevalue(0)
dut.app_err_valid.setimmediatevalue(0)
dut.app_err_hdr.setimmediatevalue(0)
dut.app_err_info.setimmediatevalue(0)
dut.app_err_func_num.setimmediatevalue(0)
dut.ceb_ack.setimmediatevalue(0)
dut.ceb_din.setimmediatevalue(0)
dut.ceb_cdm_convert_data.setimmediatevalue(0)
dut.hip_reconfig_clk.setimmediatevalue(0)
dut.hip_reconfig_rst_n.setimmediatevalue(1)
dut.hip_reconfig_address.setimmediatevalue(0)
dut.hip_reconfig_read.setimmediatevalue(0)
dut.hip_reconfig_write.setimmediatevalue(0)
dut.hip_reconfig_writedata.setimmediatevalue(0)
self.rc.make_port().connect(self.dev)
# user logic
self.tx_source = S10PcieSource(S10TxBus.from_prefix(dut, "tx_st"),
dut.coreclkout_hip)
self.tx_source.ready_latency = 3
self.rx_sink = S10PcieSink(S10RxBus.from_prefix(dut, "rx_st"),
dut.coreclkout_hip)
self.rx_sink.ready_latency = 18 if self.tx_source.width == 512 else 17
self.regions = [None] * 6
self.regions[0] = mmap.mmap(-1, 1024 * 1024)
self.regions[1] = mmap.mmap(-1, 1024 * 1024)
self.regions[3] = mmap.mmap(-1, 1024)
self.current_tag = 0
self.tag_count = 32
self.tag_active = [False] * 256
self.tag_release = Event()
self.rx_cpl_queues = [Queue() for k in range(256)]
self.rx_cpl_sync = [Event() for k in range(256)]
self.dev_bus_num = 0
self.dev_device_num = 0
self.dev_max_payload = 0
self.dev_max_read_req = 0
self.dev_msi_enable = 0
self.dev_msi_multi_msg_enable = 0
self.dev_msi_address = 0
self.dev_msi_data = 0
self.dev_msi_mask = 0
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, len(self.regions[0]))
self.dev.functions[0].configure_bar(1, len(self.regions[1]), True,
True)
self.dev.functions[0].configure_bar(3, len(self.regions[3]), False,
False, True)
cocotb.start_soon(self._run_rx_tlp())
cocotb.start_soon(self._run_cfg())
def __init__(self, dut):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
# PCIe
self.rc = RootComplex()
self.rc.max_payload_size = 0x1 # 256 bytes
self.rc.max_read_request_size = 0x2 # 512 bytes
self.dev = S10PcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=8,
# pld_clk_frequency=250e6,
l_tile=False,
# signals
# Clock and reset
# npor=dut.npor,
# pin_perst=dut.pin_perst,
# ninit_done=dut.ninit_done,
# pld_clk_inuse=dut.pld_clk_inuse,
# pld_core_ready=dut.pld_core_ready,
reset_status=dut.rst_250mhz,
# clr_st=dut.clr_st,
# refclk=dut.refclk,
coreclkout_hip=dut.clk_250mhz,
# RX interface
rx_bus=S10RxBus.from_prefix(dut, "rx_st"),
# TX interface
tx_bus=S10TxBus.from_prefix(dut, "tx_st"),
# TX flow control
tx_ph_cdts=dut.tx_ph_cdts,
tx_pd_cdts=dut.tx_pd_cdts,
tx_nph_cdts=dut.tx_nph_cdts,
tx_npd_cdts=dut.tx_npd_cdts,
tx_cplh_cdts=dut.tx_cplh_cdts,
tx_cpld_cdts=dut.tx_cpld_cdts,
tx_hdr_cdts_consumed=dut.tx_hdr_cdts_consumed,
tx_data_cdts_consumed=dut.tx_data_cdts_consumed,
tx_cdts_type=dut.tx_cdts_type,
tx_cdts_data_value=dut.tx_cdts_data_value,
# Hard IP status
# int_status=dut.int_status,
# int_status_common=dut.int_status_common,
# derr_cor_ext_rpl=dut.derr_cor_ext_rpl,
# derr_rpl=dut.derr_rpl,
# derr_cor_ext_rcv=dut.derr_cor_ext_rcv,
# derr_uncor_ext_rcv=dut.derr_uncor_ext_rcv,
# rx_par_err=dut.rx_par_err,
# tx_par_err=dut.tx_par_err,
# ltssmstate=dut.ltssmstate,
# link_up=dut.link_up,
# lane_act=dut.lane_act,
# currentspeed=dut.currentspeed,
# Power management
# pm_linkst_in_l1=dut.pm_linkst_in_l1,
# pm_linkst_in_l0s=dut.pm_linkst_in_l0s,
# pm_state=dut.pm_state,
# pm_dstate=dut.pm_dstate,
# apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
# apps_ready_entr_l23=dut.apps_ready_entr_l23,
# apps_pm_xmt_turnoff=dut.apps_pm_xmt_turnoff,
# app_init_rst=dut.app_init_rst,
# app_xfer_pending=dut.app_xfer_pending,
# Interrupt interface
app_msi_req=dut.app_msi_req,
app_msi_ack=dut.app_msi_ack,
app_msi_tc=dut.app_msi_tc,
app_msi_num=dut.app_msi_num,
app_msi_func_num=dut.app_msi_func_num,
# app_int_sts=dut.app_int_sts,
# Error interface
# app_err_valid=dut.app_err_valid,
# app_err_hdr=dut.app_err_hdr,
# app_err_info=dut.app_err_info,
# app_err_func_num=dut.app_err_func_num,
# Configuration output
tl_cfg_func=dut.tl_cfg_func,
tl_cfg_add=dut.tl_cfg_add,
tl_cfg_ctl=dut.tl_cfg_ctl,
# Configuration extension bus
# ceb_req=dut.ceb_req,
# ceb_ack=dut.ceb_ack,
# ceb_addr=dut.ceb_addr,
# ceb_din=dut.ceb_din,
# ceb_dout=dut.ceb_dout,
# ceb_wr=dut.ceb_wr,
# ceb_cdm_convert_data=dut.ceb_cdm_convert_data,
# ceb_func_num=dut.ceb_func_num,
# ceb_vf_num=dut.ceb_vf_num,
# ceb_vf_active=dut.ceb_vf_active,
# Hard IP reconfiguration interface
# hip_reconfig_clk=dut.hip_reconfig_clk,
# hip_reconfig_address=dut.hip_reconfig_address,
# hip_reconfig_read=dut.hip_reconfig_read,
# hip_reconfig_readdata=dut.hip_reconfig_readdata,
# hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
# hip_reconfig_write=dut.hip_reconfig_write,
# hip_reconfig_writedata=dut.hip_reconfig_writedata,
# hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
)
# self.dev.log.setLevel(logging.DEBUG)
self.rc.make_port().connect(self.dev)
self.driver = mqnic.Driver()
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
# Ethernet
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start())
self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start())
self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1)
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start())
self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start())
self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2)
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start())
self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start())
self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3)
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start())
self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4)
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start())
self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start())
self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start())
self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start())
self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start())
self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start())
self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start())
self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3)
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start())
self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4)
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start())
self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
# dut.qsfp0_i2c_scl_i.setimmediatevalue(1)
# dut.qsfp0_i2c_sda_i.setimmediatevalue(1)
# dut.qsfp0_intr_n.setimmediatevalue(1)
# dut.qsfp0_mod_prsnt_n.setimmediatevalue(0)
# dut.qsfp0_rx_error_count_0.setimmediatevalue(0)
# dut.qsfp0_rx_error_count_1.setimmediatevalue(0)
# dut.qsfp0_rx_error_count_2.setimmediatevalue(0)
# dut.qsfp0_rx_error_count_3.setimmediatevalue(0)
# dut.qsfp1_i2c_scl_i.setimmediatevalue(1)
# dut.qsfp1_i2c_sda_i.setimmediatevalue(1)
# dut.qsfp1_intr_n.setimmediatevalue(1)
# dut.qsfp1_mod_prsnt_n.setimmediatevalue(0)
# dut.qsfp1_rx_error_count_0.setimmediatevalue(0)
# dut.qsfp1_rx_error_count_1.setimmediatevalue(0)
# dut.qsfp1_rx_error_count_2.setimmediatevalue(0)
# dut.qsfp1_rx_error_count_3.setimmediatevalue(0)
# dut.qspi_dq_i.setimmediatevalue(0)
self.loopback_enable = False
cocotb.start_soon(self._run_loopback())
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
# PCIe
self.rc = RootComplex()
self.dev = S10PcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=2,
# pld_clk_frequency=250e6,
l_tile=False,
# signals
# Clock and reset
# npor=dut.npor,
# pin_perst=dut.pin_perst,
# ninit_done=dut.ninit_done,
# pld_clk_inuse=dut.pld_clk_inuse,
# pld_core_ready=dut.pld_core_ready,
reset_status=dut.rst,
# clr_st=dut.clr_st,
# refclk=dut.refclk,
coreclkout_hip=dut.clk,
# RX interface
rx_bus=S10RxBus.from_prefix(dut, "rx_st"),
# TX interface
tx_bus=S10TxBus.from_prefix(dut, "tx_st"),
# TX flow control
tx_ph_cdts=dut.tx_ph_cdts,
tx_pd_cdts=dut.tx_pd_cdts,
tx_nph_cdts=dut.tx_nph_cdts,
tx_npd_cdts=dut.tx_npd_cdts,
tx_cplh_cdts=dut.tx_cplh_cdts,
tx_cpld_cdts=dut.tx_cpld_cdts,
tx_hdr_cdts_consumed=dut.tx_hdr_cdts_consumed,
tx_data_cdts_consumed=dut.tx_data_cdts_consumed,
tx_cdts_type=dut.tx_cdts_type,
tx_cdts_data_value=dut.tx_cdts_data_value,
# Hard IP status
# int_status=dut.int_status,
# int_status_common=dut.int_status_common,
# derr_cor_ext_rpl=dut.derr_cor_ext_rpl,
# derr_rpl=dut.derr_rpl,
# derr_cor_ext_rcv=dut.derr_cor_ext_rcv,
# derr_uncor_ext_rcv=dut.derr_uncor_ext_rcv,
# rx_par_err=dut.rx_par_err,
# tx_par_err=dut.tx_par_err,
# ltssmstate=dut.ltssmstate,
# link_up=dut.link_up,
# lane_act=dut.lane_act,
# currentspeed=dut.currentspeed,
# Power management
# pm_linkst_in_l1=dut.pm_linkst_in_l1,
# pm_linkst_in_l0s=dut.pm_linkst_in_l0s,
# pm_state=dut.pm_state,
# pm_dstate=dut.pm_dstate,
# apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
# apps_ready_entr_l23=dut.apps_ready_entr_l23,
# apps_pm_xmt_turnoff=dut.apps_pm_xmt_turnoff,
# app_init_rst=dut.app_init_rst,
# app_xfer_pending=dut.app_xfer_pending,
# Interrupt interface
app_msi_req=dut.app_msi_req,
app_msi_ack=dut.app_msi_ack,
app_msi_tc=dut.app_msi_tc,
app_msi_num=dut.app_msi_num,
app_msi_func_num=dut.app_msi_func_num,
# app_int_sts=dut.app_int_sts,
# Error interface
# serr_out=dut.serr_out,
# hip_enter_err_mode=dut.hip_enter_err_mode,
# app_err_valid=dut.app_err_valid,
# app_err_hdr=dut.app_err_hdr,
# app_err_info=dut.app_err_info,
# app_err_func_num=dut.app_err_func_num,
# Configuration output
tl_cfg_func=dut.tl_cfg_func,
tl_cfg_add=dut.tl_cfg_add,
tl_cfg_ctl=dut.tl_cfg_ctl,
# Configuration extension bus
# ceb_req=dut.ceb_req,
# ceb_ack=dut.ceb_ack,
# ceb_addr=dut.ceb_addr,
# ceb_din=dut.ceb_din,
# ceb_dout=dut.ceb_dout,
# ceb_wr=dut.ceb_wr,
# ceb_cdm_convert_data=dut.ceb_cdm_convert_data,
# ceb_func_num=dut.ceb_func_num,
# ceb_vf_num=dut.ceb_vf_num,
# ceb_vf_active=dut.ceb_vf_active,
# Hard IP reconfiguration interface
# hip_reconfig_clk=dut.hip_reconfig_clk,
# hip_reconfig_address=dut.hip_reconfig_address,
# hip_reconfig_read=dut.hip_reconfig_read,
# hip_reconfig_readdata=dut.hip_reconfig_readdata,
# hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
# hip_reconfig_write=dut.hip_reconfig_write,
# hip_reconfig_writedata=dut.hip_reconfig_writedata,
# hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
)
self.test_dev = PcieIfTestDevice(
clk=dut.clk,
rst=dut.rst,
rx_req_tlp_bus=PcieIfRxBus.from_prefix(dut, "rx_req_tlp"),
tx_cpl_tlp_bus=PcieIfTxBus.from_prefix(dut, "tx_cpl_tlp"),
tx_rd_req_tlp_bus=PcieIfTxBus.from_prefix(dut, "tx_rd_req_tlp"),
rd_req_tx_seq_num=dut.m_axis_rd_req_tx_seq_num,
rd_req_tx_seq_num_valid=dut.m_axis_rd_req_tx_seq_num_valid,
tx_wr_req_tlp_bus=PcieIfTxBus.from_prefix(dut, "tx_wr_req_tlp"),
wr_req_tx_seq_num=dut.m_axis_wr_req_tx_seq_num,
wr_req_tx_seq_num_valid=dut.m_axis_wr_req_tx_seq_num_valid,
rx_cpl_tlp_bus=PcieIfRxBus.from_prefix(dut, "rx_cpl_tlp"),
)
self.dev.log.setLevel(logging.DEBUG)
self.rc.make_port().connect(self.dev)
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
self.dev.functions[0].configure_bar(0, 1024 * 1024)
self.test_dev.add_mem_region(1024 * 1024)
self.dev.functions[0].configure_bar(1, 1024 * 1024, True, True)
self.test_dev.add_prefetchable_mem_region(1024 * 1024)
self.dev.functions[0].configure_bar(3, 1024, False, False, True)
self.test_dev.add_io_region(1024)
self.dut.msi_irq.setimmediatevalue(0)