def getTop():
top = Component('aegean_top')
top.addPackage('ieee','std_logic_1164')
top.addPackage('ieee','numeric_std')
top.addPackage('work','config')
top.addPackage('work','ocp')
return top
def generate(self):
# Instantiation of noc nodes and links
nodes = self.getNodes()
noc = Component('noc')
noc.addPackage('ieee','std_logic_1164')
noc.addPackage('ieee','std_logic_unsigned')
noc.addPackage('ieee','numeric_std')
noc.addPackage('work','config_types')
noc.addPackage('work','config')
noc.addPackage('work','ocp')
noc.addPackage('work','noc_defs')
noc.addPackage('work','noc_interface')
noc.entity.addPort('clk','in','std_logic',1)
noc.entity.addPort('reset','in','std_logic',1)
noc.entity.addPort('ocp_io_ms','in','ocp_io_m_a',1)
noc.entity.addPort('ocp_io_ss','out','ocp_io_s_a',1)
noc.entity.addPort('spm_ports_m','out','spm_masters',1)
noc.entity.addPort('spm_ports_s','in','spm_slaves',1)
noc.arch.declSignal('north_in_f, east_in_f, south_in_f, west_in_f','link_m_f')
noc.arch.declSignal('north_in_b, east_in_b, south_in_b, west_in_b','link_m_b')
noc.arch.declSignal('north_out_f, east_out_f, south_out_f, west_out_f','link_m_f')
noc.arch.declSignal('north_out_b, east_out_b, south_out_b, west_out_b','link_m_b')
for k in range(0,len(nodes)):
j, i = nodes[k].get('loc').strip('()').split(',')
instancename = nodes[k].get('id') + '_' + nodes[k].get('IPTypeRef')
nocNode = self.getNocNode()
self.bindNocNode(nocNode,k,i,j)
noc.arch.instComp(nocNode,instancename)
noc.arch.declComp(nocNode)
if self.getTopType() == 'custom':
links = self.getLinks()
for k in range(0,len(links)):
j1, i1 = links[k].get('source').strip('()').split(',')
j2, i2 = links[k].get('sink').strip('()').split(',')
same_col = (j1 == j2)
same_row = (i1 == i2)
#if not (same_row != same_col):
if not ((same_row or same_col) and (same_row != same_col)):
raise SystemExit(__file__ +': Error: Link in specification is illegal. ' + str(etree.tostring(links[k])))
if (abs(int(j1)-int(j2)) > 1) or (abs(int(i1)-int(i2)) > 1):
raise SystemExit(__file__ +': Error: Link is trying to connect cores too far appart. ' + str(etree.tostring(links[k])))
if same_row:
if int(j1) > int(j2):
nocCode.writeEast(noc,i1,i2,j1,j2)
elif int(j1) < int(j2):
nocCode.writeWest(noc,i1,i2,j1,j2)
else:
raise SystemExit(__file__ +': Error: Something is wrong!!!')
if same_col:
if int(i1) > int(i2):
nocCode.writeSouth(noc,i1,i2,j1,j2)
elif int(i1) < int(i2):
nocCode.writeNorth(noc,i1,i2,j1,j2)
else:
raise SystemExit(__file__ +': Error: Something is wrong!!!')
elif self.getTopType() == 'bitorus':
nocCode.writeBitorus(noc)
elif self.getTopType() == 'mesh':
nocCode.writeMesh(noc)
else:
SystemExit(__file__ +': Error: xml validation error')
noc.writeComp(self.p.NOCFile)
routerType = self.getRouterType()
argo_src = open(self.p.BUILD_PATH+'/.argo_src','w')
argo_src.write(self.p.ARGO_PATH+'/src/config_types.vhd ')
argo_src.write(self.p.BUILD_PATH + '/ocp_config.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/ocp/ocp.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/util/math_util.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/noc_defs.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/noc_interface.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/mem/bram.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/mem/bram_tdp.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/ni/counter.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/ni/dma.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/mem/com_spm.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/ni/nAdapter.vhd ')
if routerType == 'sync':
argo_src.write(self.p.ARGO_PATH+'/src/routers/synchronous/xbar.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/synchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/synchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/noc/synchronous/noc_node.vhd ')
#raise SystemExit(__file__ +': Error: routerType: ' + routerType + ' is not yet implemented.')
elif routerType == 'async':
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/delays.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/rtl/matched_delay.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/rtl/sr_latch.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/rtl/c_gate_generic.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/crossbar.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/latch_controller.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/channel_latch.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu_latch.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu_comb.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/crossbar_stage.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/fifo.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/noc/asynchronous/noc_node.vhd ')
elif routerType == 'async_fpga':
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/delays.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/fpga/matched_delay.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/fpga/AS_C2.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/fpga/c_gate_generic.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/crossbar.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/latch_controller.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/channel_latch.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu_latch.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu_comb.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/crossbar_stage.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/fifo.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/noc/asynchronous/noc_node.vhd ')
argo_src.close()
return noc
def getAegean():
aegean = Component('aegean')
aegean.addPackage('ieee','std_logic_1164')
aegean.addPackage('ieee','numeric_std')
aegean.addPackage('work','config_types')
aegean.addPackage('work','config')
aegean.addPackage('work','ocp')
aegean.addPackage('work','argo_types')
aegean.addPackage('work','noc_interface')
aegean.entity.addPort('clk')
aegean.entity.addPort('reset')
aegean.entity.addPort('sram_burst_m','out','ocp_burst_m')
aegean.entity.addPort('sram_burst_s','in','ocp_burst_s')
return aegean
def getTest():
test = Component('aegean_testbench')
test.addPackage('ieee','std_logic_1164')
test.addPackage('ieee','numeric_std')
test.addPackage('std','textio')
test.addPackage('modelsim_lib','util')
test.addPackage('work','test')
test.addPackage('work','ocp')
return test
def getAegean():
aegean = Component('aegean')
aegean.addPackage('ieee', 'std_logic_1164')
aegean.addPackage('ieee', 'numeric_std')
aegean.addPackage('work', 'config_types')
aegean.addPackage('work', 'config')
aegean.addPackage('work', 'ocp')
aegean.addPackage('work', 'argo_types')
aegean.addPackage('work', 'noc_interface')
aegean.entity.addPort('clk')
aegean.entity.addPort('reset')
aegean.entity.addPort('sram_burst_m', 'out', 'ocp_burst_m')
aegean.entity.addPort('sram_burst_s', 'in', 'ocp_burst_s')
return aegean
def generate(self):
# Instantiation of noc nodes and links
nodes = self.getNodes()
noc = Component('noc')
noc.addPackage('ieee', 'std_logic_1164')
noc.addPackage('ieee', 'std_logic_unsigned')
noc.addPackage('ieee', 'numeric_std')
noc.addPackage('work', 'config_types')
noc.addPackage('work', 'config')
noc.addPackage('work', 'ocp')
noc.addPackage('work', 'argo_types')
noc.addPackage('work', 'noc_interface')
noc.entity.addPort('clk', 'in', 'std_logic', 1)
noc.entity.addPort('reset', 'in', 'std_logic', 1)
noc.entity.addPort('ocp_io_ms', 'in', 'ocp_io_m_a', 1)
noc.entity.addPort('supervisor', 'in', 'std_logic_vector', len(nodes))
noc.entity.addPort('ocp_io_ss', 'out', 'ocp_io_s_a', 1)
noc.entity.addPort('spm_ports_m', 'out', 'mem_if_masters', 1)
noc.entity.addPort('spm_ports_s', 'in', 'mem_if_slaves', 1)
noc.entity.addPort('irq', 'out', 'std_logic_vector', len(nodes) * 2)
noc.arch.declSignal('master_run', 'std_logic')
noc.arch.declSignal('north_in_f, east_in_f, south_in_f, west_in_f',
'link_m_f')
noc.arch.declSignal('north_in_b, east_in_b, south_in_b, west_in_b',
'link_m_b')
noc.arch.declSignal('north_out_f, east_out_f, south_out_f, west_out_f',
'link_m_f')
noc.arch.declSignal('north_out_b, east_out_b, south_out_b, west_out_b',
'link_m_b')
for k in range(0, len(nodes)):
j, i = nodes[k].get('loc').strip('()').split(',')
instancename = nodes[k].get('id') + '_' + nodes[k].get(
'IPTypeRef').replace('-', '_')
nocNode = self.getNocNode()
if k == 0:
nocMaster = True
else:
nocMaster = False
self.bindNocNode(nocNode, k, i, j, nocMaster)
noc.arch.instComp(nocNode, instancename)
noc.arch.declComp(nocNode)
if self.getTopType() == 'custom':
links = self.getLinks()
for k in range(0, len(links)):
j1, i1 = links[k].get('source').strip('()').split(',')
j2, i2 = links[k].get('sink').strip('()').split(',')
same_col = (j1 == j2)
same_row = (i1 == i2)
#if not (same_row != same_col):
if not ((same_row or same_col) and (same_row != same_col)):
raise SystemExit(
__file__ +
': Error: Link in specification is illegal. ' +
str(etree.tostring(links[k])))
if (abs(int(j1) - int(j2)) > 1) or (abs(int(i1) - int(i2)) >
1):
raise SystemExit(
__file__ +
': Error: Link is trying to connect cores too far appart. '
+ str(etree.tostring(links[k])))
if same_row:
if int(j1) > int(j2):
nocCode.writeEast(noc, i1, i2, j1, j2)
elif int(j1) < int(j2):
nocCode.writeWest(noc, i1, i2, j1, j2)
else:
raise SystemExit(__file__ +
': Error: Something is wrong!!!')
if same_col:
if int(i1) > int(i2):
nocCode.writeSouth(noc, i1, i2, j1, j2)
elif int(i1) < int(i2):
nocCode.writeNorth(noc, i1, i2, j1, j2)
else:
raise SystemExit(__file__ +
': Error: Something is wrong!!!')
elif self.getTopType() == 'bitorus':
nocCode.writeBitorus(noc)
elif self.getTopType() == 'mesh':
nocCode.writeMesh(noc)
else:
SystemExit(__file__ + ': Error: xml validation error')
noc.writeComp(self.p.NOCFile)
routerType = self.getRouterType()
argo_src = open(self.p.BUILD_PATH + '/.argo_src', 'w')
argo_src.write(self.p.ARGO_PATH + '/src/config_types.vhd ')
argo_src.write(self.p.BUILD_PATH + '/ocp_config.vhd ')
argo_src.write(self.p.BUILD_PATH + '/config.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ocp/ocp.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/util/math_util.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/argo_types.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/noc_interface.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/mem/tdp_ram.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/mem/tdp_bram.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/rx_unit.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/irq_fifo.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/config_bus.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/spm_bus.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/packet_manager.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/schedule_table.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/TDM_controller.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/MC_controller.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/mem/com_spm.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/network_interface.vhd ')
if routerType == 'sync':
argo_src.write(self.p.ARGO_PATH +
'/src/routers/synchronous/xbar.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/synchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/synchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/noc/synchronous/noc_node.vhd ')
#raise SystemExit(__file__ +': Error: routerType: ' + routerType + ' is not yet implemented.')
elif routerType == 'async':
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/delays.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/rtl/matched_delay.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/rtl/sr_latch.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/rtl/c_gate_generic.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/crossbar.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/latch_controller.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/channel_latch.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu_latch.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu_comb.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/crossbar_stage.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/fifo.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/noc/asynchronous/noc_node.vhd ')
elif routerType == 'async_fpga':
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/delays.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/fpga/matched_delay.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/fpga/AS_C2.vhd ')
argo_src.write(
self.p.ARGO_PATH +
'/src/routers/asynchronous/fpga/c_gate_generic.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/crossbar.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/latch_controller.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/channel_latch.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu_latch.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu_comb.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/crossbar_stage.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/fifo.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/noc/asynchronous/noc_node.vhd ')
argo_src.close()
return noc
def getTest():
test = Component('aegean_testbench')
test.addPackage('ieee', 'std_logic_1164')
test.addPackage('ieee', 'numeric_std')
test.addPackage('std', 'textio')
test.addPackage('modelsim_lib', 'util')
test.addPackage('work', 'test')
test.addPackage('work', 'ocp')
return test
