def __init__(self,
which,
rx_ant_a='RXA',
rx_ant_b='RXA',
rx_source_a='A',
rx_source_b='B'):
"""
USRP dual source contructor.
@param which the unit number
@param rx_ant_a the antenna choice
@param rx_ant_b the antenna choice
"""
#initialize hier2 block
gr.hier_block2.__init__(
self,
'usrp_dual_source',
gr.io_signature(0, 0, 0),
gr.io_signature(2, 2, self._get_io_size()),
)
#create usrp object
self._make_usrp(which=which, nchan=2)
subdev_spec_a = common.to_spec(rx_source_a, rx_ant_a)
subdev_spec_b = common.to_spec(rx_source_b, rx_ant_b)
self._get_u().set_mux(self._get_u().determine_rx_mux_value(
subdev_spec_a, subdev_spec_b))
self._subdev_a = self._get_u().selected_subdev(subdev_spec_a)
self._subdev_b = self._get_u().selected_subdev(subdev_spec_b)
#connect
deinter = gr.deinterleave(self._get_io_size())
self.connect(self._get_u(), deinter)
for i in range(2):
self.connect((deinter, i), (self, i))
def __init__(self, which):
"""
USRP simple sink contructor.
@param which the unit number
"""
#initialize hier2 block
gr.hier_block2.__init__(
self,
'usrp_dual_sink',
gr.io_signature(2, 2, self._get_io_size()),
gr.io_signature(0, 0, 0),
)
#create usrp object
self._make_usrp(which=which, nchan=2)
subdev_spec_a = common.to_spec('A')
subdev_spec_b = common.to_spec('B')
self._get_u().set_mux(self._get_u().determine_tx_mux_value(
subdev_spec_a, subdev_spec_b))
self._subdev_a = self._get_u().selected_subdev(subdev_spec_a)
self._subdev_b = self._get_u().selected_subdev(subdev_spec_b)
#connect
inter = gr.interleave(self._get_io_size())
self.connect(inter, self._get_u())
for i in range(2):
self.connect((self, i), (inter, i))
def __init__(self, which, side='A', rx_ant='RXA', no_hb=False):
"""
USRP simple source contructor.
@param which the unit number
@param side the usrp side A or B
@param rx_ant the antenna choice
@param no_hb disable half band filters
"""
self._no_hb = no_hb
#initialize hier2 block
gr.hier_block2.__init__(
self,
'usrp_simple_source',
gr.io_signature(0, 0, 0),
gr.io_signature(1, 1, self._get_io_size()),
)
#create usrp object
if self._no_hb:
self._make_usrp(which=which,
nchan=1,
fpga_filename="std_4rx_0tx.rbf")
else:
self._make_usrp(which=which, nchan=1)
subdev_spec = common.to_spec(side, rx_ant)
self._get_u().set_mux(
self._get_u().determine_rx_mux_value(subdev_spec))
self._subdev = self._get_u().selected_subdev(subdev_spec)
if common.is_flex(rx_ant): self._subdev.select_rx_antenna(rx_ant)
#connect
self.connect(self._get_u(), self)
def __init__(self, which):
"""
USRP simple sink contructor.
@param which the unit number
"""
# initialize hier2 block
gr.hier_block2.__init__(
self, "usrp_dual_sink", gr.io_signature(2, 2, self._get_io_size()), gr.io_signature(0, 0, 0)
)
# create usrp object
self._make_usrp(which=which, nchan=2)
subdev_spec_a = common.to_spec("A")
subdev_spec_b = common.to_spec("B")
self._get_u().set_mux(self._get_u().determine_tx_mux_value(subdev_spec_a, subdev_spec_b))
self._subdev_a = self._get_u().selected_subdev(subdev_spec_a)
self._subdev_b = self._get_u().selected_subdev(subdev_spec_b)
# connect
inter = gr.interleave(self._get_io_size())
self.connect(inter, self._get_u())
for i in range(2):
self.connect((self, i), (inter, i))
def __init__(self, which, rx_ant_a="RXA", rx_ant_b="RXA"):
"""
USRP dual source contructor.
@param which the unit number
@param rx_ant_a the antenna choice
@param rx_ant_b the antenna choice
"""
# initialize hier2 block
gr.hier_block2.__init__(
self, "usrp_dual_source", gr.io_signature(0, 0, 0), gr.io_signature(2, 2, self._get_io_size())
)
# create usrp object
self._make_usrp(which=which, nchan=2)
subdev_spec_a = common.to_spec("A", rx_ant_a)
subdev_spec_b = common.to_spec("B", rx_ant_b)
self._get_u().set_mux(self._get_u().determine_rx_mux_value(subdev_spec_a, subdev_spec_b))
self._subdev_a = self._get_u().selected_subdev(subdev_spec_a)
self._subdev_b = self._get_u().selected_subdev(subdev_spec_b)
# connect
deinter = gr.deinterleave(self._get_io_size())
self.connect(self._get_u(), deinter)
for i in range(2):
self.connect((deinter, i), (self, i))
def __init__(self, which, side='A'): """ USRP simple sink contructor. @param which the unit number @param side the usrp side A or B """ #initialize hier2 block gr.hier_block2.__init__( self, 'usrp_simple_sink', gr.io_signature(1, 1, self._get_io_size()), gr.io_signature(0, 0, 0), ) #create usrp object self._make_usrp(which=which, nchan=1) subdev_spec = common.to_spec(side) self._get_u().set_mux(self._get_u().determine_tx_mux_value(subdev_spec)) self._subdev = self._get_u().selected_subdev(subdev_spec) #connect self.connect(self, self._get_u())
def __init__(self, which, side='A'):
"""
USRP simple sink contructor.
@param which the unit number
@param side the usrp side A or B
"""
#initialize hier2 block
gr.hier_block2.__init__(
self,
'usrp_simple_sink',
gr.io_signature(1, 1, self._get_io_size()),
gr.io_signature(0, 0, 0),
)
#create usrp object
self._make_usrp(which=which, nchan=1)
subdev_spec = common.to_spec(side)
self._get_u().set_mux(
self._get_u().determine_tx_mux_value(subdev_spec))
self._subdev = self._get_u().selected_subdev(subdev_spec)
#connect
self.connect(self, self._get_u())
def __init__(self, which, side='A', rx_ant='RXA', no_hb=False): """ USRP simple source contructor. @param which the unit number @param side the usrp side A or B @param rx_ant the antenna choice @param no_hb disable half band filters """ self._no_hb = no_hb #initialize hier2 block gr.hier_block2.__init__( self, 'usrp_simple_source', gr.io_signature(0, 0, 0), gr.io_signature(1, 1, self._get_io_size()), ) #create usrp object if self._no_hb: self._make_usrp(which=which, nchan=1, fpga_filename="std_4rx_0tx.rbf") else: self._make_usrp(which=which, nchan=1) subdev_spec = common.to_spec(side, rx_ant) self._get_u().set_mux(self._get_u().determine_rx_mux_value(subdev_spec)) self._subdev = self._get_u().selected_subdev(subdev_spec) if common.is_flex(rx_ant): self._subdev.select_rx_antenna(rx_ant) #connect self.connect(self._get_u(), self)
