s0 = delay(clk, s0, 1)
s1 = delay(clk, s1, 1)
valid = delay(clk, valid, 1)
#reorder
s0, s1, valid = reorder(clk, s0, s1, valid, stage)
return bit_reverse_order(clk, s0, s1, valid, 2**(num_stages-1))
clk = Clock("clk")
base_type = SFixed(16, 8)
subtype = Complex(base_type)
a = subtype.input("in")
b = subtype.input("in")
valid = Boolean().input("valid")
s0, s1, valid_out = fft(clk, a, b, valid, 3)
test = [1, 0, 1, 0, 1, 0, 1, 0]
clk.initialise()
for i in range(10):
for i in range(4):
a.set(test[i]), b.set(test[i+4]), valid.set(1)
print(("%10s %10s %10s"%(s0.get(), s1.get(), valid_out.get())))
clk.tick()
valid.set(0)
print(("%10s %10s %10s"%(s0.get(), s1.get(), valid_out.get())))
clk.tick()
