def fft_shift_get_all(correlator):
"""
Get the current FFT shift settings, coarse and fine, for all correlator f-engines.
"""
rv = {}
for in_n, ant_str in enumerate(correlator.config._get_ant_mapping_list()):
ffpga_n, xfpga_n, fxaui_n, xxaui_n, feng_input = correlator.get_ant_str_location(ant_str)
coarse_ctrl = corr_functions.read_masked_register([correlator.ffpgas[ffpga_n]], register_fengine_coarse_control)
fine_ctrl = corr_functions.read_masked_register([correlator.ffpgas[ffpga_n]], register_fengine_fine_control)
rv[ant_str] = [coarse_ctrl[0]['fft_shift'], fine_ctrl[0]['fft_shift']]
return rv
def fft_shift_get_all(correlator):
"""
Get the current FFT shift settings, coarse and fine, for all correlator f-engines.
"""
rv = {}
for in_n, ant_str in enumerate(correlator.config._get_ant_mapping_list()):
ffpga_n, xfpga_n, fxaui_n, xxaui_n, feng_input = correlator.get_ant_str_location(
ant_str)
coarse_ctrl = corr_functions.read_masked_register(
[correlator.ffpgas[ffpga_n]], register_fengine_coarse_control)
fine_ctrl = corr_functions.read_masked_register(
[correlator.ffpgas[ffpga_n]], register_fengine_fine_control)
rv[ant_str] = [coarse_ctrl[0]['fft_shift'], fine_ctrl[0]['fft_shift']]
return rv
def feng_status_get(c, ant_str):
"""Reads and decodes the status register for a given antenna. Adds some other bits 'n pieces relating to Fengine status."""
#'sync_val': 28:30, #This is the number of clocks of sync pulse offset for the demux-by-four ADC 1PPS.
ffpga_n, xfpga_n, fxaui_n, xxaui_n, feng_input = c.get_ant_str_location(ant_str)
rv = corr_functions.read_masked_register([c.ffpgas[ffpga_n]], register_fengine_fstatus, names = ['fstatus%i' % feng_input])[0]
if rv['xaui_lnkdn'] or rv['xaui_over'] or rv['clk_err'] or rv['ct_error'] or rv['fft_overrange']:
rv['lru_state']='fail'
elif rv['adc_overrange'] or rv['adc_disabled']:
rv['lru_state']='warning'
else:
rv['lru_state']='ok'
return rv
def feng_status_get(c, ant_str):
"""
Reads and decodes the status register for a given antenna. Adds some other bits 'n pieces relating to Fengine status.
"""
ffpga_n, xfpga_n, fxaui_n, xxaui_n, feng_input = c.get_ant_str_location(ant_str)
rv = corr_functions.read_masked_register([c.ffpgas[ffpga_n]], register_fengine_fstatus, names = ['fstatus%i' % feng_input])[0]
if rv['xaui_lnkdn'] or rv['xaui_over'] or rv['clk_err'] or rv['ct_error'] or rv['fine_fft_overrange'] or rv['coarse_fft_overrange']:
rv['lru_state']='fail'
elif rv['adc_overrange']:
rv['lru_state']='warning'
else:
rv['lru_state']='ok'
return rv
def feng_status_get(c, ant_str):
"""Reads and decodes the status register for a given antenna. Adds some other bits 'n pieces relating to Fengine status."""
#'sync_val': 28:30, #This is the number of clocks of sync pulse offset for the demux-by-four ADC 1PPS.
ffpga_n, xfpga_n, fxaui_n, xxaui_n, feng_input = c.get_ant_str_location(
ant_str)
rv = corr_functions.read_masked_register([c.ffpgas[ffpga_n]],
register_fengine_fstatus,
names=['fstatus%i' % feng_input
])[0]
if rv['xaui_lnkdn'] or rv['xaui_over'] or rv['clk_err'] or rv[
'ct_error'] or rv['fft_overrange']:
rv['lru_state'] = 'fail'
elif rv['adc_overrange'] or rv['adc_disabled']:
rv['lru_state'] = 'warning'
else:
rv['lru_state'] = 'ok'
return rv
def feng_status_get(c, ant_str):
"""
Reads and decodes the status register for a given antenna. Adds some other bits 'n pieces relating to Fengine status.
"""
ffpga_n, xfpga_n, fxaui_n, xxaui_n, feng_input = c.get_ant_str_location(
ant_str)
rv = corr_functions.read_masked_register([c.ffpgas[ffpga_n]],
register_fengine_fstatus,
names=['fstatus%i' % feng_input
])[0]
if rv['xaui_lnkdn'] or rv['xaui_over'] or rv['clk_err'] or rv[
'ct_error'] or rv['fine_fft_overrange'] or rv[
'coarse_fft_overrange']:
rv['lru_state'] = 'fail'
elif rv['adc_overrange']:
rv['lru_state'] = 'warning'
else:
rv['lru_state'] = 'ok'
return rv
