def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
# Remove this and replace with your implementation!
raise AssertionError("connect not implemented in class DataMemory!")
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert(len(inputSources) == 2), 'control unit should have 2 input'
assert(len(outputValueNames) == 0), 'control unit has 0 output'
assert(len(control) == 0), 'control unit has no control signal'
assert(len(outputSignalNames) == 11), 'control unit has 11 control output signals'
self.inputZero = inputSources[0][1] # opcode
self.inputOne = inputSources[1][1] # instruction[5:0]
self.regdst = outputSignalNames[0]
self.jump = outputSignalNames[1]
self.branch = outputSignalNames[2]
self.memread = outputSignalNames[3]
self.memtoreg = outputSignalNames[4]
self.aluop = outputSignalNames[5] # 4 bit control direct signal
self.memwrite = outputSignalNames[6]
self.alusrc = outputSignalNames[7]
self.regwrite = outputSignalNames[8]
self.branchnotequal = outputSignalNames[9]
self.loadui = outputSignalNames[10]
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
assert (
len(inputSources) == 1), ' InstructionMemory should have 1 input'
assert (len(outputValueNames) == 7
), ' InstructionMemory has only 7 outputs'
assert (len(control) == 0), 'InstructionMemory has no control signal'
assert (len(outputSignalNames) == 0
), 'InstructionMemory does not have any control output'
self.inputZero = inputSources[0][1] #'read address port'
self.output1 = outputValueNames[0] #'control signal or opcode '
self.output2 = outputValueNames[1] # ' read register 1'
self.output3 = outputValueNames[
2] #'read register 2 or mux upper input'
# self.output4 = outputValueNames[3] 'mux upper input'
self.output4 = outputValueNames[3] # 'mux lower input'
self.output5 = outputValueNames[4] # 'sign extend'
self.output6 = outputValueNames[5] # 'alu control'
self.output7 = outputValueNames[6] # 'jump address'
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
assert (len(inputSources) == 1), 'Random control has one input'
assert (
len(outputValueNames) == 0), 'Random control does not have output'
assert (len(control) == 0
), 'Random control does not have any control signals'
assert (len(outputSignalNames) == 11
), 'Random control has eleven control outputs'
self.input_Instruction = inputSources[0][1]
self.signal_Regdest = outputSignalNames[0]
self.signal_Regwrite = outputSignalNames[1]
self.signal_ALUsrc = outputSignalNames[2]
self.signal_ALUop = outputSignalNames[3]
self.signal_Memwrite = outputSignalNames[4]
self.signal_Memtoreg = outputSignalNames[5]
self.signal_Memread = outputSignalNames[6]
self.signal_ALUtype = outputSignalNames[7]
self.signal_Andgate = outputSignalNames[8]
self.signal_Jmpctrl = outputSignalNames[9]
self.signal_Luictrl = outputSignalNames[10]
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert(len(inputSources) == len(outputValueNames)), 'Wall must the same amount of inputs as outputs'
assert(len(control) == len(outputSignalNames)), 'Wall must the same amount of control signals as countrol output signals'
self.inputSources = inputSources
self.control = control
def connect(self, inputSources, outputValueNames, control, outputSignalNames): CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames) assert(len(inputSources) == 0), 'Constants have no input' assert(len(outputValueNames) == 1), 'Constants has only one output' assert(len(control) == 0), 'Constants do not have any control signal' assert(len(outputSignalNames) == 0), 'Constants do not have any control output' self.outputName = outputValueNames[0]
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert(len(inputSources) == 1), ' left Shift16 should have 1 input'
assert(len(outputValueNames) == 1), ' left Shift16 has only 1 output'
assert(len(control) == 0), ' left shift16 has 0 control signal'
assert(len(outputSignalNames) == 0), ' left shift16 has 0 control output'
self.inputZero = inputSources[0][1] #input
self.output1 = outputValueNames[0] #output
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert(len(inputSources) == 1), 'AluControl should have two input'
assert(len(outputValueNames) == 0), 'AluControl has only one output'
assert(len(control) == 1), 'AluControl has no control signal'
assert(len(outputSignalNames) == 1), 'AluControl does not have any control output'
self.inputZero = inputSources[0][1]
self.ctrlALUOp = control[0][1]
self.controlZero = outputSignalNames[0]
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert(len(inputSources) == 2), 'SignExtender should have two input'
assert(len(outputValueNames) == 1), 'SignExtender has only one output'
assert(len(control) == 0), 'SignExtender has no control signal'
assert(len(outputSignalNames) == 0), 'SignExtender does not have any control output'
self.inputZero = inputSources[0][1]
self.inputOne = inputSources[1][1]
self.outputName = outputValueNames[0]
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
# Remove this and replace with your implementation!
# raise AssertionError("connect not implemented in class InstructionMemory!");
assert (len(inputSources) == 1), 'Instruction memory should have one input'
assert (len(outputValueNames) == 1), 'Instruction memory has only one output'
assert (len(control) == 0), 'Instruction memory has no control signal'
assert (len(outputSignalNames) == 0), 'Instruction memory does not have any control output'
self.input_pcAdress = inputSources[0][1]
self.output_Instruction = outputValueNames[0]
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert (len(inputSources) == 1), 'PC should have one input'
assert (len(outputValueNames) == 1), 'PC has only one output'
assert (len(control) == 0), 'PC has no control input'
assert (len(outputSignalNames) == 0), 'PC should not have any control output'
self.inputField_newPcAddress = inputSources[0][1]
self.outputField_pcAddress = outputValueNames[0]
self.inputValues[self.inputField_newPcAddress] = format(int(self.baseaddr, 16), "#034b") # initialize PC
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
self.inputNames = []
for src, name in inputSources:
self.inputNames.append(name)
self.controlNames = []
for src, name in control:
self.controlNames.append(name)
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
assert (len(inputSources) == 2), 'Adder should have two inputs'
assert (len(outputValueNames) == 1), 'Adder has only one output'
assert (len(control) == 0), 'Adder should not have any control signal'
assert (len(outputSignalNames) == 0
), 'Adder should not have any control output'
self.outputName = outputValueNames[0]
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
assert (len(inputSources) == 0), 'AndGate has no inputs'
assert (len(outputValueNames) == 0), 'AndGate has no outputs'
assert (len(control) == 2), 'AndGate has two control signals'
assert (len(outputSignalNames) == 1), 'AndGate has one control output'
self.signalOne = control[0][1]
self.signalTwo = control[1][1]
self.result = outputSignalNames[0]
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert(len(inputSources) == 2), ' DataMemory should have 2 inputs'
assert(len(outputValueNames) == 1), ' DataMemory has only 1 output'
assert(len(control) == 2), 'DataMemory has 2 control signal'
assert(len(outputSignalNames) == 0), 'DataMemory does not have any control output'
self.inputZero = inputSources[0][1] # read address port'
self.inputOne = inputSources[1][1] # write data port'
self.output1 = outputValueNames[0] # read data port'
self.controlName1 = control[0][1] # memwrite contol signal'
self.controlName2 = control[1][1] # memread contol signal'
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
assert (len(inputSources) == 1), 'LeftShiftTwo has one input'
assert (len(outputValueNames) == 1), 'LeftShiftTwo has one output'
assert (len(control) == 0), 'leftShiftTwo has no control signals'
assert (len(outputSignalNames) == 0
), 'LeftShiftTwo does not have any control output'
self.inputData = inputSources[0][1]
self.outputResult = outputValueNames[0]
def connect(self, inputSources, outputValueNames, control,
outputRegWriteNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputRegWriteNames)
#input names
self.reg = inputSources[0][1]
self.reg2 = inputSources[1][1]
self.writeReg = inputSources[2][1]
self.writeData = inputSources[3][1]
self.regWrite = control[0][1]
self.readData = outputValueNames[0]
self.readData2 = outputValueNames[1]
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
assert (len(inputSources) == 2)
assert (len(outputValueNames) == 1)
assert (len(control) == 0)
assert (len(outputSignalNames) == 0)
self.inputZero = inputSources[0][1]
self.inputOne = inputSources[1][1]
self.outputName = outputValueNames[0]
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
assert (len(inputSources) == 1), ' signextend should have 1 input'
assert (len(outputValueNames) == 1), ' signextend has only 1 output'
assert (len(control) == 0), ' signextend has 0 control signal'
assert (
len(outputSignalNames) == 0), ' signextend has 0 control output'
self.inputZero = inputSources[0][1] #'input '
self.output1 = outputValueNames[0] #'output '
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
assert (len(inputSources) == 1), 'Breaker should have one input'
assert (len(outputValueNames) == 1), 'Breaker has only one output'
assert (
len(control) == 0), 'Breaker should not have any control signal'
assert (len(outputSignalNames) == 0
), 'Breaker should not have any control output'
self.Input = inputSources[0][1]
self.Output = outputValueNames[0]
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert (len(inputSources) == 2), 'ALU should have two inputs'
assert (len(outputValueNames) == 1), 'ALU has one output'
assert (len(control) == 2), 'ALU has two control signals'
assert (len(outputSignalNames) == 1), 'ALU does has one control output'
self.LeftOp = inputSources[0][1]
self.RightOp = inputSources[1][1]
self.outputResult = outputValueNames[0]
self.ALUOp = control[0][1]
self.ALUOpT = control[1][1]
self.outputZero = outputSignalNames[0]
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
assert (len(inputSources) == 0), 'Branch should have two input'
assert (len(outputValueNames) == 0), 'Branch has only one output'
assert (len(control) == 2), 'Branch has no control signal'
assert (len(outputSignalNames) == 1
), 'Branch does not have any control output'
self.sigZero = control[0][1]
self.sigOne = control[1][1]
self.outZero = outputSignalNames[0]
def connect(self, inputSources, outputValueNames, control, outputSignalNames): CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames) ''' Connect branch to input controllers ''' assert(len(inputSources) == 0), 'Branch should have no inputs' assert(len(outputValueNames) == 0), 'Branch has no output' assert(len(control) == 2), 'Branch has two control signals' assert(len(outputSignalNames) == 1), 'Branch has one output signal' self.controlBranch = control[0][1] self.zero = control[1][1] self.output = outputSignalNames[0]
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert (len(inputSources) == 1), 'Splitter has one input'
assert (len(outputValueNames) == 6), 'Splitter has six outputs'
assert (len(control) == 0), 'Splitter has no control signals'
assert (len(outputSignalNames) == 0), 'Splitter does not have any control output'
self.inputData = inputSources[0][1]
self.outputControl = outputValueNames[0]
self.outputR1 = outputValueNames[1]
self.outputR2 = outputValueNames[2]
self.outputWR = outputValueNames[3]
self.outputSE = outputValueNames[4]
self.outputJMP = outputValueNames[5]
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
assert (
len(inputSources) == 0), 'Random control does not have any inputs'
assert (
len(outputValueNames) == 0), 'Random control does not have output'
assert (len(control) == 0
), 'Random control does not have any control signals'
assert (len(outputSignalNames) == 1
), 'Random control has one control output'
self.signalName = outputSignalNames[0]
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
'''
Connect ShiftLeft2 to input source
'''
assert (len(inputSources) == 1), 'ShiftLeft2 has one input'
assert (len(outputValueNames) == 1), 'ShiftLeft2 has one output'
assert (len(control) == 0), 'ShiftLeft2 has no control signal'
assert (
len(outputSignalNames) == 0), 'ShiftLeft2 has no control output'
self.input = inputSources[0][1]
self.output = outputValueNames[0]
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
'''
Connect mux to input sources and controller
Note that the first inputSource is input zero, and the second is input 1
'''
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert(len(inputSources) == 2), 'Mux should have two inputs'
assert(len(outputValueNames) == 1), 'Mux has only one output'
assert(len(control) == 1), 'Mux has one control signal'
assert(len(outputSignalNames) == 0), 'Mux does not have any control output'
self.inputZero = inputSources[0][1]
self.inputOne = inputSources[1][1]
self.outputName = outputValueNames[0]
self.controlName = control[0][1]
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert(len(inputSources) == 1), 'InstructionMemory should have one input'
assert(len(outputValueNames) == 8), 'InstructionMemory has eight outputs'
assert(len(control) == 0), 'Memory has no control signal'
assert(len(outputSignalNames) == 0), 'Memory does not have any control output'
self.inputZero = inputSources[0][1]
self.outputOpcode = outputValueNames[0]
self.outputRs = outputValueNames[1]
self.outputRt = outputValueNames[2]
self.outputRd = outputValueNames[3]
self.outputShamt = outputValueNames[4]
self.outputFunct = outputValueNames[5]
self.outputImm = outputValueNames[6]
self.outputAddr = outputValueNames[7]
def connect(self, inputSources, outputValueNames, control,
outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control,
outputSignalNames)
assert (len(inputSources) == 2
), ' alteredshift left should have 2 inputs'
assert (
len(outputValueNames) == 1), ' alteredshiftleft has only 1 output'
assert (len(control) == 0), 'alteredshiftleft has no control signal'
assert (len(outputSignalNames) == 0
), 'alteredshiftleft does not have any control output'
self.inputZero = inputSources[0][1] # input from instruction 25:0
self.inputOne = inputSources[1][1] # input from adder 31:0
self.output1 = outputValueNames[
0] # 31:28 concatenated with 26 bits left shifted by 2
def connect(self, inputSources, outputValueNames, control, outputSignalNames):
CPUElement.connect(self, inputSources, outputValueNames, control, outputSignalNames)
assert(len(inputSources) == 4), 'reg file should have 4 inputs'
assert(len(outputValueNames) == 2), 'reg file has only 2 output'
assert(len(control) == 1), 'reg file has one control signal'
assert(len(outputSignalNames) == 0), 'reg file does not have any control output'
self.inputZero = inputSources[0][1] #'register read port1 '
self.inputOne = inputSources[1][1] #'register read port2 '
self.inputtwo = inputSources[2][1] #' register write port'
self.inputthree = inputSources[3][1] # ' write data port'
self.outputNameone = outputValueNames[0] # 'read data 1'
self.outputNametwo = outputValueNames[1] # 'read data 2'
self.controlName = control[0][1] # 'regwrite contol signal'