def dac_test():
tb = DAC()
cd_dac = ClockDomain("dac", reset_less=True)
tb.clock_domains += cd_dac
def run(tb):
ida = 0x28FC
qda = 0x3CFC
dut = tb
for i in range(12):
yield dut.idata.eq(ida)
yield dut.qdata.eq(qda)
yield
yield dut.idata.eq(ida + 10)
yield dut.qdata.eq(qda - 20)
yield
yield dut.idata.eq(ida + 20)
yield dut.qdata.eq(qda - 30)
yield
for i in range(20):
yield
run_simulation(tb, run(tb),
vcd_name="dac_test.vcd",
clocks = {
"sys": (8, 0),
"dac": (4, 0),
},
)
def setup(self):
if self.pwm:
self.io.setMode(self.pin)
self.io.write(self.pin, 0)
else:
self.dac = DAC(self.io)
self.dac.setup()
def train_dac_model(self, model_params):
dac = DAC()
smoother_model = dac.build_model(hidden_sizes=[64, 64],
seq_len=50,
no_words=40000,
emb_layer=self.embedding_layer,
lr=0.01)
generator = Generator(sequences=self.sequences,
batch_size=SMOOTH_BS,
max_words=MAX_NUM_WORDS,
max_len=MAX_LEN,
split=SMOOTH_SPLIT)
smoother_model = dac.train(generator,
full_model=smoother_model,
model_params=model_params,
bs=SMOOTH_BS,
split=SMOOTH_SPLIT,
pretrain_epochs=4,
epochs=SMOOTH_EPOCHS)
def run(self, predict_path, smoother_path, eval_path):
self._parse_corpus(MIN_SEQ_LEN, TEXT_DATA_DIR + TEXT_DATA)
self.prepare_emb(EMBEDDING_DIM, MAX_LEN)
predict_model = None
if predict_path is None:
model_params = {
'lstm': [16],
'merge_layer': 'concat',
'dense': {
'size': [64, 32],
'act': 'elu',
'dropout': 0
},
'optimizer': 'adam',
'lr': 0.0005
}
predict_model = self.train_predict_model(model_params)
else:
pass
#predict_model = self.load_predict_model(predict_path)
#smoother_model = None
if smoother_path is None:
model_params = {'size': [64, 64], 'lr': 0.01}
#smoother_model = self.train_dac_model(model_params)
else:
self.dac = DAC()
self.dac.load_model(smoother_path)
#GENERATE PUN
while True:
try:
final = pungen.form_pun(eval_path)
break
except Exception:
pass
print(final)
###############################################################################
# SCHEDULER
##########
# You shall modify speedCoeff only
###############################################################################
scheduler = Scheduler(speedCoeff=1)
###############################################################################
# REGISTERS
##########
# Add registers like that : reg = Register("NAME")
###############################################################################
###############################################################################
# ECUS
##########
# You should always add registers in same order. Else there is an overlap.
# TODO I want to find out how to add registers with no order constraint
###############################################################################
allEcus = [
Ecu("../examples/viper2/App-GBF/trampoline", scheduler, [
Timer("TIMER0", 1, type=timer.AUTO, delay=10),
DAC("DAC0", 2, position=[0, 0]),
LCD("LCD1", 3, position=[360, 0]),
LCD("LCD2", 4, position=[360, 120]),
BP("BPPlus", 10, position=[360, 240], picture="pictures/BPPlus"),
BP("BPMinus", 11, position=[460, 240], picture="pictures/BPMinus"),
Power("POWER", 9),
])
]