def get_lm_equation(self, testname, dv, iv_list, mode={'dummy_digitalmode':0}):
_port = [iv[0] for iv in iv_list]
_varl = [iv[1] for iv in iv_list]
_terms = self.get_terms(testname, dv, mode)
_coefs = [self.get_lm_coef(testname, dv, iv, mode) for iv in _terms]
def get_unit_terms(term):
''' extact variables. For example, ctl1*ctl2 will produce [ctl1,ctl2] '''
return [f for f in term.split('*') if len(f) >0 and f[0].isalpha()]
all_terms = sorted(list(set(flatten_list([get_unit_terms(t) for t in _terms]))-set(['offset'])))
assert list(set(all_terms)-set(_port))==[], 'Lack of terms in get_lm_equation'
equation = ' + '.join(['%s*%s' %(str(_coefs[i]),t) if t!='offset' else str(_coefs[i]) for i,t in enumerate(_terms)]).replace('+-','-')+';'
for i,v in enumerate(_port):
equation = re.sub(r'\b%s\b' % v, _varl[i], equation)
return equation
def _build_formula_from_lr(self, model):
''' build a linear equation from linear regression result '''
dv = model.model.formula.split('~')[0]
pv = model.params.keys()
pv_expanded = list(set(flatten_list([s.split(':') for s in pv]))) # list of expanded predictors
qa_expanded = [s for k in self.quantizedport_name for s in pv_expanded if re.match(k+'_\d$', s)] # find terms quantized analog
coef = model.params.values
terms = ['%e*%s' %(coef[i], self._change_R_power_to_Vlog_power(pv[i]).replace(':','*')) for i in range(len(pv))]
terms[0] = terms[0].split('*')[0]
expr = dv+' = '+' + '.join(terms) #+';'
for q in qa_expanded: # change _\d$ with [\d]
k = q.rfind('_')
if self._ph.get_by_name(q[:k]).bit_width == 1: # if bit-width ==1, replace x[0] with x
expr = expr.replace(q,q[:k])
else:
expr = expr.replace(q, q[:k]+'['+q[k+1:]+']')
return expr
def _print_wires(self, tb_filename):
wires_declared = sorted([w.split()[-1] for w in self._test_cfg.get_wires()])
wires = []
for l in vp.getline_verilog(tb_filename):
if vp.is_instance(l):
portmap = vp.parse_port_map(l)
wires.append(portmap.values())
wires = sorted(list(set(flatten_list(wires))))
wire_matched = wires_declared == wires
def printable_wirename(wire_list):
return ["'%s'" % w for w in wire_list]
map(self._logger.info, print_section(mcode.INFO_034, 2))
self._logger.warn(mcode.WARN_006 % ', '.join(printable_wirename(wires)))
self._logger.warn(mcode.WARN_007 % ', '.join(printable_wirename(wires_declared)))
self._logger.warn(mcode.WARN_008 % ('matched' if wire_matched else 'unmatched'))
if wire_matched == False:
unmatched_wires = list(set(wires_declared)-set(wires))+list(set(wires)-set(wires_declared))
self._logger.warn(mcode.WARN_009 % ('s are' if len(unmatched_wires)>1 else ' is', ', '.join(printable_wirename(unmatched_wires))))
self._logger.warn(mcode.WARN_010)
def get_info_all(self): # print information of all ports to a logger
for p in flatten_list(self.get_name().values()):
self.get_info(p)
def _extract_all_wiretype(self, cfg):
''' extract all wire types '''
_wiretypes = list(
set(flatten_list([v.values() for k, v in self._map.items()])))
return list(set(merge_list(_wiretypes, [self._default])))
def load_test_vector(self, ph, workdir): # load dumped test vector
self._logger.info('\n' + mcode.INFO_042)
csv_d = os.path.join(workdir, EnvFileLoc().csv_vector_prefix+'_digital.csv') # for digital
csv_a = os.path.join(workdir, EnvFileLoc().csv_vector_prefix+'_analog.csv') # for analog
assert_file(csv_d)
assert_file(csv_a)
self._logger.debug(' - %s' % csv_d)
self._logger.debug(' - %s' % csv_a)
df = pd.read_csv(csv_a)
self._a_vector = dict([ (k, self.conv_frombin(ph, k, df[k])) for k in df.keys() if k in flatten_list(ph.get_name().values()) ])
df = pd.read_csv(csv_d)
self._d_vector = dict([ (k, self.conv_frombin(ph, k, df[k])) for k in df.keys() if k in flatten_list(ph.get_name().values()) ])
def get_wires(self):
''' return list of wires declared in wire section '''
return list(
set(
flatten_list(self.get_testbench()[self._tenvs.wire][
self._tenvtb.model_ams].values())))