def __init__(self, instanceName):
"""
Here the Element constructor must be called. Do not connect
internal nodes here.
"""
cir.Element.__init__(self, instanceName)
self.diogs = Junction()
self.diogd = Junction()
def __init__(self, instanceName):
cir.Element.__init__(self, instanceName)
# Use junctions to model diodes and capacitors
self.jif = SVJunction()
self.jir = SVJunction()
self.jile = Junction()
self.jilc = Junction()
# collector/emitter terminal numbers: may be re-mapped by
# extrinsic device
self._ct = 0
self._et = 2
def process_params(self, thermal=False):
# Remove tape if present
ad.delete_tape(self)
# Remove internal terminals (there should be none created
# by intrinsic model)
self.clean_internal_terms()
# Tell autothermal (if used) to re-generate thermal ports
self.__addThermalPorts = True
# By default drain and source are terminals 0 and 2
self.__di = 0
self.__si = 2
# Resistances
extraVCCS = list()
if self.rsh != 0.:
if self.nrd != 0.:
# Drain resistor
self.__di = self.add_internal_term('di', 'V')
extraVCCS += [((0, self.__di), (0, self.__di),
1. / self.rsh / self.nrd)]
if self.nrs != 0.:
# Source resistor
self.__si = self.add_internal_term('si', 'V')
extraVCCS += [((2, self.__si), (2, self.__si),
1. / self.rsh / self.nrs)]
# Linear capacitances
extraVCQS = list()
if self.cgdo != 0.:
# Gate-drain ovelrlap cap
extraVCQS += [((1, self.__di), (1, self.__di),
self.cgdo * self.w)]
if self.cgso != 0.:
# Gate-source ovelrlap cap
extraVCQS += [((1, self.__si), (1, self.__si),
self.cgso * self.w)]
if self.cgbo != 0.:
# Gate-bulk ovelrlap cap
extraVCQS += [((1, 3), (1, 3), self.cgbo * self.l)]
# Add extra linear resistors/caps (if any)
self.linearVCCS = extraVCCS
self.linearVCQS = extraVCQS
# Override nonlinear port specs if needed
if extraVCCS:
# Ids, Idb, Isb
self.csOutPorts = [(self.__di, self.__si), (self.__di, 3),
(self.__si, 3)]
# Controling voltages are DB, GB and SB
self.controlPorts = [(self.__di, 3), (1, 3), (self.__si, 3)]
# One charge source connected to each D, G, S
self.qsOutPorts = [(self.__di, 3), (1, 3), (self.__si, 3)]
# Calculate some variables (that may also be calculated in
# intrinsic model)
self.__Tnabs = const.T0 + self.tnom
self.__egapn = self.eg0 - .000702 * (self.__Tnabs**2) \
/ (self.__Tnabs + 1108.)
# Initialize variables in junctions
if self.ad != 0.:
self.dj = Junction()
self.dj.process_params(isat=self.js * self.ad,
cj0=self.cj * self.ad,
vj=self.pb,
m=self.mj,
n=1.,
fc=self.fc,
xti=self.xti,
eg0=self.eg0,
Tnomabs=self.__Tnabs)
if self.asrc != 0.:
self.sj = Junction()
self.sj.process_params(isat=self.js * self.asrc,
cj0=self.cj * self.asrc,
vj=self.pb,
m=self.mj,
n=1.,
fc=self.fc,
xti=self.xti,
eg0=self.eg0,
Tnomabs=self.__Tnabs)
if self.pd != 0.:
self.djsw = Junction()
self.djsw.process_params(isat=self.jssw * self.pd,
cj0=self.cjsw * self.pd,
vj=self.pbsw,
m=self.mjsw,
n=1.,
fc=self.fc,
xti=self.xti,
eg0=self.eg0,
Tnomabs=self.__Tnabs)
if self.ps != 0.:
self.sjsw = Junction()
self.sjsw.process_params(isat=self.jssw * self.ps,
cj0=self.cjsw * self.ps,
vj=self.pbsw,
m=self.mjsw,
n=1.,
fc=self.fc,
xti=self.xti,
eg0=self.eg0,
Tnomabs=self.__Tnabs)
# Process parameters from intrinsic device:
# set_temp_vars() called there
IMOS.process_params(self)
def __init__(self, instanceName):
IBJT.__init__(self, instanceName)
# Collector-bulk junction
self.cbjtn = Junction()
self.__doc__ += IBJT.__doc__
