def _init_gpio():
ret_value = True
initconfig = Profile.get_initconfig()
digital_io = Profile.get_ioes()
if 'gpio' in initconfig.keys():
for io_id, param in initconfig['gpio'].iteritems():
try:
device_path = digital_io[io_id]['path']
if Exgpio.dir_set(device_path, (param['dir'], )) is not False:
logger.boot(
'set the %s gpio number %s direction:%s success' %
(io_id, param['dir'][0], param['dir'][1]))
if 'value' in param.keys():
if Exgpio.set(device_path,
(param['value'], )) is not False:
logger.boot(
'set the %s gpio number %s value:%s success' %
(io_id, param['value'][0], param['value'][1]))
else:
logger.boot(
'warning: set the %s gpio number %s value:%s fail'
%
(io_id, param['value'][0], param['value'][1]))
ret_value = False
else:
logger.boot(
'warning the %s gpio number %s direction:%s fail' %
(io_id, param['dir'][0], param['dir'][1]))
ret_value = False
except Exception as e:
logger.boot("error: %s _init_gpio execute error:\n%s" %
(io_id, traceback.format_exc()))
ret_value = False
return ret_value
def test_get_eeprom_by_name():
#test eeprom
base_board_eeprom = Profile.get_eeprom_by_name('TB_EEPROM')
assert base_board_eeprom['bus'] == '/dev/AXI4_EEPROM_IIC'
assert base_board_eeprom['addr'] == int('0x50', 16)
assert base_board_eeprom['partno'] == 'CAT24C08'
assert base_board_eeprom['switch_channel'] == 'TB'
datalogger_eeprom = Profile.get_eeprom_by_name('datalogger')
assert datalogger_eeprom['bus'] == '/dev/AXI4_EEPROM_IIC'
assert datalogger_eeprom['addr'] == int('0x53', 16)
assert datalogger_eeprom['partno'] == 'CAT24C08'
assert datalogger_eeprom['switch_channel'] == 'Datalogger-1'
eload_1_eeprom = Profile.get_eeprom_by_name('ELOAD1')
assert eload_1_eeprom['bus'] == '/dev/AXI4_ELOAD_IIC'
assert eload_1_eeprom['addr'] == int('0x53', 16)
assert eload_1_eeprom['partno'] == 'CAT24C08'
assert eload_1_eeprom['switch_channel'] == "none"
try:
Profile.get_eeprom_by_name('SPAM')['bus']
except KeyError:
assert True
else:
assert False
def parse_chip_profile(chip_profile, board_name):
chip_id = chip_profile['id']
eeprofile = Profile.get_eeprom()
eeprofile[chip_id] = dict()
for key, value in chip_profile.iteritems():
eeprofile[chip_id][key] = copy.deepcopy(value)
eeprofile[chip_id]['bus'] = Profile.get_bus_path(chip_profile['bus'])
eeprofile[chip_id]['addr'] = int(chip_profile['addr'], 16)
def spi_config(bus_name,
clk_frequency,
clk_type,
wait_time_us=1,
spi_clk_polarity='high'):
logger.warning(
"spi config -->bus_name:%s, clk_frequency:%s, clk_type:%s, wait_time_us:%s "
% (bus_name, clk_frequency, clk_type, wait_time_us))
""" Set spi bus parameter
Args:
spi_clk_frequency(int): spi bus clock frequency, unit is Hz
spi_clk_type(str): 'pos' --sclk posedge send data, sclk negedge receive data
'neg' --sclk negedge send data, sclk posedge receive data
wait_time_us(float): the wait time for new spi access
spi_clk_polarity(str): 'high' --when CS is high, the SCLK is high
'low' --when CS is high, the SCLK is low
Returns:
None
"""
try:
profile = Profile.get_bus_by_name(bus_name)
bus = SpiFactory.create_object(SpiFactory, profile["path"])
return bus.config(clk_frequency, clk_type, wait_time_us,
spi_clk_polarity)
except Exception as e:
logger.error("execute module spi_config False:" + repr(e))
return False
def test_get_busswitch_by_name():
#test busswitch
TB_channel = Profile.get_busswitch_by_name('TB')
TB_chip = Profile.get_busswitch_by_name(TB_channel['chip'])
assert TB_chip['partno'] == 'TCA9548'
assert TB_chip['addr'] == int('0x71', 16)
assert TB_chip['bus'] == '/dev/AXI4_EEPROM_IIC'
assert Profile.get_busswitch_by_name('TB')['channel'] == 0
assert Profile.get_busswitch_by_name('DMM_1')['channel'] == 1
assert Profile.get_busswitch_by_name('CODEC_1')['channel'] == 2
assert Profile.get_busswitch_by_name('Datalogger_1')['channel'] == 3
assert Profile.get_busswitch_by_name('BK')['channel'] == 4
assert Profile.get_busswitch_by_name('Power_EEPROM')['channel'] == 5
assert Profile.get_busswitch_by_name('DIGIPOT')['channel'] == 6
assert Profile.get_busswitch_by_name('POWER_DIGIPOT')['channel'] == 7
def _create_uart_object():
ret_value = True
for bus_name, bus in Profile.get_buses().iteritems():
try:
if bus['bus'] == 'uart':
device_path = bus['path']
if utility.mount_on_fpga(device_path):
class_name = 'Axi4Uart'
createok = XObject.create_object(bus_name, class_name,
device_path)
else:
class_name = 'UartBus'
createok = XObject.create_object(bus_name, class_name,
device_path)
if createok:
logger.boot("create the %s uart object %s" %
(bus_name, class_name))
else:
logger.boot(
"warning: can not find the %s uart class %s in this project code"
% (bus_name, class_name))
ret_value = False
except Exception as e:
logger.boot("error: create %s uart object fail:\n%s" %
(bus_name, traceback.format_exc()))
ret_value = False
return ret_value
def parse_board_profile(board):
'''
"DATALOGGER": {
"id": "DATALOGGER",
"partno": "Scope-002-001",
"daq_channel":[
{"ch": 0, "alias": "volt", "port": 7603},
{"ch": 1, "alias": "current", "port": 7604}
],
"adc": {"partno": "AD7175", "path": "/dev/AXI4_DATALOGGER_AD7177"},
"eeprom": {"partno": "CAT24C08", "bus": "EEPROM_IIC", "switch_channel": "Datalogger-1", "addr": "0x53"}
}
'''
board_name = board['id']
boards = Profile.get_boards()
boards[board_name] = dict()
boards[board_name]['id'] = board_name
boards[board_name]['partno'] = board['partno']
boards[board_name]['adc'] = board['adc'].copy()
boards[board_name]['adc']['path'] = Utility.get_dev_path(
) + '/' + board['adc']['path']
boards[board_name]['daq_channel'] = copy.deepcopy(board['daq_channel'])
boards[board_name]['frame_device_path'] = Utility.get_dev_path(
) + '/' + board['frame_device_path']
def io_dir_get(board_name, *bits):
""" Get the IO pins dir state from dev
Args:
board_name: str type , board name.
bits: can be a multi-parameter.
eg: bit8, bit9,bit181 , ...
or
list type .format: ["bitX", "bitX", ...]
X:(1- )
returns:
dict type: format: {'bitX': Y, "bitX":Y, ...}
X: (1- )
Y: 1 or 1
"""
bit_state_dict = OrderedDict()
try:
ioprofile = Profile.get_extendio_by_name(board_name)
bit_state_dict = Extendio.dir_get(ioprofile, bits)
except Exception as e:
logger.error("execute module io io_dir_get error:" + repr(e))
bit_state_dict["error"] = 0
return bit_state_dict
def io_chip_dir_get(board_name, *chipname):
""" Get the CHIP pins dir state from dev
Args:
board_name: str type , board name.
chipname: list type, format: ["cpX", "cpX", ...]
X:[1- ]
Which io chip name state we will get .
Returns:
dict type: {"cpX": Y}, "cpX": Y, "cpX": False...}
X:[1- ]
Y: 16bit: [0x0000 - 0xffff]
24bit:[0x000000 - 0xffffff]
eg: cp5 read false returns: {"cp5": False,}
"""
chip_state_dict = OrderedDict()
ioprofile = Profile.get_extendio_by_name(board_name)
for name in chipname:
try:
chip_state_dict[name] = Extendio.chip_dir_get(ioprofile, name)
except Exception as e:
logger.error("execute module io io_chip_dir_get False:" + repr(e))
chip_state_dict[name] = False
return chip_state_dict
def spi_slave_enable(bus_name):
logger.debug("spi slave enable -->bus name:%s "%(bus_name))
try:
profile = Profile.get_bus_by_name(bus_name)
bus = SpiSlaveFactory.create_object(SpiSlaveFactory, profile["path"])
return bus.enable()
except Exception as e:
logger.error("execute module spi_slave_enable False:" + repr(e))
return False
def __init__(self, name, channel=None):
self._name = name
self._profile = Profile.get_bus_by_path(name)
self._channel = None if channel == 'none' else channel
if utility.mount_on_fpga(name) is None:
self._bus = CI2cBus(name)
else:
self._bus = Axi4I2c(name)
self._bus.config(int(self._profile["rate"]))
def spi_disable(bus_name):
logger.warning("spi disable -->bus name:%s " % (bus_name))
try:
profile = Profile.get_bus_by_name(bus_name)
bus = SpiFactory.create_object(SpiFactory, profile["path"])
return bus.disable()
except Exception as e:
logger.error("execute module spi_disable False:" + repr(e))
return False
def parse_chip_profile(chip_profile, board_name):
chipname = chip_profile['id']
extendios = Profile.get_extendio()
extendios[board_name] = extendios.setdefault(board_name, OrderedDict())
extendio = extendios[board_name]
extendio[chipname] = dict()
extendio[chipname]['bus'] = Profile.get_bus_path(chip_profile['bus'])
extendio[chipname]['addr'] = int(chip_profile['addr'], 16)
extendio[chipname]['partno'] = chip_profile['partno']
extendio[chipname]['switch_channel'] = chip_profile['switch_channel']
chips = Profile.get_chips()
chips[chipname] = extendio[chipname]
bit_values = 0
bit_dir = 0
dir_value = {'input': 1, 'output': 0}
for pin in chip_profile['property']:
pinname = pin['id']
extendio[pinname] = dict()
extendio[pinname]['pin'] = pin['pin']
extendio[pinname]['chip'] = chipname
if 'default' in pin.keys():
bit_values |= (int(pin['default']) << (int(pin['pin']) - 1))
if 'dir' in pin.keys():
bit_dir |= (dir_value[pin['dir']] << (int(pin['pin']) - 1))
value_list = []
dir_list = []
for x in xrange(len(chip_profile['property']) / 8):
value_list.append((bit_values >> (x * 8)) & 0xff)
dir_list.append((bit_dir >> (x * 8)) & 0xff)
initconfig = Profile.get_initconfig()
initconfig['extendio'] = initconfig.setdefault('extendio',
OrderedDict())
initconfig['extendio'][board_name] = initconfig['extendio'].setdefault(
board_name, OrderedDict())
initconfig['extendio'][board_name][chipname] = dict(dir=dir_list,
value=value_list)
def test_get_extendio_by_name():
base_board_extendio = Profile.get_extendio_by_name('instrument')
extendio_8 = base_board_extendio['cp8']
assert extendio_8['partno'] == 'CAT9555'
assert extendio_8['bus'] == '/dev/i2c-0'
assert extendio_8['addr'] == int('0x07', 16)
assert extendio_8['switch_channel'] == 'none'
bit128 = base_board_extendio['bit128']
assert bit128['pin'] == '16'
assert bit128['chip'] == 'cp8'
def test_get_extendio():
extendioes = Profile.get_extendio()
extendio = extendioes['instrument']
extendio_2 = extendio['cp2']
assert extendio_2['partno'] == 'CAT9555'
assert extendio_2['bus'] == '/dev/i2c-0'
assert extendio_2['addr'] == int('0x01', 16)
assert extendio_2['switch_channel'] == 'none'
bit30 = extendio['bit30']
assert bit30['pin'] == '14'
assert bit30['chip'] == 'cp2'
def test_initconfig():
initconfig = Profile.get_initconfig()
assert len(initconfig['extendio']['instrument']) == 8
assert len(initconfig['boards']) == 4
assert initconfig['extendio']['instrument']['cp1']['value'][0] == int(
'0x0', 16)
assert initconfig['extendio']['instrument']['cp1']['value'][1] == int(
'0x0', 16)
assert initconfig['extendio']['instrument']['cp1']['dir'][0] == int(
'0x1f', 16)
assert initconfig['extendio']['instrument']['cp1']['dir'][1] == int(
'0x0', 16)
def _init_extendio():
ret_value = True
extendios = Profile.get_extendio()
initconfig = Profile.get_initconfig()
for board_name, extendio_profile in extendios.iteritems():
for chip_name, bit in initconfig['extendio'][board_name].iteritems():
try:
partno = extendio_profile[chip_name]['partno']
if Extendio.chip_dir_set(extendio_profile, chip_name,
bit['dir']) is True:
ret = Extendio.chip_set(extendio_profile, chip_name,
bit['value'])
if ret is False:
logger.boot(
'error: set the %s board %s chip %s value:%s fail'
% (board_name, partno, chip_name,
logger.print_list2hex(bit['value'])))
ret_value = False
else:
logger.boot(
'init the %s board extendio chip %s success, value is %s, direction is %s'
% (board_name, chip_name,
logger.print_list2hex(bit['value']),
logger.print_list2hex(bit['dir'])))
else:
logger.boot(
'error: set the %s board %s chip %s direction:%s fail'
% (board_name, partno, chip_name,
logger.print_list2hex(bit['dir'])))
ret_value = False
except Exception:
logger.boot("error: %s _init_extendio execute error:\n%s" %
(chip_name, traceback.format_exc()))
ret_value = False
return ret_value
def test_get_bus_by_name():
ps_i2c_0 = Profile.get_bus_by_name('ps_i2c_0')
assert ps_i2c_0['bus'] == 'i2c'
assert ps_i2c_0['path'] == '/dev/i2c-0'
assert ps_i2c_0['rate'] == '100000'
UUT_UART = Profile.get_bus_by_name('UUT_UART')
assert UUT_UART['bus'] == 'uart'
assert UUT_UART['path'] == '/dev/AXI4_UUT_UART'
assert UUT_UART['baudrate'] == '115200'
assert UUT_UART['ipcore'] == 'Axi4Uart'
INSTRUMENT_IIC_2 = Profile.get_bus_by_name('INSTRUMENT_IIC_2')
assert INSTRUMENT_IIC_2['bus'] == 'i2c'
assert INSTRUMENT_IIC_2['path'] == '/dev/AXI4_INSTRUMENT_IIC_2'
assert INSTRUMENT_IIC_2['rate'] == '400000'
assert INSTRUMENT_IIC_2['ipcore'] == 'Axi4I2c'
EEPROM_IIC = Profile.get_bus_by_name('EEPROM_IIC')
assert EEPROM_IIC['bus'] == 'i2c'
assert EEPROM_IIC['path'] == '/dev/AXI4_EEPROM_IIC'
assert EEPROM_IIC['rate'] == '400000'
assert EEPROM_IIC['ipcore'] == 'Axi4I2c'
def init():
initok = True
logger.boot('start init')
if _create_chip_object() is False:
initok = False
if _create_board_object() is False:
initok = False
if _create_uart_object() is False:
initok = False
initconfig = Profile.get_initconfig()
#init gpio
if _init_gpio() is False:
initok = False
#initexitendio
if initconfig.has_key('extendio'):
if _init_extendio() is False:
initok = False
#init board
if initconfig.has_key('boards'):
if _init_board() is False:
initok = False
#init net
try:
if _init_net() is False:
initok = False
except Exception as e:
logger.boot("error: _init_net execute error:\n%s" %
(traceback.format_exc()))
initok = False
#init uart
if initconfig.has_key('uart'):
if _init_uart() is False:
initok = False
if not initok:
logger.boot('error: init project fail')
else:
logger.boot("init project done")
return initok
def swd_freq_set(bus_id, freq_data):
logger.warning("swd freq set ---> %s" % list((bus_id, freq_data)))
""" Set swd clk freq parameter
Args:
freq_data(int): swd bus clock frequency, unit is Hz
Returns:
None
"""
try:
profile = Profile.get_bus_by_name(bus_id)
bus = SwdFactory.create_object(SwdFactory, profile["path"])
return bus.swd_freq_set(freq_data)
except Exception as e:
logger.error("execute module swd freq set False:" + repr(e))
return False
def swd_rst_set(bus_id, level):
logger.warning("swd rst set ---> %s" % list((bus_id, level)))
""" swd debug rst ctrl
Args:
level(string): 'L'--Low level,'H'--High level
Returns:
None
"""
try:
profile = Profile.get_bus_by_name(bus_id)
bus = SwdFactory.create_object(SwdFactory, profile["path"])
return bus.swd_rst_pin_ctrl(level)
except Exception as e:
logger.error("execute module swd rst set False:" + repr(e))
return False
return False
def test_read_profile(jsonfile):
classes = globals()
XObject.set_classes(classes)
parser = ProfileParser()
parser.read_profile(jsonfile)
boards = Profile.get_boards()
boards[power_profile['id']] = power_profile
assert len(Profile.get_extendio()) == 1
assert len(Profile.get_busswitch()) == 9
assert len(Profile.get_eeprom()) == 8
assert len(Profile.get_boards()) == 5
assert len(Profile.get_buses()) == 8
assert len(Profile.get_chips()) == 12
def swd_timing_generate(bus_id, timing_data):
logger.warning("swd timing generate ---> %s, len:%s" %
([('0x%02x' % i) for i in timing_data], len(timing_data)))
""" swd_switch_timing_generate
Args:
timing_data(list): timing_data, bit order: first_byte_bit0-->bit7,second_byte_bit0-->bit7,...,last_byte_bit0-->bit7
Returns:
False | True
"""
try:
profile = Profile.get_bus_by_name(bus_id)
bus = SwdFactory.create_object(SwdFactory, profile["path"])
return bus.swd_switch_timing_gen(timing_data)
except Exception as e:
logger.error("execute module swd rst set False:" + repr(e))
return False
return False
def io_dir_set(board_name, bits):
""" Set the IO DIR by the defined profile
Args:
board_name: str type , board name.
bits: dict type. format: {"bitX":Y, "bitX":Y, ...}
X: (1- )
Y: 1 or 0
Returns:
bool: The return value. True for success, False otherwise.
"""
try:
ioprofile = Profile.get_extendio_by_name(board_name)
return Extendio.dir_set(ioprofile, bits)
except Exception as e:
logger.error("execute module io io_dir_set error:" + repr(e))
return False
def _create_chip_object():
ret_value = True
for chip_name, profile in Profile.get_chips().iteritems():
try:
partno = profile['partno']
if XObject.create_object(chip_name, partno, profile):
logger.boot('create the %s chip object %s' %
(chip_name, partno))
else:
logger.boot(
'warning: can not find the %s chip class %s in this project code'
% (chip_name, partno))
ret_value = False
except Exception as e:
logger.boot('error: create %s chip object fail:\n%s' %
(chip_name, traceback.format_exc()))
ret_value = False
return ret_value
def _create_board_object():
ret_value = True
for board_name, board_profile in Profile.get_boards().iteritems():
try:
class_name = board_profile['partno'].replace('-', '')
if XObject.create_object(board_name, class_name, board_profile):
logger.boot('create the %s board object %s' %
(board_name, class_name))
else:
logger.boot(
'warning: can not find the %s board class %s in this project code'
% (board_name, class_name))
ret_value = False
except Exception as e:
logger.boot("error: create %s board object fail:\n%s" %
(board_name, traceback.format_exc()))
ret_value = False
return ret_value
def i2c_config(bus_id, rate):
logger.debug("bus:%s, rate:%s" % (bus_id, rate))
"""
Args:
bus_id: str type, i2c bus id.
rate: int type.
Returns:
return None
"""
try:
profile = Profile.get_bus_by_name(bus_id)
bus = I2cBus(profile["path"])
return bus.config(rate)
except Exception as e:
logger.error("execute module i2c config False:" + repr(e))
return False
def eeprom_read(module_name, addr, length):
""" read data by the defined profile
Args:
module_name: the key of Dictionary which can get the hardware profile.for example: "dmm-module-1"
addr: read data from this addr.
length: read data length.
Returns:
list: success return data which beed saved in a list. False otherwise.
"""
try:
profile = Profile.get_eeprom_by_name(module_name)
result = Eeprom.read(profile, addr, length)
except Exception as e:
logger.error("execute module eeprom_read False:" + repr(e))
return False
return result
def spi_slave_write(bus_name, address, write_data):
logger.debug("spi slave write -->bus name:%s, address:%s, write_data:%s "%(bus_name,address,write_data))
""" write data in spi bus
Args:
bus_name: str type, spi bus id.
address: int type
write_datas: list type.
Returns:
bool: The return value. True for success, False otherwise.
"""
try:
profile = Profile.get_bus_by_name(bus_name)
bus = SpiSlaveFactory.create_object(SpiSlaveFactory, profile["path"])
return bus.register_write(address, write_data)
except Exception as e:
logger.error("execute module spi_slave_write False:" + repr(e))
return False
def eeprom_write(module_name, addr, data):
""" write a list data by the defined profile
Args:
module_name: the key of Dictionary which can get the hardware profile.for example: "dmm-module-1"
addr: which addr will be write data in.
data: data type is list.
Returns:
bool: The return value. True for success, False otherwise.
"""
try:
profile = Profile.get_eeprom_by_name(module_name)
result = Eeprom.write(profile, addr, data)
except Exception as e:
logger.error("execute module eeprom_write False:" + repr(e))
return False
return result