class Foo(m.Circuit):
io = m.IO(a=m.In(m.Bits[8]),
b=m.In(m.Bits[8]),
c=m.In(m.Bits[8]),
x=m.Out(m.Bits[8]),
y=m.Out(m.Bits[8]))
io += m.ClockIO(has_resetn=True)
x = [m.bits(0, 8), m.bits(0, 8), m.bits(1, 8), m.bits(0, 8)]
if should_pass:
y = [m.bits(0, 8), m.bits(1, 8), m.bits(2, 8), m.bits(3, 8)]
else:
y = [m.bits(1, 8), m.bits(1, 8), m.bits(1, 8), m.bits(1, 8)]
count = m.Register(m.Bits[2])()
count.I @= count.O + 1
io.x @= m.mux(x, count.O)
io.y @= m.mux(y, count.O)
m.display("io.x=%x, io.y=%x", io.x, io.y).when(m.posedge(io.CLK))
if use_sva:
f.assert_(f.sva(f.not_(f.onehot(io.a)), "&&", io.b.reduce_or(),
"&&", io.x[0].value(), "|=>",
io.y.value() != f.past(io.y.value(), 2)),
name="name_A",
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
else:
f.assert_(
# Note parens matter!
(f.not_(f.onehot(io.a)) & io.b.reduce_or() & io.x[0].value())
| f.implies | f.delay[1] | (io.y != f.past(io.y.value(), 2)),
name="name_A",
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
class Main(m.Circuit):
io = m.IO(a=m.In(m.Bit), b=m.In(m.Bit), c=m.In(m.Bit)) + m.ClockIO()
if sva:
seq = f.sequence(f.sva(io.b, "until_with !", io.c))
f.assert_(f.sva(f.rose(io.a), "|->", seq), on=f.posedge(io.CLK))
else:
seq = f.sequence(io.b | f.until_with | f.not_(io.c))
f.assert_(f.rose(io.a) | f.implies | seq, on=f.posedge(io.CLK))
class Main(m.Circuit):
io = m.IO(I=m.In(m.Bits[8]), x=m.In(m.Bit)) + m.ClockIO()
if use_sva:
f.assert_(f.sva(f.not_(f.onehot(io.I)), "|-> ##1", io.x),
on=f.posedge(io.CLK))
else:
f.assert_(f.not_(f.onehot(io.I)) | f.implies | f.delay[1] | io.x,
on=f.posedge(io.CLK))
class Main(m.Circuit):
io = m.IO(a=m.In(m.Bit), b=m.In(m.Bit), c=m.In(m.Bit)) + m.ClockIO()
if sva:
seq = f.sva(io.b, "throughout", "!", io.c, "[-> 1]")
f.assert_(f.sva(f.rose(io.a), "|->", seq), on=f.posedge(io.CLK))
else:
seq = io.b | f.throughout | f.not_(io.c | f.goto[1])
f.assert_(f.rose(io.a) | f.implies | seq, on=f.posedge(io.CLK))
class Main(m.Circuit):
io = m.IO(a=m.In(m.Bit), b=m.In(m.Bit))
io += m.ClockIO(has_resetn=True)
f.assert_(io.a | f.implies | f.delay[2] | io.b,
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
f.assert_(f.sva(io.a, "|-> ##2", io.b),
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
class Main(m.Circuit):
io = m.IO(write=m.In(m.Bit), read=m.In(m.Bit)) + m.ClockIO()
if sva:
f.assert_(f.sva(io.write == 1, f"|-> s_eventually", io.read == 1),
on=f.posedge(io.CLK))
else:
f.assert_(
(io.write == 1) | f.implies | f.eventually | (io.read == 1),
on=f.posedge(io.CLK))
class Main(m.Circuit):
io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8])) + m.ClockIO()
io.O @= m.Register(T=m.Bits[8])()(io.I)
if sva:
f.assert_(f.sva(io.I, "|-> ##1",
io.O.value() == 0),
on=f.posedge(io.CLK))
else:
f.assert_(io.I | f.implies | f.delay[1] | (io.O.value() == 0),
on=f.posedge(io.CLK))
class Main(m.Circuit):
io = m.IO(write=m.In(m.Bit), read=m.In(m.Bit)) + m.ClockIO()
if sva:
symb = num_reps
if isinstance(symb, slice):
symb = f"{symb.start}:{symb.stop}"
f.assert_(f.sva(io.write == 1, f"[-> {symb}]", '##1', io.read,
'##1', io.write),
on=f.posedge(io.CLK))
else:
f.assert_((io.write == 1) | f.goto[num_reps] | f.delay[1] | io.read
| f.delay[1] | io.write,
on=f.posedge(io.CLK))
class Main(m.Circuit):
io = m.IO(write=m.In(m.Bit), read=m.In(m.Bit)) + m.ClockIO()
if sva:
seq0 = f.sva(~io.read, "##1", io.write)
seq1 = f.sva(io.read, "##1", io.write)
symb = "*" if zero_or_one == 0 else "+"
f.assert_(f.sva(seq0, "|-> ##1", io.read, f"[{symb}] ##1", seq1),
on=f.posedge(io.CLK))
else:
seq0 = ~io.read | f.delay[1] | io.write
seq1 = io.read | f.delay[1] | io.write
f.assert_(seq0 | f.implies | f.delay[1] | io.read
| f.repeat[zero_or_one:] | f.delay[1] | seq1,
on=f.posedge(io.CLK))
class Main(m.Circuit):
io = m.IO(a=m.In(m.Bit), b=m.In(m.Bit))
io += m.ClockIO(has_resetn=True)
f.assert_(io.a | f.implies | f.delay[2] | io.b,
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN),
compile_guard=compile_guard,
name="foo")
temp = m.Bit(name="temp")
temp @= io.a
f.assert_(f.sva(temp, "|-> ##2", io.b),
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN),
compile_guard=compile_guard,
name="bar")
class Main(m.Circuit):
io = m.IO(write=m.In(m.Bit), read=m.In(m.Bit)) + m.ClockIO()
N = 2
if sva:
seq0 = f.sequence(f.sva(~io.read, "##1", io.write))
seq1 = f.sequence(f.sva(io.read, "##1", io.write))
f.assert_(f.sva(~io.read & ~io.write, "[*2] |->", seq0,
f"[*{N}] ##1", seq1),
on=f.posedge(io.CLK))
else:
seq0 = f.sequence(~io.read | f.delay[1] | io.write)
seq1 = f.sequence(io.read | f.delay[1] | io.write)
f.assert_(~io.read & ~io.write | f.repeat[2] | f.implies | seq0
| f.repeat[N] | f.delay[1] | seq1,
on=f.posedge(io.CLK))
def my_assert(property, on=None, disable_iff=None):
# If needed, create undriven clock/reset temporaries, will be driven by
# automatic clock wiring logic
if on is None:
on = f.posedge(m.Clock())
if disable_iff is None:
disable_iff = f.not_(m.AsyncResetN())
f.assert_(property, on=on, disable_iff=disable_iff)
class Foo(m.Circuit):
io = m.IO(valid=m.In(m.Bit),
sop=m.In(m.Bit),
eop=m.In(m.Bit),
ready=m.Out(m.Bit)) + m.ClockIO(has_resetn=True)
io.ready @= 1
if use_sva:
f.assert_(
f.sva(
f.not_(~(io.valid & io.ready.value() & io.eop)),
"throughout",
# Note: need sequence here to wrap parens
f.sequence(
f.sva((io.valid & io.ready.value() & io.sop),
"[-> 2]"))),
name="eop_must_happen_btn_two_sop_A",
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
f.assert_(f.sva(io.valid & io.ready.value() & io.eop, "##1",
~io.valid, "[*0:$] ##1", io.valid, "|->", io.sop),
name="first_valid_after_eop_must_have_sop_A",
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
else:
f.assert_(f.not_(~(io.valid & io.ready.value() & io.eop))
| f.throughout |
((io.valid & io.ready.value() & io.sop) | f.goto[2]),
name="eop_must_happen_btn_two_sop_A",
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
f.assert_((io.valid & io.ready.value() & io.eop) | f.delay[1] |
(~io.valid) | f.repeat[0:] | f.delay[1] |
(io.valid | f.implies | io.sop),
name="first_valid_after_eop_must_have_sop_A",
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
class Main(m.Circuit):
io = m.IO(write=m.In(m.Bit), read=m.In(m.Bit)) + m.ClockIO()
if sva:
f.assert_(f.sva(io.write, "|-> ##[1:2]", io.read),
on=f.posedge(io.CLK))
f.assert_(f.sva(io.write, "|-> ##[*]", io.read),
on=f.posedge(io.CLK))
f.assert_(f.sva(io.write, "|-> ##[+]", io.read),
on=f.posedge(io.CLK))
else:
f.assert_(io.write | f.implies | f.delay[1:2] | io.read,
on=f.posedge(io.CLK))
f.assert_(io.write | f.implies | f.delay[0:] | io.read,
on=f.posedge(io.CLK))
f.assert_(io.write | f.implies | f.delay[1:] | io.read,
on=f.posedge(io.CLK))
class Main(m.Circuit):
io = m.IO(I=m.In(m.Bit), O=m.Out(m.Bit)) + m.ClockIO()
io.O @= m.Register(T=m.Bit)()(io.I)
f.assume(io.I | f.delay[1] | ~io.I, on=f.posedge(io.CLK))
class Main(m.Circuit):
io = m.IO(a=m.In(m.Bits[2])) + m.ClockIO()
if sva:
f.assert_(f.sva(io.a, "inside {0, 1}"), on=f.posedge(io.CLK))
else:
f.assert_(io.a | f.inside | {0, 1}, on=f.posedge(io.CLK))
